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Commenced Publication in 2007Founding and Former Series Editors:Alfredo Cuzzocrea, Xiaoyong Du, Orhun Kara, Ting Liu, Dominik Ślęzak,and Xiaokang Yang

Editorial Board

Simone Diniz Junqueira BarbosaPontifical Catholic University of Rio de Janeiro (PUC-Rio),Rio de Janeiro, Brazil

Phoebe ChenLa Trobe University, Melbourne, Australia

Joaquim FilipePolytechnic Institute of Setúbal, Setúbal, Portugal

Igor KotenkoSt. Petersburg Institute for Informatics and Automation of the RussianAcademy of Sciences, St. Petersburg, Russia

Krishna M. SivalingamIndian Institute of Technology Madras, Chennai, India

Takashi WashioOsaka University, Osaka, Japan

Junsong YuanNanyang Technological University, Singapore, Singapore

Lizhu ZhouTsinghua University, Beijing, China

More information about this series at http://www.springer.com/series/7899

Brajesh Kumar Kaushik • Sudeb DasguptaVirendra Singh (Eds.)

VLSI Design and Test21st International Symposium, VDAT 2017Roorkee, India, June 29 – July 2, 2017Revised Selected Papers

123

EditorsBrajesh Kumar KaushikIndian Institute of Technology RoorkeeRoorkeeIndia

Sudeb DasguptaIndian Institute of Technology RoorkeeRoorkeeIndia

Virendra SinghIndian Institute of Technology BombayMumbaiIndia

ISSN 1865-0929 ISSN 1865-0937 (electronic)Communications in Computer and Information ScienceISBN 978-981-10-7469-1 ISBN 978-981-10-7470-7 (eBook)https://doi.org/10.1007/978-981-10-7470-7

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Preface

VLSI Design and Test (VDAT) is a leading event of the VLSI Society of India. The21st symposium in this series, the VLSI Design and Test Symposium (VDAT 2017),was held from June 29 to July 2, 2017, at the Indian Institute of Technology Roorkee,India. The objective of the symposium is to bring professional engineers, academics,and researchers from India and abroad to discuss emerging topics of VLSI and relatedfields on a common platform and to share new ideas, experiences, and knowledge. Thechief guest at the event was Dr. V. K. Saraswat, Padma Shri, Padma Bhushan,Member NITI Aayog.

The scientific program consisted of peer-reviewed paper presentations in paralleltechnical sessions. In addition, keynote lectures, presentations by industry profes-sionals, panel discussions, tutorials, and a poster presentation were conducted duringthe conference. Research contributions in the following areas were invited for VDAT2017:

1. Digital Design2. Analog/Mixed Signal3. VLSI Testing4. Devices and Technology – I5. VLSI Architectures6. Emerging Technologies and Memory7. Devices and Technology – II8. System Design9. Low Power Design and Test

10. RF Circuits11. Architecture and CAD12. Design Verification

This year we received 246 papers from around the world. After a rigorous reviewprocess, the Program Committee selected 48 regular papers and 27 short papers for theproceedings (the acceptance rate was 30%). In all, 150 expert reviewers were involvedin rating the papers and on an average each paper received at least three independentreviews. The program of the symposium spanned over four days; the main conferenceprogram was preceded by a day of tutorial presentations that had six tutorials deliveredby eminent researchers and practitioners in the field. The symposium hosted thefollowing tutorials:

1. Gauri Sankar Malla, “Achieving the Best STA Accuracy for Advanced Nodes.”2. N. R. Mohapatra and Mr. Pardeep Kumar, “Computational Lithography for

Advanced CMOS Nodes.”3. M. Hasan, “Circuit and System Design Issues for IoT Sensor Node.”4. K. Bhattacharya, “Design of Modern mm-Wave Transmitters and Power Amplifiers

in Silicon and FD SoI CMOS.”

5. Nishit Gupta and Deepak Jharodia, “Transaction Level Modelling with System Cfor System Level Design.”

6. H. S. Jatana and Ashutosh Yadav, “Advanced Analog Design.”

Several invited talks and keynote speeches were delivered by experts from India andabroad enlightening the participants on various aspects of emerging issues in VLSIresearch. These talks were delivered by Prof. P. Chakrabarti (IIT-BHU), Dr. DeveshDwivedi (Global Foundaries, Bangalore), Prof. Maryam Shojaei (IIT-Bombay),Dr. Sudarshan Kumar (HSMC), Mr. Subhasish Mukherjee (Cadence), Mr. Sanjay Gupta(Vice President and India Country Manager, NXP), and Prof. Masahiro Fujita (TokyoUniversity). VDAT 2017 was a focused research event encompassing themes related tovarious disciplines of VLSI.

We sincerely thank all the officials and sponsors for their support in recognizing thevalue of this conference. We would like to express our thanks to the keynote speakersand the tutorial speakers for kindly agreeing to deliver their lectures. Thanks to theauthors and reviewers of all the papers for their quality research work. We heartilythank every member of the Conference Committee for their unyielding support inmaking this event a success.

November 2017 Brajesh Kumar KaushikSudeb DasguptaVirendra Singh

VI Preface

Organization

VDAT 2017 was organized by the Department of Electronics and CommunicationEngineering, Indian Institute of Technology Roorkee, India.

Patron

Ajit Kumar Chaturvedi IIT Roorkee, India

Advisory Committee

Jaswinder Ahuja VLSI Society of India, IndiaVishwani D Agarwal Auburn University, USAManoj Sachdev University of Waterloo, CanadaV. Ramgopal Rao Indian Institute of Technology Delhi, IndiaKewal K. Saluja University of Wisconsin, Madison, USAKaustav Banerjee University of California, Santa Barbara, USADebashish Dutta R&D Group, Ministry of Electronics & IT,

Government of India

General Chairs

M. Jagadesh Kumar JNU, IndiaDebashis Ghosh ECE, IIT Roorkee, India

Publicity Chairs

Brajesh Kumar Kaushik IIT Roorkee, IndiaHafizur Rahaman IIEST, Shibpur, IndiaA. Panda NIST, India

Organization Chairs

Anand Bulusu IIT Roorkee, IndiaSanjeev Manhas IIT Roorkee, India

Program Chairs

Sudeb Dasgupta IIT Roorkee, IndiaVirendra Singh IIT Bombay, India

Tutorial Chairs

Bishnu Prasad Das IIT Roorkee, IndiaArnab Dutta IIT Roorkee, India

Fellowship Chairs

N. P. Pathak IIT Roorkee, IndiaMeenakshi Rawat IIT Roorkee, India

Transport Chairs

Rajib Panigrahi IIT Roorkee, IndiaPyari Mohan Pradhan IIT Roorkee, India

Website Chairs

Brijesh Kumar IIT Roorkee, IndiaR. Balasubramanian IIT Roorkee, India

Finance Chairs

M. V. Kartikeyan IIT Roorkee, IndiaA. Patnaik IIT Roorkee, IndiaBrijesh Kumar IIT Roorkee, India

Sponsorship Chairs

Sanjeev Manhas IIT Roorkee, IndiaBishnu Prasad Das IIT Roorkee, IndiaKarun Rawat IIT Roorkee, IndiaPreet Yadav NXP Semiconductors India Pvt. Ltd., IndiaGaurav Trivedi IIT Guwahati, India

Accommodations

Dharmendra Singh IIT Roorkee, IndiaMadhav. J. Nigam IIT Roorkee, IndiaVinod Pankajakshan IIT Roorkee, India

Publication Chairs

Brajesh Kumar Kaushik IIT Roorkee, IndiaSudip Roy IIT Roorkee, India

VIII Organization

Technical Program Committee

Amit Acharyya IIT Hyderabad, IndiaPratima Agarwal IIT Guwahati, IndiaS. R. Ahamed IIT Guwahati, IndiaSatyadev Ahlawat IIT Bombay, IndiaNaushad Alam AMU, Aligarh, IndiaSk Subidh Ali IIT Tirupati, IndiaSankaran Aniruddhan IIT Madras, IndiaAnsuman Banerjee Indian Statistical Institute, Kolkata, IndiaGaurab Banerjee Indian Institute of Science, Bangalore, IndiaKunal Banerjee Intel LabsSwapna Banerjee IIT Kharagpur, IndiaLava Bhargava MNIT Jaipur, IndiaBhargab B. Bhattacharya Indian Statistical Institute, Kolkata, IndiaEnakshi Bhattacharya IIT Madras, IndiaTarun Kanti Bhattacharyya IIT Kharagpur, IndiaSantosh Biswas IIT Guwahati, IndiaD. Boolchandani NIT Jaipur, IndiaAnand Bulusu IIT Roorkee, IndiaIndrajit Chakrabarti IIT Kharagpur, IndiaParthasarathi Chakrabarti IIT BHU, IndiaSusanta Chakraborti IIEST, IndiaAmlan Chakraborty University of Calcutta, Kolkata, IndiaRajat Subhra Chakraborty IIT Kharagpur, IndiaAnjan Chakravorty IIT Madras, IndiaRajeevan Chandel NIT Hamirpur, IndiaDavid Chang National Cheng Kung University, TaiwanAbhijit Chatterjee Georgia Tech, USAAmitabh Chatterjee IIT Guwahati, IndiaShouribrata Chatterjee IIT Delhi, IndiaAnupam Chattopadhyay Nanyang Technological University, SingaporeSantanu Chattopadhyay IIT Kharagpur, IndiaYogesh Chauhan IIT Kanpur, IndiaShailesh Chouhan Aalto University, FinlandBijoy Krishna Das IIT Madras, IndiaBishnu Das IIT Roorkee, IndiaDebesh K. Das Jadavpur University Kolkatta, IndiaSayantan Das Verific Design Automation, Kolkata, IndiaAmitava Dasgupta IIT Madras, IndiaSudeb Dasgupta Indian Institute of Technology, Roorkee, IndiaSujay Deb IIIT Delhi, IndiaM. Jamal Deen Academy of Science, Royal Society of CanadaMadhav Desai IIT Bombay, IndiaSoumyajit Dey IIT Kharagpur, IndiaArnab Dutta IIT Roorkee, India

Organization IX

Ramen Dutta Marvell Technology Group, SwitzerlandSiddharth Duttagupta IIT Bombay, IndiaMasahiro Fujita Tokyo UniversityManoj Singh Gaur MNIT Jaipur, IndiaPriyankar Ghosh IBM India Software Labs, IndiaSantosh Ghosh Intel Corporation, USAChandan Giri IIEST Shibpur, IndiaNeeraj Goel IIT Ropar, IndiaPrasanta Kumar Guha IIT Kharagpur, IndiaMridula Gupta Delhi University, IndiaShalabh Gupta IIT Bombay, IndiaAritra Hazra IIT Madras, IndiaTsung-Yi Ho National Tsing Hua University, TaiwanJuinn-Dar Huang National Chiao Tung University, TaiwanSrivatsava Jandhyala IIIT Hyderabad, IndiaRam Rakesh Jangir GJU Hisar, IndiaSatyabrata Jit IIT BHU, IndiaJohn Jose IIT Guwahati, IndiaVeezhinathan Kamakoti IIT Madras, IndiaHemangee Kapoor IIT Guwahati, IndiaSougata Kar NIT Rourkela, IndiaChandan Karfa IIT Guwahati, IndiaAbhijit Karmakar CEERI, IndiaAlika Khare IIT Guwahati, IndiaAbhinav Kranti IIT Indore, IndiaSubir Kumar Sarkar Jadavpur University Kolkatta, IndiaSubrat Kumar Panda Capillary Technologies, Bangalore, IndiaBrajesh Kumar Kaushik IIT Roorkee, IndiaSantanu Kundu LSI India Research and Development Pvt. Ltd., IndiaSubhadip Kundu Synopsys India Pvt. Ltd., Bangalore, IndiaKusum Lata LNMIIT Jaipur, IndiaSushanta Mandal Centurion University, Odisha, IndiaSanjeev Manhas IIT Roorkee, IndiaJimson Mathew IIT Patna, IndiaAnzhela Matrosova Tomsk State University, RussiaBodhisatwa Mazumdar New York University Abu Dhabi, UAEUsha Mehta Nirma University, Ahmedabad, IndiaPrabhat Mishra University of Florida, USADebasis Mitra IIEST Shibpur, IndiaSrobona Mitra Synopsys India Pvt. Ltd., Bangalore, IndiaNihar Mohapatra IIT Gandhinagar, IndiaArijit Mondal IIT Patna, IndiaSamrat Mondal IIT Patna, IndiaShaibal Mukherjee Indian Institute of Technology (IIT) Indore, IndiaSubhankar Mukherjee Cadence Design Systems, Noida, IndiaDebdeep Mukhopadhyay IIT Kharagpur, India

X Organization

Madhu Mutyam IIT Madras, IndiaDeleep R. Nair IIT Madras, IndiaPradeep Nair IIT Bombay, IndiaNagarjuna Nallam IIT Guwahati, IndiaAshutosh Nandi NIT Kurukshetra, IndiaSukumar Nandi IIT Guwahati, IndiaSergei Ostanin Tomsk State University, RussiaRoy Paily IIT Guwahati, IndiaAjit Pal IIT Kharagpur, IndiaBhaskar Pal Synopsys India Pvt. Ltd., Bangalore, IndiaPankaj Pal NIT Uttarakhand, IndiaAjit Panda NIST, IndiaPreeti Ranjan Panda IIT Delhi, IndiaSoumya Pandit IRPE, University of Calcutta, Kolkata, IndiaChetan Parikh IIIT Bangalore, IndiaMahesh Patil IIT Bombay, IndiaSachin Patkar IIT Bombay, IndiaKolin Paul IIT Delhi, IndiaSajal Paul ISM-IIT Dhanbad, IndiaGayadhar Pradhan National Institute of Technology, Patna, IndiaAmit Prakash Singh GGS-IPU, IndiaHafizur Rahaman Indian Institute of Engineering Science and Technology

(IIEST), Shibpur, IndiaBalwinder Raj NIT Jalandhar, IndiaArvind Rajawat MANIT, Bhopal, IndiaAshwani Rana NIT Hamirpur, IndiaSurendra Rathod SPIT, Mumbai, IndiaKarun Rawat IIT Roorkee, IndiaDebdutta Ray IIT Madras, IndiaSubir Roy IIIT Bangalore, IndiaSudip Roy IIT Roorkee, IndiaDebasri Saha University of Calcutta, IndiaMounita Saha Synopsys India Pvt. Ltd., Bangalore, IndiaVineet Sahula MNIT Jaipur, IndiaRaj Sarin NIT Jalandhar, IndiaArnab Sarkar IIT Guwahati, IndiaChandan Kumar Sarkar Jadavpur University, Kolkatta, IndiaKewal Sauja University of Wisconsin Madison, USAManoj Saxena Delhi University, IndiaSaurabh Saxena Indian Institute of Technology Madras, IndiaIndranil Sengupta IIT Kharagpur, IndiaG. K. Sharma IIT Madras, IndiaMaryam Shojaei Baghini IIT Bombay, IndiaAshok Sihag BML Munjal University, IndiaSuraj Sindhia Intel, IndiaAdit Singh Auburn University, USA

Organization XI

Shiv Govind Singh IIT Hydrebad, IndiaVirendra Singh IIT Bombay, IndiaManan Suri Indian Institute of Technology Delhi, IndiaSusmita Sur-Kolay Indian Statistical Institute Kolkata, IndiaGaurav Trivedi IIT Guwahati, IndiaNajeeb-ud-din NIT Srinagar, IndiaRamesh Vaddi Dr. SPM International Institute of Information

Technology, IndiaVinita Vasudevan IIT Madras, IndiaAmit Verma Indian Institute of Technology Kanpur, IndiaSantosh Vishwakarma IIT Indore, IndiaRobert Wille Johannes Kepler University, AustriaShigeru Yamashita Ritsumeikan University, JapanHailong Yao Tsinghua University, ChinaNina Yevtushenko Tomsk Polytechnic University, RussiaRajesh Zele IIT Bombay, India

XII Organization

Sponsors

Ministry of Electronics and Information Technology, Government of IndiaVLSI Society of IndiaCSIR IndiaHPCadenceSpringerIEEE CAS/SSC, Roorkee ChapterIEEE UP SectionTektronixISROREDINGTONEigenFOREVISION

Organization XIII

Contents

Digital Design

Flexible Composite Galois Field GFðð2mÞ2Þ Multiplier Designs . . . . . . . . . . 3M. Mohamed Asan Basiri and Sandeep K. Shukla

Estimating the Maximum Propagation Delay of 4-bit Ripple Carry AdderUsing Reduced Input Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Manan Mewada, Mazad Zaveri, and Anurag Lakhlani

VLSI Implementation of Throughput Efficient Distributed ArithmeticBased LMS Adaptive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Mohd. Tasleem Khan and Shaik Rafi Ahamed

Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder . . . . 36K. Dheepika, K. S. Jevasankari, Vippin Chandhar, and Binsu J. Kailath

Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm . . . . . . . 48Pravin Zode, R. B. Deshmukh, and Abdus Samad

Performance Optimized 64b/66b Line Encoding Technique for High SpeedSERDES Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Jatindeep Singh, Satyajit Mohapatra, and Nihar Ranjan Mohapatra

A New Multi-objective Hardware-Software-Partitioning AlgorithmicApproach for High Speed Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Naman Govil, Rahul Shrestha, and Shubhajit Roy Chowdhury

A Framework for Branch Predictor Selection with Aggregationon Multiple Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Moumita Das, Ansuman Banerjee, and Bhaskar Sardar

FPGA Implementation of a Novel Area Efficient FFT Scheme Using MixedRadix FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Thilagavathy R, Susmitha Settivari, Venkataramani B,and Bhaskar M

Analog/Mixed Signal

Low Voltage, Low Power Transconductor for Low FrequencyGm-C Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Hanumantha Rao G. and Rekha S.

An Improved Highly Efficient Low Input Voltage Charge Pump Circuit . . . . 93Naresh Kumar, Raja Hari Gudlavalleti,and Subash Chandra Bose

A Calibration Technique for Current Steering DACs - Self Calibrationwith Capacitor Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Pallavi Darji and Chetan Parikh

Characterization and Compensation Circuitry for Piezo-Resistive PressureSensor to Accommodate Temperature Induced Variation . . . . . . . . . . . . . . . 115

M. Santosh, Anjli Bansal, Jitendra Mishra, K. C. Behra,and S. C. Bose

FEM Based Device Simulator for High Voltage Devices . . . . . . . . . . . . . . . 127Ashok Ray, Gaurav Kumar, Sushanta Bordoloi,Dheeraj Kumar Sinha, Pratima Agarwal,and Gaurav Trivedi

Synapse Circuits Implementation and Analysis in 180 nm MOSFETand CNFET Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Sushma Srivastava and S. S. Rathod

A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator . . . . . . . . 144Vivek Tyagi, M. S. Hashmi, Ganesh Raj, and Vikas Rana

VLSI Testing

Deterministic Shift Power Reduction in Test Compression . . . . . . . . . . . . . . 155Kanad Basu, Rishi Kumar, Santosh Kulkarni, and Rohit Kapur

Pseudo-BIST: A Novel Technique for SAR-ADC Testing . . . . . . . . . . . . . . 168Yatharth Gupta, Sujay Deb, Vikrant Singh, V. N. Srinivasan,Manish Sharma, and Sabyasachi Das

SFG Based Fault Simulation of Linear Analog Circuits Using FaultClassification and Sensitivity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Rahul Bhattacharya, S. H. M. Ragamai, and Subindu Kumar

A Cost Effective Technique for Diagnosis of Scan Chain Faults . . . . . . . . . . 191Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu,and Ashok Suhag

Multi-mode Toggle Random Access Scan to Minimize TestApplication Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Anshu Goel and Rohini Gulve

XVI Contents

Performance Analysis of Disability Based Fault Tolerance Techniquesfor Permanent Faults in Chip Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . 217

Avishek Choudhury and Biplab K. Sikdar

Devices and Technology – I

Low-Power Sequential Circuit Design Using Work-FunctionEngineered FinFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Ashish Soni, Abhijit Umap, and Nihar R. Mohapatra

Vertical Nanowire FET Based Standard Cell Design Employing Verilog-ACompact Model for Higher Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Satish Maheshwaram, Om Prakash, Mohit Sharma, Anand Bulusu,and Sanjeev Manhas

Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-EffectTransistor as pH Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Ajay Singh, Rakhi Narang, Manoj Saxena, and Mridula Gupta

Exploiting Characteristics of Steep Slope Tunnel Transistors TowardsEnergy Efficient and Reliable Buffer Designs for IoT SoCs . . . . . . . . . . . . . 259

Japa Aditya, Vallabhaneni Harshita, and Ramesh Vaddi

An Efficient VLSI Architecture for PRESENT Block Cipherand Its FPGA Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Jai Gopal Pandey, Tarun Goel, and Abhijit Karmakar

Investigation of TCADs Models for Characterization of Sub 16 nmIn0:53Ga0:47As FinFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

J. Pathak and A. Darji

Hausdorff Distance Driven L-Shape Matching Based LayoutDecomposition for E-Beam Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Arindam Sinharay, Pranab Roy, and Hafizur Rahaman

VLSI Architectures

Energy-Efficient VLSI Architecture & Implementation of Bi-modalMulti-banked Register-File Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Sumanth Gudaparthi and Rahul Shrestha

Performance-Enhanced d2-LBDR for 2D Mesh Network-on-Chip . . . . . . . . . 313Anugrah Jain, Vijay Laxmi, Meenakshi Tripathi,Manoj Singh Gaur, and Rimpy Bishnoi

Contents XVII

ACAM: Application Aware Adaptive Cache Management for Shared LLC. . . 324Sujit Kr Mahto and Newton

Adaptive Packet Throttling Technique for Congestion Managementin Mesh NoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

N. S. Aswathy, R. S. Reshma Raj, Abhijit Das, John Jose,and V. R. Josna

Defeating HaTCh: Building Malicious IP Cores . . . . . . . . . . . . . . . . . . . . . 345Anshu Bhardwaj and Subir Kumar Roy

Low Cost Circuit Level Implementation of PRESENT-80 S-BOX . . . . . . . . . 354S. Shanthi Rekha and P. Saravanan

Emerging Technologies and Memory

Modeling and Analysis of Transient Heat for 3D IC . . . . . . . . . . . . . . . . . . 365Subhajit Chatterjee, Surajit Kr. Roy, Chandan Giri,and Hafizur Rahaman

Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder . . . . . . . . . . 376Mamata Panigrahy, Nirmal Chandra Behera, B. Vandana,Indrajit Chakrabarti, and Anindya Sundar Dhar

Metal-Oxide Nanostructures Designed by Glancing Angle DepositionTechnique and Its Applications on Sensors and Optoelectronic Devices:A Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Divya Singh

Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETsExploiting the Steep Slope and Ambipolar Characteristics . . . . . . . . . . . . . . 398

Y. Sudha Vani, N. Usha Rani, and Ramesh Vaddi

Enhancing Retention Voltage for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 406Ankit Rehani, Sujay Deb, and Suprateek Shukla

Comparison of SRAM Cell Layout Topologies to Estimate Improvementin SER Robustness in 28FDSOI and 40 nm Technologies . . . . . . . . . . . . . . 414

Anand Ilakal and Anuj Grover

Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space. . . 421Neha Chaudhuri, Chandan Bandyopadhyay, and Hafizur Rahaman

Devices and Technology – II

Delay and Frequency Investigations in Coupled MLGNR Interconnects . . . . . 429Manish Joshi, Koduri Teja, Ashish Singh, and Rohit Dhiman

XVIII Contents

LISOCHIN: An NBTI Degradation Monitoring Sensor for ReliableCMOS Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

Ambika Prasad Shah, Nandakishor Yadav,and Santosh Kumar Vishvakarma

Performance Analysis of OLED with Hole Block Layer and Impactof Multiple Hole Block Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Shubham Negi, Poornima Mittal, and Brijesh Kumar

Improved Gate Modulation in Tunnel Field Effect Transistorswith Non-rectangular Tapered Y-Gate Geometry . . . . . . . . . . . . . . . . . . . . . 463

Rakhi Narang, Mridula Gupta, and Manoj Saxena

A 36 nW Power Management Unit for Solar Energy HarvestersUsing 0.18 lm CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Purvi Patel, Biswajit Mishra, and Dipankar Nagchoudhuri

A 10T Subthreshold SRAM Cell with Minimal Bitline Switchingfor Ultra-Low Power Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

Swaati and Bishnu Prasad Das

Variability Investigation of Double Gate JunctionLess (DG-JL) Transistorfor Circuit Design Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

Vandana Kumari, Manoj Saxena, and Mridula Gupta

System Design

A High Speed KECCAK Coprocessor for Partitioned NSP Architectureon FPGA Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Rourab Paul and Sandeep Kumar Shukla

New Energy Efficient Reconfigurable FIR Filter Architectureand Its VLSI Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

Naushad Ali and Bharat Garg

FPGA-Based Smart Camera System for Real-Time AutomatedVideo Surveillance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

Sanjay Singh, Sumeet Saurav, Ravi Saini, Atanendu S. Mandal,and Santanu Chaudhury

Effectiveness of High Permittivity Spacer for Underlap Regionsof Wavy-Junctionless FinFET at 22 nm Node and Scaling ShortChannel Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

B. Vandana, J. K. Das, S. K. Mohapatra, and B. K. Kaushik

Contents XIX

Design and Implementation of Ternary Content Addressable Memory(TCAM) Based Hierarchical Motion Estimation for Video Processing . . . . . . 557

Puja Ghosh and P. Rangababu

A Custom Designed RISC-V ISA Compatible Processor for SoC . . . . . . . . . 570Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese,and Amrutur Bharadwaj

Low Power Design and Test

An Efficient Timing and Clock Tree Aware Placement Flowwith Multibit Flip-Flops for Power Reduction. . . . . . . . . . . . . . . . . . . . . . . 581

Jasmine Kaur Gulati, Bhanu Prakash, and Sumit Darak

Primitive Instantiation Based Fault Localization Circuitryfor High Performance FPGA Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Ayan Palchaudhuri and Anindya Sundar Dhar

On Generation of Delay Test with Capture Power Safety . . . . . . . . . . . . . . . 607Rohini Gulve and Nihar Hage

A Configurable and Area Efficient Technique for ImplementingIsolation Cells in Low Power SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

Prokash Ghosh and Jyotirmoy Ghosh

RF Circuits

A 10 MHz, 42 ppm/�C, 69 lW PVT Compensated Latch Based Oscillatorin BCD9S Technology for PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

Vivek Tyagi, M. S. Hashmi, Ganesh Raj, and Vikas Rana

A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled CascodeOTA with 100 dB Gain 200 MHz UGB in CMOS . . . . . . . . . . . . . . . . . . . 646

Antaryami Panigrahi and Abhipsa Parhi

A Low Power, Frequency-to-Digital Converter CMOS Based TemperatureSensor in 65 nm Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Mudasir Bashir, Sreehari Rao Patri, and K. S. R. Krishna Prasad

Design & Development of High Speed LVDS Receiver with Cold-SpareFeature in SCL’s 0.18 µm CMOS Process . . . . . . . . . . . . . . . . . . . . . . . . . 667

Munish Malik, Ajay Kumar, and H. S. Jatana

Architecture and CAD

Fast FPGA Placement Using Analytical Optimization . . . . . . . . . . . . . . . . . 681Sameer Pawanekar and Gaurav Trivedi

XX Contents

A Dependability Preserving Fluid-Level Synthesis for ReconfigurableDroplet-Based Microfluidic Biochips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

Arpan Chakraborty, Piyali Datta, Debasis Dhal,and Rajat Kumar Pal

Splitting and Transport of a Droplet with No External Actuation Forcefor Lab on Chip Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

T. Pravinraj and Rajendra Patrikar

Analytical Partitioning: Improvement over FM . . . . . . . . . . . . . . . . . . . . . . 718Sameer Pawanekar and Gaurav Trivedi

A Lifting Instruction for Performing DWT in LEON3 ProcessorBased System-on-Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

Rajul Bansal, Mahendra Kumar Jatav, and Abhijit Karmakar

Droplet Position Estimator for Open EWOD System Using Open SourceComputer Vision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

Vandana Jain, Vasavi Devarasetty, and Rajendra Patrikar

Design and Implementation of Mixed Parallel and Dataflow Architecturefor Intra-prediction Hardware in HEVC Decoder. . . . . . . . . . . . . . . . . . . . . 742

Rituparna Choudhury and P. Rangababu

Design Verification

A Formal Perspective on Effective Post-silicon Debug and TraceSignal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey,and Masahiro Fujita

Translation Validation of Loop Invariant Code Optimizations InvolvingFalse Computations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri

A Framework for Automated Feature Based Mixed-SignalEquivalence Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

Antara Ain, Sayandeep Sanyal, and Pallab Dasgupta

xMAS Based Accurate Modeling and Progress Verification of NoCs. . . . . . . 792Surajit Das, Chandan Karfa, and Santosh Biswas

Faulty TSVs Identification in 3D IC Using Pre-bond Testing . . . . . . . . . . . . 805Dilip Kumar Maity, Surajit Kumar Roy, and Chandan Giri

Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

Contents XXI