coen 3137 - experiment no. 7 - synchronous binary counters

8/12/2019 COEN 3137 - Experiment No. 7 - Synchronous Binary Counters

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COEN 3137Advanced Logic Circuits Design

EXPERIMENT NO.

7SYNCHRONOUS BINARY COUNTERS

Group #N (your g roup number)(list all team members and affix signatures)

Team Members Signature

Republic of the Philippines

POLYTECHNIC UNIVERSITY OF THE PHILIPPINES

COLLEGE OF ENGINEERING

COMPUTER ENGINEERING DEPARTMENT


2/19

LAB 7 : Synchronous Binary Counters

Duration: 3 Hours

OBJECTIVES:a. ) To construct a sequential circuit using 74LS76 ICs.b. ) To verify the state table of the experimental circuit.c.) To demonstrate the behavior of the circuit.d.) To design and implement a sequential circuit 74LS76 ICs.e.) To verify the state diagram to ensure that the circuit will work in accordancewith the design problem.

BASIC INFORMATION:A synchronous sequential circuit employ signals that affect the memoryelements only at a discrete instants of time. This is achieved by using pulses oflimited duration throughout the system so that one pulse amplitude representslogic 1 and another pulse amplitude represents logic 0.

Practical logic systems use fixed amplitudes such as voltage levels for thebinary signals. Synchronization is achieved by a timing device called a master-clock generator, which generates a periodic train of clock pulses. The clockpulses are distributed throughout the system in such a way that memoryelements are affected only with the arrival of the synchronization pulse.

DESIGNING SEQUENTIAL CIRCUITS.We can construct the sequential circuits by following this step-by-stepprocedure.

a. From the given information about the circuit, obtain state diagram and circuitexcitation table.

b. Determine the number flip-flops needed and assign a letter symbol to each.

c. Choose the type FF to be used.

d. Using the K-map, derive the circuit output functions and the flip-flop inputfunctions.

e. Draw the logic diagram.


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MATERIALS REQUIRED :3 LED 1 Breadboard1 Power supply 1 Cutter plier

1 Long nose plier 1 Wire Stripper3 150 2 74LS76 IC1 74LS14 1 NO switch4 10K

PROCEDURES:Mod 4 Binary Up/Down Counter:

Design a circuit to build a Mod 4, two bit binary up/down counter.The counter cycles from 012301... when X=0

or: 321032... when X=1This circuit can be represented by the State Transition Diagram in

fig.1 below.

The STATES (binary number) arerepresented using 2 flip-flops; eachflip-flop represents 1 binary digit. Theflip-flops can remember what hashappened in the past, or what valuehas been stored in them.

There will be one external input, Xwhich controls the direction of thecount: UP for X=0, and DOWN for X=1.The state of the flip-flopsrepresenting the 2-bit binary number(the count) will be the only circuit

output.

We could design this circuit using JK, D or T flip-flops, but in this example welluse D flip-flops. When we are finished the circuit will look something like thisincomplete circuit:

Construct the State Transition Diagramfor Counter Circuit


4/19

lights

I. XDB QB

Clc

QB

DA QA

Clc

QA

clock

Our task is to design the circuit, such that the flip flop inputs willproduce the currentNext Stateoutputs. The design procedure wewill follow for this problem will be:

Design Procedure:1. Obtain the State Table from the problem statement of from the

State Transition Diagram.2. Derive the flip-flop input equations from the next state conditions

in the state table.3. Use K-maps to simplify the flip-flop input equations.

4. Draw the logic diagram with flip-flops and combinational gates asspecified by the flip-flop input equations.

We will illustrate the solution using both D flip flops and JK flip flops. Startingwith D flip flop solution.


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Present Input Next State Flip FlopInputsQA QB X QA+ QB+ DA DB

Derive the next-state equation using the K-mapping method:

QAQB

X 0 0 0 1 1 1 1 0

0

1

DA=

QAQB

X 0 0 0 1 1 1 1 00

1

DB=


6/19

Draw the logic diagram for this counter circuit:

lights

II. XDB QB

Clc

QB

DA QA

Clc

QA

clock

Complete the solution using JK flip flops is shown on the followingpage.

PresentStateInput Next State Flip Flop Inputs

QA QB X QA+ QB+ J A KA JB KB0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1


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JK FLIP FLOP #1 corresponds to most significant bit of the 2 bitbinary number, while flip flop #2 represents the least significant bit.

Deriving the next-state equations using K-mapping:

JK FLIP FLOP 1

QAQB

QCX0 0 0 1 1 1 1 0

QAQB

QCX0 0 0 1 1 1 1 0

0 0 0 0

0 1 0 1

1 1 1 11 0 1 0

JA= K

A=

JK FLIP FLOP 2

QAQBQCX

0 0 0 1 1 1 1 0 QAQBQCX0 0 0 1 1 1 1 0

0 0 0 0

0 1 0 1

1 1 1 1

1 0 1 0

JB= K

B=


8/19

Draw the logic diagram for circuit implementation:

Problem #2: Design a circuit that cycle through the numbers:13452134....

Your counter for the sequence of numbers should advance up ordown based on a control variable input. When control variable C=1,advance forward, while a control input of C=0 should cause abackward move in the sequence. Assume the sequence wrapsaround at both ends. For example, if you have selected sequence13452 and the counter started up at 1, with control input at one(C=1), seven clock pulses should cause the following transitions:

13452134....


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1.Draw the State Transition Diagram:

2.Fill in the State Table below, for your sequence, using thecompleted JK excitation values in the small table below.


10/19

For now leave the rows associated with the unused numbersempty for now. Later after we fill in the K-maps we will come

back and explore what happens if the circuit ever gets into one ofthese states.Present State input Next State Flip Flop InputsQA QB QC E QA+ QB+ QC+ JA KA JB KB JC KC #0 0 0 0

00 0 0 1

0 1 0

10 0 1 1

0 1 0 0

20 1 0 1

0 1 1 0

30 1 1 1

1 0 0 0

41 0 0 1

1 0 1 0

51 0 1 1

1 1 0 0

61 1 0 1

1 1 1 0

71 1 1 1


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JK FLIP FLOP 1

QAQB

QCE 0 0 0 1 1 1 1 0

QAQB

QCE 0 0 0 1 1 1 1 00 0 0 0

0 1 0 1

1 1 1 1

1 0 1 0

JA= K

A=

JK FLIP FLOP 2

QAQB

QCE0 0 0 1 1 1 1 0

QAQB

QCE0 0 0 1 1 1 1 0

0 0 0 0

0 1 0 1

1 1 1 1

1 0 1 0

JB= KB =

JK FLIP FLOP 3

QAQB

QCE0 0 0 1 1 1 1 0

QAQB

QCE0 0 0 1 1 1 1 0

0 0 0 0

0 1 0 1

1 1 1 1

1 0 1 0

JC= KC=


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Circuit DiagramControl Input

E________________________________________________________

JA QA

__

JB QB

__

JC QC

__


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74LS76A

1 2 3 4 5 6 7 8

910111213141516

FIGURE 6. Dual JK Flip-Flop with Set and C lear

K

CP

J

QSD

CDQ

16

1

4 14

15

2

3

K

CP

J

QSD

CDQ

12

6

9 10

11

7

8

VCC

=PIN 5GND=PIN 13

LOGIC SYMBOLPIN CONFIGURATION

330

K

CP

J

QSD

CD

Q

16

1

4

14

15

2

3

VCC

K

CP

J

QSD

CD

Q

12

6

9

10

11

7

8

VCC

330

330

P O

T

10K

5Vs

RA

7

6

2 1

5

3

84

555IC

RB

C

VCC

5V

OUT

0.0110uF

++

10K

100K

Figure 6-1 Synchronous Sequential Circuit


14/19

DATA and RESULTSPART 1. Synchronous Sequential Circuit Analysis.

Control Input Equations

0

0

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

P

stateIn FF Inputs

N

stateO

P

state

Next state

= 0 = 1OUT

=0 =1

TRUTH TABLE

TRANSITION TABLE

STATE DIAGRAM


15/19

PART II. Synchronous Sequential Circuit Design.

0

0

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

Presentstate FF Inputs

FF Excitation Table

STATE DIAGRAM Nextstate

0

1

00 01 11 10

0

1

00 01 11 10

0

1

00 01 11 10

0

1

00 01 11 10

0

1

00 01 11 10

0

1

00 01 11 10


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Design Circuit.


17/19

QUESTIONS :a.) Does the actual output of Figure 6-1 agree with theoritical value?

Explain the reason of discrepancy, if any.

_________________________________________________________________

_________________________________________________________________

b.) Does the actual output of your design circuit agree with theoriticalvalue? Explain the reason of discrepancy, if any.

_________________________________________________________________

_________________________________________________________________

c.) In the circuit of Figure 6-2, the inputs A, B, and C are all initiallyLOW. Output Y is suppose to go HIGH only when A, B, and C go toHIGH in a certain sequence.Determine the sequence that will make Y go HIGH.Explain why the START pulse is needed.

_________________________________________________________________

_________________________________________________________________

_________________________________________________________________

_________________________________________________________________

_________________________________________________________________

A Y

J

Q

Q

K

SET

CLR

XJ

Q

Q

K

SET

CLR

Figure 6-2.

B

C

Start


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d.) Refer to the circuit in Figure 6-3. Assume that all asynchronous

inputs are connected to VCC. When tested, the circuit waveformsappear as shown in Figure 6-3. Consider the following list ofpossible faults. For each one indicate "YES" or "NO" as to whether

it could cause the observed results. Explain each response.

a.) CLR input Y2is open.

______________________________________________________________________________________________________________________________________________________

b.) Y1output's transition times are too long, possibly due toloading.

____________________________________________________________________________________________________________________________________________________

c. Y2output shorted to ground.____________________________________________________________________________________________________________________________________________________________

d. Y2's hold-time requirement is not being met.____________________________________________________________________________________________________________________________________________________________


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CONCLUSION:____________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

Clock

Y2

Y1

Y0

Y2

J

Q

Q

K

SET

CLR

Y1

J

Q

Q

K

SET

CLR

Y0

J

Q

Q

K

SET

CLR

Input Clock Pulses

Figure 6-3. JK FF wired as a 3-bit counter

1

1

1

1

1

1

Figure 6-4. Waveforms of the circuit in Figure 6-3.

coen 3137 - experiment no. 7 - synchronous binary counters

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