cobalt/onyx online catalog - dynamic c4 · models 71620 & 71720: transceiver with three a/ds,...

2

Contents

Xilinx FPGA Performance ............................................................................................................................................. 3The Cobalt/Onyx Architecture ....................................................................................................................................... 4Cobalt/Onyx Formats & Interfaces ................................................................................................................................. 9Support Software ........................................................................................................................................................ 13Models 71620 & 71720: Transceiver with Three A/Ds, DUC, Two D/As - XMC .............................................................. 14Model 71621: Transceiver with Three A/Ds, DDCs, DUC, Two D/As - XMC .................................................................. 17Model 71630: 1 GHz A/D, 1 GHz D/A - XMC ............................................................................................................. 19Model 71640: 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit A/D - XMC ............................................................... 22Model 71650: Transceiver with Two A/Ds, DUC, Two D/As - XMC................................................................................ 25Model 71651: Transceiver with Two A/Ds, DDC, DUC, Two D/As ................................................................................ 28Models 71660 & 71760: 4-Channel 200 MHz A/D - XMC ........................................................................................... 30Model 71661: 4-Channel 200 MHz A/D with DDCs and Beamformer -XMC ................................................................ 33Model 71662: 4-Channel 200 MHz A/D with 32-Channel DDC - XMC ........................................................................ 35Model 71670: 4-Channel 1.25 GHz D/A with DUC - XMC .......................................................................................... 37Model 71671: 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation - XMC ...................................................... 40Model 71690: L-Band RF Tuner with 2-Channel 200 MHz A/D - XMC .......................................................................... 42Performance Graphs................................................................................................................................................... 45Model 71611: Quad Serial FPDP Interface .................................................................................................................. 46Model 7192: High-Speed Synchronizer and Distribution Board - PMC/XMC ................................................................. 48Model 9192: Rack-mount High-Speed System Synchronizer Unit ................................................................................. 50Model 7893: System Synchronizer and Distribution Board - PCIe ................................................................................. 52Coming Soon! ............................................................................................................................................................ 54Customer Information................................................................................................................................................. 55

A/D Converters D/A Converters Other

Qty Rate Bits Qty Rate Bits Features

71620 71720 3 200 MHz 16 2 800 MHz 16

71621 71721 3 200 MHz 16 2 800 MHz 16 3 DDCs, Sum, Int

71660 71760 4 200 MHz 16

71661 71761 4 200 MHz 16 4 DDCs, Sum

71662 71762 4 200 MHz 16 32 DDCs, Sum

71690 71790 2 200 MHz 16 L-Band Tuner

71650 71750 2 400 MHz 14 2 800 MHz 16

71651 71751 2 400 MHz 14 2 800 MHz 16 2 DDCs, Int

71650 71750 2 500 MHz 12 2 800 MHz 16

71651 71751 2 500 MHz 12 2 800 MHz 16 2 DDCs, Int

Extended Int

71630 71730 1 1 GHz 12 1 1 GHz 12

71640 71740 2 1.8 GHz 12

71640 71740 1 3.6 GHz 12

71670

71671

71770

71771

4

4

1.25 GHz

1.25 GHz

16

16

71611 Quad sFPDP

DDC = Digital DownconverterRate = Maximum Sampling Frequency

Int = Interpolation Filter

Sum = Beamforming Summation Block & Aurora Chaining Interface

–sFPDP = Serial FPDP VITA 17.1

Cobalt/Onyx Selection Chart

http://pentek.com/products/Detail.cfm?Model=71721













3

Xilinx FPGA Performance

0

100

200

300

400

500

600

700

Logic Cells

In Thousands

Smaller DevicesLarger Devices

330T

550T585T

415T

485T

690T

LX130TLX195T

LX240T

SX315TLX356T

SX475T

LX160

LX/SX50T FX70T LX85T SX95T LX/FX110T LX155T

LX40 SX55LX/FX60 LX80 LXFX100

LX160

Virtex-4

Virtex-5

Virtex-6

Virtex-7

he atest Gen r ions of te FP AThe Latest Generations of Virtex FPGAs e e r ons f e Ahe at st G n i o t FPThe Latest Generations of Virtex FPGAs

Logic Cell Density Comparison, Virtex-4, Virtex-5, Virtex-6, and Virtex-7 FPGAs Used in Pentek Products

With each new generation of FPGAdevices, Xilinx continues to push theperformance envelope to match theever increasing requirements of targetapplications.

The announcement of the Virtex-6and Virtex-7 were no exception.More processing power, lower powerconsumption, and updated interfacefeatures to match the latest technologyI/O requirements, are all part of thesenew devices.

While it might be easy to assumethat faster, bigger, more powerful isbetter, it’s important to understand howthe latest FPGA innovations actuallydeliver this higher performance tobest match the device to the specificrequirements of the application.

One of the standard metrics forFPGAs is the number of logic cells.This figure shows the steady improve-ment in the last four generations of

Xilinx FPGAs starting with the Virtex-4and continuing to the Virtex-7. Thegraph displays the number of logiccells contained in a range of differentdensity devices offered in a 35 mm x35 mm BGA (Ball-Grid Array) package.This clearly shows the dramatic increasein resource density, bounded by theconstraints of the size and power dissi-pation capacity of a given package.

Since Virtex-4 CLBs (Configurable LogicBlocks) comprise eight logic cells, whileVirtex-5 and Virtex-6 CLBs comprise 12,the increase in logic cells betweenVirtex-4 and Virtex-5 actually translatesto a decrease in CLBs because eachCLB in the Virtex-5 requires more logiccells. While the Virtex-5 CLBs are morepowerful than their Virtex-4 counter-parts, there are still fewer of them touse. What is also clear from this graphis that the Virtex-6 represents a signifi-

cant increase in density from theVirtex-5 family.

The Virtex-7 offers the highestperformance thus far with twice theperformance and twice the resourcesof the Virtex-6.

The Virtex-7 devices feature low-power 28 nm process technology toimplement up to 3.1 Tbits/sec of I/Oand up to 2 million logic cells. Theyprovide up to 6.7 TMACs of DSPresources, especially important forsoftware radio applications. Because ofnew process technologies and otherpower management schemes, theyconsume half the power of Virtex-6 fora given function.

This combination of lower powerand higher performance for each of thekey resources benefits software radio,opens up new product markets, andextends the capabilities of existingapplications.

4

The Cobalt & Onyx Architecture

atur s n I me tioFeatures and Implementationur I m ioat n e tFeatures and Implementationb l n x h ra F t rCobalt & Onyx Architectural Features x a F rb n h r tCobalt & Onyx Architectural Features■ Cobalt®: Xilinx Virtex-6 FPGA■ OnyxTM: Xilinx Virtex-7 FPGA■ Configurable memory resources—

depending on model■ On-board clocking and synchro-

nization■ Modular I/O design to support a

wide range of signal types

r d rdMain BoardMain BoardThe main board serves as the foundationof all Cobalt and Onyx products. It housesthe FPGA, FLASH memory, XMCinterfaces, user programmable FPGAinterfaces and hosts the memory andI/O modules.

ob lCobaltob lCobalt & & & & On P o n tuOnyx Performance Featuresn n tO P o uOnyx Performance Features■ A/D sampling rates from 10 MHz

to 3 GHz■ D/A sampling rates up to 1.25 GHz■ Powerful linked-list DMA engines■ PCI Express as the primary control

and data transfer interface■ Secondary serial gigabit interface■ All models available in XMC,

PCI Express, OpenVPX andCompactPCI formats

■ Available in commercial and inseveral ruggedization levels up toand including conduction cooling

I o leI/O ModuleI o e lI/O ModuleThe I/O module is a separate printed-circuit board that caries all of theanalog interface circuitry providingexcellent isolation from noise. Typicalfront panel signals include analog inand out, clocking, sync, and triggering.

M r Memor y R e urcy ResourcesThese two smaller boards are usedfor the memory resources allowingfor customization of two types ofmemory—depending on model.

Fle bl h e ureFlexible Architecturel h e reFle b uFlexible ArchitectureThe modularity of this assembly offersan unprecedented degree of flexibilityfor creating Cobalt or Onyx moduleswith completely different features byjust incorporating different I/O modules.

As shown in the diagram, the frontpanel allows for a maximum of six

SSMC signal connectors. The externalclocking, trigger and synchronizationconnector is a front-panel multipin flatcable connector and is the same on allmodels, except those designed to oper-ate at frequencies higher than 1.0 GHz.

5

D/A Clock/Sync Bus

VCXO

A/D

RF In

RFXFORMR

RF In

RFXFORMR

COBALT: VIRTEX-6 FPGA

LX130T, LX240T, LX365T, SX315T or SX475T

ONYX: VIRTEX-7 FPGA

VX330T, VX485T or V 690T

TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

A/D

Sample Clk /Reference Clk In

A/D Clock/Sync BusD/A

RFXFORMR

RF Out

RFXFORMR

16

CONFIGFLASH64 MB

RFXFORMR

RF Out

RFXFORMR

D/A

DIGITALUPCONVERTER

40 Cobalt48 Onyx

4X

GTX

4X8X

GTX LVDSGTX

Option-104FPGAGPIO

Option-105SerialI/O

8X

P14PMC

P16XMC

P15XMC

PCIe

TIMING BUSGENERATOR

Clock / Sync /Gate / PPS

GTX

P15XMC

CONFIGFLASH1 GB

ONYXOnly

COBALTOnly

PCIe

FPGAConfigBus

GATEXPRESS PCIeCONFIGURATION

MANAGER

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

Cobalt Memory Configurations

Onyx Memory Configuration

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB


ompone s C cuitComponents and Circuitrm one C u to p s c iComponents and Circuitryyyy

X i e i il x- o V 7 Xilinx Virtex-6 or Virtex-7 FPGAThe Cobalt Virtex-6 FPGA can bepopulated with a variety of differentFPGAs to match the specific require-ments of the processing task. SupportedFPGAs include: LX130T, LX240T,LX365T, SX315T, or SX475T.

Likewise, the Onyx Virtex-7 FPGAcan be populated with a variety ofFPGAs to match the specific require-ments of the processing task. SupportedFPGAs include: VX330T, VX485T, orVX690T.

The SXT parts feature up to 2016DSP48E slices, while the VX690Tfeatures 3600 DSP48E1 slices. Thesedevices are ideal for modulation/demodulation, encoding/decoding,encryption/decryption, and channel-ization of the signals between trans-mission and reception.

e oMemor s u e oy ResourcesCobalt: Up to four independent memorybanks can be configured with all QDRII+SRAM, DDR3 SDRAM, or as combina-tion of two banks of each memory type.

Each QDRII+ SRAM bank can beup to 8 MB deep and is an integral partof the board’s DMA capabilities, provid-ing FIFO memory space for creatingDMA packets. For applications requiringdeep memory resources, DDR3 SDRAMbanks can each be up to 512 MB deep.

o lt r I o ulCobalt or Onyx I/O Modulelt I o lo r uCobalt or Onyx I/O ModuleShown here is a typical Cobalt or OnyxI/O module. The input analog ports aretransformer-coupled to two high-speedA/D converters. The digital outputs aredelivered into the Virtex-6 or Virtex-7FPGA for signal processing, data captureor for routing to other module resources.

Besides the two A/Ds, the typicalmodule could include one DUC(Digital Upconverter), and two D/Aswhich are transformer-coupled to theoutput analog ports.

In addition to the input and outputports, the module includes a multiportconnector for clocking and synchroni-zation. All connectors are on the frontpanel.

H m rFLASH MemoryyCobalt: The 16-bit wide 64 MB FLASHprovides non-volatile memory for factoryboot code, self-test, and user parametersOnyx: The 16-bit wide 1024 MB FLASHprovides non-volatile memory for factoryboot code, self-test, user parameters,and FPGA images for dynamicallyreconfiguring the FPGA.

Onyx: Four independent DDR3 SDRAMmemory banks are available. Each bankis 1 GB deep and is an integral part ofthe board’s DMA capabilities, provid-ing FIFO memory space for creatingDMA packets. Built-in memory functionsinclude an A/D data transient capturemode and D/A waveform playback mode.

In addition to the factory-installedfunctions, custom user-installed IPwithin the FPGA can take advantage ofthe memories for many other purposes.

More on next page ➤

6


D/A Clock/Sync Bus

VCXO

A/D

RF In

RFXFORMR

RF In

RFXFORMR



ONYX: VIRTEX-7 FPGA


TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

A/D



RFXFORMR

RF Out

RFXFORMR

16

CONFIGFLASH64 MB

RFXFORMR

RF Out

RFXFORMR

D/A

DIGITALUPCONVERTER

40 Cobalt48 Onyx

4X

GTX

4X8X

GTX LVDSGTX

Option-104FPGAGPIO

Option-105SerialI/O

8X

P14PMC

P16XMC

P15XMC

PCIe

TIMING BUSGENERATOR


GTX

P15XMC

CONFIGFLASH1 GB

ONYXOnly

COBALTOnly

PCIe

FPGAConfigBus


MANAGER

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB



16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

Components and CircuitrComponents and CircuitrComponents and CircuitrComponents and CircuitrComponents and Circuitryyyyy

Clocking and Synchronization Clocking and Synchronization Clocking and Synchronization Clocking and Synchronization Clocking and SynchronizationThe internal timing buses provide eithera single clock or two different clockrates to the A/D and D/A signal paths.

The timing bus includes a clock,sync and a gate or trigger signal. Anon-board clock generator receives anexternal sample clock which can beused directly for either the A/D or D/Asections or can be divided by a built-inclock synthesizer circuit to providedifferent A/D and D/A clocks.

In an alternate mode, the sampleclock can be sourced from an onboard

Board InterfacesBoard InterfacesBoard InterfacesBoard InterfacesBoard InterfacesThe FPGA is also used to implementthe primary board interfaces. The basicXMC module shown here is also avail-able in different formats, such as PCIExpress, OpenVPX, and CompactPCI.

More information about formats andinterfaces starts on page 9.

Available only in the Onyx series, theGateXpressTM is a sophisticated FPGAPCIe configuration manager for loadingand reloading the FPGA. At powerup,GateXpress presents a PCIe target forthe host computer to discover, effectivelygiving the FPGA time to load from FLASH.This is especially important for largerFPGAs where the loading times canexceed the PCIe discovery window.

The board’s configuration FLASHcan hold up to four FPGA images fordynamically reconfiguring the FPGA.

programmable VCXO (Voltage-Con-trolled Crystal Oscillator). In this mode,the synthesizer locks the VCXO to anexternal system reference, typically10 MHz.

A front panel 26-pin LVPECL Clock/Sync connector allows multiple boardsto be synchronized. In the slave mode,it accepts LVPECL inputs that drive theclock, sync and gate signals. In the mastermode, the LVPECL bus can drive thetiming signals for synchronizing multipleboards.

7


a ress f G i a oGateXpress for FPGA Configurationess f G ia r a oGateXpress for FPGA ConfigurationThe Onyx architecture includes GateXpress,a sophisticated FPGA-PCIe configurationmanager for loading and reloading theFPGA. At power up, GateXpress imme-diately presents a PCIe target for thehost computer to discover, effectivelygiving the FPGA time to load fromFLASH.

This is especially important for largerFPGAs where the loading times canexceed the PCIe discovery window,typically 100 msec on most PCs.

The board’s configuration FLASHcan hold four FPGA images. Images canbe factory-installed IP or custom IPcreated by the user, and programmedinto the FLASH via JTAG using XilinxiMPACT or through the board’s PCIe

interface. At power up the user canchoose which image will load based ona hardware switch setting.

Once booted, GateXpress allowsthe user three options for dynamicallyreconfiguring the FPGA with a new IPimage. The first is the option to load analternate image from FLASH throughsoftware control. The user selects thedesired image and issues a reloadcommand.

The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. Thisis important in security situations wherethere can be no latent user image leftin nonvolatile memory when power isremoved. In applications where the

FPGA IP may need to change manytimes during the course of a mission,images can be stored on the host com-puter and loaded through PCIe as needed.

The third option, typically used duringdevelopment, allows the user to directlyload the FPGA through JTAG using XilinxiMPACT.

In all three FPGA loading scenarios,GateXpress handles the hardware nego-tiation simplifying and streamlining theloading task. In addition, GateXpresspreserves the PCIe configuration spaceallowing dynamic FPGA reconfigurationwithout needing to reset the hostcomputer to rediscover the board.After the reload, the host simply contin-ues to see the board with the expecteddevice ID.

D/A Clock/Sync Bus

VCXO

A/D

RF In

RFXFORMR

RF In

RFXFORMR

ONYX: VIRTEX-7 FPGA


TTL Gate / Trig

TTL Sync / PPS

Sample C k

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

A/D



RFXFORMR

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

D/A

DIGITALUPCONVERTER

40 Cobalt48 Onyx

4X

GTX

4X8X

GTX LVDS

Option-104FPGAGPIO

Option-105SerialI/O

P14PMC

P16XMC

TIMING BUSGENERATOR


GTX

P15XMC

CONFIGFLASH1 GB

ONYXOnly

PCIe

FPGAConfigBus


MANAGER

32 32 32 32

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

8


All of the board’s data and control pathsare accessible by the FPGA, enablingfactory-installed functions including datamultiplexing, channel selection, datapacking, gating, triggering, and memorycontrol. The Cobalt & Onyx Architectureorganizes the FPGA as a container fordata processing applications whereeach function exists as an intellectualproperty (IP) module.

Each member of the Cobalt/Onyxfamily is delivered with factory-installed

applications ideally matched to theboard’s analog interfaces. Dependingon model, the factory-installed functionsmay include A/D acquisition and D/Awaveform playback IP modules. IP mod-ules for either DDR3 or QDRII+ (Cobaltonly) memories, a controller for alldata clocking and synchronization func-tions, a test signal generator, and aPCIe interface complete the factory-installed functions and enable theboard to operate as a complete turn-

key solution without the need to developany FPGA IP.

For applications that require special-ized functions, users can install customIP for data processing. Pentek GateFlow®

FPGA Design Kits (described later inthis catalog) include all of the factoryinstalled modules as documentedsource code. Developers can integratetheir IP with the Pentek factory-installedfunctions or use the GateFlow to com-pletely replace the Pentek IP with theirs.

q n o uleA/D Acquisition IP Modules q o le n uA/D Acquisition IP ModulesThis typical Cobalt/Onyx moduleincludes two A/D Acquisition IPmodules for easy capture and datamoving. Each IP module can receivedata from either of the two A/Ds, atest signal generator or from the D/AWaveform Playback IP Module inloopback mode. Each IP modulehas an associated memory bank forbuffering data in FIFO mode or forstoring data in transient capture mode.All memory banks are supportedwith DMA engines for moving A/Ddata through the PCIe interface.

These powerful linked-list DMAengines are capable of a uniqueAcquisition Gate Driven mode. Inthis mode, the length of a transferperformed by a link definition neednot be known prior to data acquisition;rather, it is governed by the length ofthe acquisition gate. This is extremelyuseful in applications where an exter-nal gate drives acquisition and theexact length of that gate is not knownor is likely to vary.

For each transfer, the DMA enginecan automatically construct metadatapackets containing A/D channel ID, asample-accurate time stamp, and datalength information. These actionssimplify the host processor’s job ofidentifying and executing on the data.

D D/A WD D/A Wa o m l y ck Mo eaveform Playback IP Modulea y k eo m l c Moaveform Playback IP ModuleFactory-installed functions for thistypical Cobalt/Onyx module include asophisticated D/A Waveform PlaybackIP module. A linked-list controllerallows users to easily play back wave-forms stored in either on-board memoryor off- board host memory to thedual D/As.

Parameters including length of wave-form, delay from playback trigger,waveform repetition, etc. can beprogrammed for each waveform.

Up to 64 individual link entriescan be chained together to createcomplex waveforms with a minimumof programming.

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D Ch 1

fromA/D Ch 2

toD/A

GigabitSerial I/O

PCIe FPGAGPIO

(supports user installed IP)

D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4

V A AVIRTEX-6/VIRTEX-7 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE 1

LINKED-LISTDMA ENGINE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

8X 4X 4X 40

GA ataflowFPGA DataflowG af wA at loFPGA Dataflow

9

C mat ForXMC Format

Cobalt & Onyx Formats & Interfaces

D/A Clock/Sync Bus

VCXO

A/D

RF In

RFXFORMR

RF In

RFXFORMR



ONYX: VIRTEX-7 FPGA


TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

A/D



RFXFORMR

RF Out

RFXFORMR

16

CONFIGFLASH64 MB

RFXFORMR

RF Out

RFXFORMR

D/A

DIGITALUPCONVERTER

40 Cobalt48 Onyx

4X

GTX

4X8X

GTX LVDSGTX

Option-104FPGAGPIO

Option-105SerialI/O

8X

P14PMC

P16XMC

P15XMC

PCIe

TIMING BUSGENERATOR


GTX

P15XMC

CONFIGFLASH1 GB

ONYXOnly

COBALTOnly

PCIe

FPGAConfigBus


MANAGER

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB



16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

n aXMC InterfaceBoth Cobalt and Onyx XMC productscomply with the VITA 42.0 XMC speci-fication. Each of the two connectorsprovides dual 4X links or a single 8X link.

With dual XMC connectors, the XMCproducts support both x4 and x8 PCIeon the first XMC connector leaving thesecond connector free to support user-installed transfer protocols specific tothe target application.

s e c r ePCI Express InterfaceThe Cobalt XMC includes an industry-standard interface fully compliant withPCI Express Gen. 1 & 2 bus specifications.Gen. 2 provides 4 GB/sec peak datatransfer rate.

The Onyx XMC includes an industry-standard interface fully compliant withPCI Express Gen. 1, 2 & 3 bus specifi-cations. Gen. 3 provides 8 GB/sec peaktransfer rate.

The PCIe interface includes multipleDMA controllers for efficient transfersto and from the module.

Op o e ci l I a eOptional InterfacesOption -104 installs the P14 PMCconnector with 20 pairs of LVDS con-nections (Cobalt) or 24 pairs (Onyx) tothe FPGA for custom I/O.

Option -105 installs the P16 XMCconnector with a single 8X or dual 4Xgigabit links to the FPGA to supportserial protocols.

Here is a photograph of the typicalboard reviewed in detail in the previoussection. In its XMC configuration, eachCobalt or Onyx module complies withthe VITA 42.0 XMC specification andis suitable for mounting on motherboardswith PMC/XMC connectors.

All XMC modules are available incommercial and in several ruggedizationlevels up to and including conductioncooling.

10


I xpr ss FormatPCI Express Format xpr s matI s ForPCI Express Format

D/A Clock/Sync Bus

VCXO

A/D

RF In

RFXFORMR

RF In

RFXFORMR



ONYX: VIRTEX-7 FPGA


TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

A/D



RFXFORMR

RF Out

RFXFORMR

16

CONFIGFLASH64 MB

RFXFORMR

RF Out

RFXFORMR

D/A

DIGITALUPCONVERTER

40 Cobalt48 Onyx

4X

GTX

4X8X

GTX LVDSGTX

Option-104FPGAGPIO

Option-105SerialI/O

8X

PCIe

TIMING BUSGENERATOR


GTX

CONFIGFLASH1 GB

ONYXOnly

COBALTOnly

PCIe

FPGAConfigBus


MANAGER

16

QDRIISRAM8 MB

1616

QDRIISRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB



16

QDRIISRAM8 MB

1616

QDRIISRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

68-pinHeader

x8 PCI Expressx8 PCI Express

Dual 4XSerialConn

The PCI Express format shown here issuitable for mounting in PCs with PCIeconnectors and interfaces. Physically,the XMC module reviewed in the previouspage is mounted on a PCI Express “carrier”board with x8 PCIe motherboard con-nectors. Other connectors on this boardprovide additional interfaces as describedbelow.

The unique design of the PCIe carrierincludes an integrated fan that keepsthe module cool even in demandingsituations while still requiring a singlePCIe slot.

e cOp io l eOptional InterfacesOption -104 connects 20 pairs of LVDSconnections (Cobalt) or 24 pairs (Onyx)from the FPGA on PMC P14 to a 68-pinDIL ribbon-cable header on the PCIeboard for custom I/O.

Option -105 connects two 4X giga-bit serial links from the FPGA on XMCP16 to two 4X gigabit serial connectorsalong the top edge of the PCIe board.

s e c r e r s e cePCI Express InterfacePCI Express InterfaceThe Cobalt PCIe board includes anindustry-standard interface fully com-pliant with PCI Express Gen. 1 & 2 busspecifications. Gen. 2 provides 4 GB/secpeak data transfer rate.

The Onyx PCIe board includes anindustry-standard interface fully com-pliant with PCI Express Gen. 1, 2 & 3bus specifications. Gen. 3 provides8 GB/sec peak transfer rate.

The PCIe interface includes multipleDMA controllers for efficient transfersto and from the module.

11


3 nVPX m tU pe r a3U OpenVPX Format

D/A Clock/Sync Bus

VCXO

A/D

RF In

RFXFORMR

RF In

RFXFORMR



ONYX: VIRTEX-7 FPGA


TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

A/D

Sample Clk /Reference C k In


RFXFORMR

RF Out

RFXFORMR

16

CONFIGFLASH64 MB

RFXFORMR

RF Out

RFXFORMR

D/A

DIGITALUPCONVERTER

4X

GTX

4X8X

GTX LVDSGTX

Option-104FPGAGPIO

Option-105SerialI/O

8X

PCIe

TIMING BUSGENERATOR


GTX

CONFIGFLASH1 GB

ONYXOnly

COBALTOnlyPCIe

FPGAConfigBus


MANAGER

16

QDRIISRAM8 MB

1616

QDRIISRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB



16

QDRIISRAM8 MB

1616

QDRIISRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

40

VPX BACKPLANE

VPX-P2

4X

Gbit

Serial

4X

Gbit

Serial

4X

Gbit

Serial

4X

Gbit

Serial

CROSSBAR

SWITCH

VPX-P1

The OpenVPX format is compatiblewith several VITA standards including:

VITA-46, VITA-48 andVITA-65 (OpenVPXTM SystemSpecification)

Shown here is the 3U OpenVPX COTSversion (left) and the rugged versionwhich is available in several rugge-dization levels up to and includingconduction cooling.

i a I t rfa e Optional Interfaces i I a e a t rf Optional InterfacesOption -104 provides 20 pairs of LVDSconnections between the FPGA and theVPX-P2 connector for custom I/O.

Option -105 connects two 4X giga-bit serial links from the FPGA on XMCP16 to the crossbar switch for routingto VPX-P1.

cFa ri -Fa ric-Fabric-TFabric-T n n C sb r ta Swi cn a n C sb r Switcransparent Crossbar Switchransparent Crossbar SwitchThe 3U OpenVPX Cobalt or Onyx boardfeatures a unique high-speed switchingconfiguration. A fabric-transparent cross-bar switch bridges numerous interfacesand components on the board usinggigabit serial data paths with no latency.

Programmable signal input equaliza-tion and output pre-emphasis settingsenable optimization. Data paths canbe selected as single (1X) lanes, orgroups of four lanes (4X) for routingover to the VPX-P1 connector.

r s e cePCI Express Interface s e c r ePCI Express InterfaceThe Cobalt 3U OpenVPX board includesan industry-standard interface fullycompliant with PCI Express Gen. 1 & 2bus specifications. Gen. 2 provides4 GB/sec peak data transfer rate.

The Onyx 3U OpenVPX boardincludes an industry-standard interfacefully compliant with PCI Express Gen.1, 2 & 3 bus specifications. Gen. 3provides 8 GB/sec peak transfer rate.

The PCIe interface includes multipleDMA controllers for efficient transfersto and from the board.

12


Compa PCI rmatsCompactPCI Formatsompa I m tsC PC r aCompactPCI FormatsAs shown here, the CompactPCI formatis available in three configurations:

■ 6U cPCI with double density; thisconfiguration mounts two XMCmodules on a 6U carrier board.

■ 6U cPCI with single density; thisconfiguration mounts only oneXMC module on a 6U carrierboard.

■ 3U cPCI mounts one XMC moduleon a 3U carrier board

In order to describe these three configu-rations in more detail, we have omittedthe components and circuitry shown inthe previous three formats; we just showthe Virtex-6/Virtex-7 FPGAs with theexternal connections that define thestandard and optional interfaces.

6 u sitU c C e n6U cPCI Double DensityTwo PCIe-to-PCI bridges connect thex4 PCIe interfaces from each XMCmodule to a PCI-to-PCI bridge. Thisbridge connects both modules to the32- or 64-bit, 33/66 MHz PCI/PCI-X bus.

U cPC Opt o l e ce6U cPCI Optional InterfaceU c C t e c P Op o l e6U cPCI Optional InterfaceOption -104 provides 20 pairs of LVDSconnections between the FPGA and theJ3 connector for custom I/O.

The J5 connector supports Option-104 for the 2nd XMC module.

3U t n n c C e c 3U cPCI Optional InterfaceOption -104 provides 20 pairs of LVDSconnections between the FPGA andthe J3 connector for custom I/O.

3U c C le n y 3U cPCI Single Density 3 e n U c C l y 3U cPCI Single DensityA PCIe-to-PCI bridge connects the x4PCIe interface from the XMC moduleto the 32-bit, 33/66 MHz PCI/PCI-X bus.

I in D s t e n i I in e D nsit6U cPCI Single Density6U cPCI Single DensityThe 2nd XMC module, its associatedPCIe-to-PCI bridge and the optionalinterface connection to J5 are notpresent.

VIRTEX-6/VIRTEX-7 FPGA

1st XMC MODULE


2nd XMC MODULE

PCIeto PCI

BRIDGE

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

40 40

LVDS LVDSGTX GTX

Option-104FPGAGPIO

Option-104

FPGAGPIO

PCI/PCI-X Bus

COBALT Only COBALT OnlyONYX Only ONYX Only

32/64-bit, 33/66 MHzcPCI J5cPCI J3

x4PCIe

x4PCIe

GTX GTX

x4PCIe

x4PCIe

x4 PCIe x4 PCIe

CONFIGFLASH1 GB

CONFIGFLASH1 GB

CONFIGFLASH64 MB

CONFIGFLASH64 MB


MANAGER


MANAGER

FPGAConfigBus

FPGAConfig

Bus


PCIeto PCI

BRIDGE

40

LVDS GTX

Option-104FPGAGPIO

PCI/PCI-X Bus

COBALT OnlyONYX Only

32-bit, 33/66 MHzcPCI J3

x4PCIe

GTX

x4PCIe

x4 PCIe

CONFIGFLASH1 GB

CONFIGFLASH64 MB


MANAGER

FPGAConfigBus

13

Support Software

nte R ady l B d upp t P ckagePentek ReadyFlow Board Support Packagee y l B d upp nt R ad t P ckagePentek ReadyFlow Board Support PackageUsers of high-performance data acqui-sition and signal processing boardsoften find themselves frustrated by thefact that when their new devices aredelivered, they are unable to put themto immediate use.

To address this issue, Pentek hasdeveloped the ReadyFlow® BSPs(Board Support Packages) for all of itsboard-level products.

The package contains C-languageexamples that demonstrate the capabili-ties of Pentek products. The examplesincluded provide the answers to mostof the questions that occur with first-time users of these products.

ReadyFlow BSPs are designed toreduce development time during theinitial stages and when new hardware isadded to the system. All packages arebuilt with a consistent style and function-naming convention. Similar parameterson different boards have similar function

.calls, thereby allowing immediate famil-iarity with new hardware.

o a ine n e cCommand Line Interfacea e no in e cCommand Line InterfaceThe Command Line Interface is a pre-compiled executable that runs thehardware right out of the box, withoutthe need to write any code.

Specific to the hardware features ofthe supported board, it allows operat-ing arguments to be entered on thecommand line for control-ling board parameters.

For command line functionsthat control data acquisition,the captured data can besaved in a host file or routedto the Signal Analyzer.

i al A a zSignal Analyzeri l a A a zSignal AnalyzerWhen used with the Com-mand Line Interface, theSignal Analyzer allows users

to immediately start acquiring anddisplaying A/D data. A full-featuredanalysis tool, the Signal Analyzerdisplays data in time and frequencydomains. Built-in measurement func-tions display 2nd and 3rd harmonics,THD (total harmonic distortion), andSINAD (signal to noise and distortion).Interactive cursors allow users to markdata points and instantly calculate ampli-tude and frequency of displayed signals.

e l A D si itnt G e FPG Knte G e l FPGA D si KitPentek GateFlow FPGA Design KitPentek GateFlow FPGA Design Kit

G e g t FP D n KUsing the FPGA Design KitThe GateFlow® FPGA Design Kit allowsthe user to modify, replace and extendthe standard factory-installed functionsin the FPGA to incorporate special modesof operation, new control structures, andspecialized signal-processing algorithms.

The Cobalt or Onyx architectureconfigures the FPGA with standardfactory-supplied interfaces includingmemory controllers, DMA engines, A/Dand D/A interfaces, timing and synchro-nization structures, triggering and gatinglogic, time stamping and header tag-ging, data formatting engines, and thePCIe interface. These resources areconnected to the User ApplicationContainer using well-defined ports thatpresent easy-to-use data and controlsignals, effectively abstracting the lowerlevel details of the hardware.

U e ic o ae l a i o eThe User Application ContainerShown here is the FPGA block diagramof a typical Cobalt/Onyx module. TheUser Application Container holds acollection of different factory-installed

IP modules connected to the variousinterfaces through the standard portssurrounding the container. The specific IPmodules for each product are described infurther detail in the following pages.

The GateFlow Design Kit provides acomplete Xilinx ISE Foundation Toolproject folder containing all the files

necessary for the developer to recompilethe entire project with or without anyrequired changes. VHDL source codefor each IP module provides excel-lent examples of how the IP moduleswork, how they might be modified, andhow they might be replaced with customIP to implement a specific function.

Front Panel Interface

Memory

Controller

MemoryController

Sync Bus

Interface

PCI Express Interface

Global Registers

FLASH Interface

ClockGenerator

Timestamp

TestGenerator

PCI Express Backend

MemoryController

Memory

Controller

V 6 or V 7

FPGA

User Application Container

Defined and

documented

interface signals

Board

RegistersUser

Registers

DMAs P14

LVDS

P16

MGTs

Factory Installed

Base Function Application

A/D & D/A Control

Data Packing & Formatting

Meta Data Files

Linked-List A/D Control

Linked-List D/A Control

14

d 1 2 7 To ls 7 6 0 & 1 2 : Models 71620 & 71720: T ansc v r wit hr A D U Tr i T e D , ransceiver with Three A/Ds, DUC, T XMwo / s wo D/As - XMC



ONYX: VIRTEX-7 FPGA


16

CONFIGFLASH64 MB

40 Coba t48 Onyx

4X

GTX

4X8X

GTX LVDSGTX

Option-104FPGAGPIO

Option-105SerialI/O

8X

P14PMC

P16XMC

P15XMC

PCIe

GTX

P15XMC

CONFIGFLASH1 GB

ONYXOnly

COBALTOnly

PCIe

FPGAConfigBus


MANAGER

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB



16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

TIMING BUSGENERATOR


VCXO

TTL Gate / TrigTTL Sync / PPS

Sample ClkReset

Gate A/DGate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

Sample C k /Reference Clk In

200 MHz16 BIT A/D

RFXFORMR

RFXFORMR

200 MHz16 BIT A/D

800 MHz16 BIT D/A

RFXFORMR

321616

RFXFORMR

RFXFORMR

800 MHz16 BIT D/A

DIGITALUPCONVERTER

RFXFORMR

200 MHz16 BIT A/D

16

RF In RF In RF In RF OutRF Out

D/AClock/Sync

Bus

A/DClock/Sync

Bus

RFXFORMR

Model 71620 is a member of the Cobaltfamily of high performance XMC mod-ules based on the Xilinx Virtex-6 FPGA.Model 71720 is a member of the Onyxfamily of high-performance modulesbased on the Virtex-7 FPGA.

These multichannel, high-speed dataconverters, it is suitable for connectionto HF or IF ports of a communicationsor radar system. Their built-in datacapture and playback features offer anideal turnkey solution.

Each model includes three A/Ds,one DUC, two D/As and four banks ofmemory. In addition to supporting PCIExpress as a native interface, these mod-els include general-purpose and gigabitserial connectors for application-specific I/O.

/D t s C v /D C v t s A/D Converters A/D ConvertersThe front end accepts three full-scaleanalog HF or IF inputs on front panelSSMC connectors at +8 dBm into 50ohms with transformer coupling intothree Texas Instruments ADS5485200 MHz, 16-bit A/D converters.

The digital outputs are delivered intothe Virtex-6 FPGA for signal processing,data capture or for routing to othermodule resources.

g a v a Di n e e /A Digital Upconverter and D/AsA TI DAC5688 DUC (digital upconverter)and D/A accepts a baseband real or com-plex data stream from the FPGA which isoptionally interpolated, upconverted andthen delivered to the two D/As.

When operating as a DUC, it interpo-lates and translates real or complexbaseband input signals to any IF centerfrequency up to 360 MHz. It deliversreal or quadrature (I+Q) digital outputsto the dual 16-bit D/A converter. Analogoutput is through a pair of front panelSSMC connectors.

If translation is disabled, the DAC5688acts as a dual interpolating 16-bit D/Awith output sampling rates up to 800 MHz.In both modes the DAC5688 providesinterpolation factors of 2x, 4x and 8x.

Fe sFeatures■ Complete radar and software radio

interface solution

■ Supports Xilinx Virtex-6 LXT andSXT or Virtex-7 VXT FPGAs

■ Model 71720: GateXpress supportsdynamic FPGA reconfigurationacross PCIe

■ Three 200 MHz 16-bit A/Ds

■ One digital upconverter

■ Two 800 MHz 16-bit D/As

■ Model 71620: Up to 2 GB ofDDR3 SDRAM or 32 MB ofQDRII+ SRAM; Model 71720:4 GB of DDR3 SDRAM

■ Sample clock synchronization to anexternal system reference

■ LVPECL clock/sync bus formultimodule synchronization

■ Model 71620: PCI Express (Gen. 1& 2) interface up to x8; Model71720: PCI Express (Gen. 1, 2,and 3) interface up to x8

■ Optional user-configurable gigabitserial interface

■ Optional LVDS connections to theVirtex-6 FPGA for custom I/O

Contact Pentek for availability of rug-ged and conduction-cooled versions

Model 71620 Model 71720

15

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

toD/A

GigabitSerial I/OPCIe

FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4

X X GVIRTEX-6/VIRTEX-7 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

8X 4X 4X 40 Model 7162048 Model 71720

c u i P M q o leA/D Acquisition IP ModulesBoth models feature three A/D Acqui-sition IP Modules for easily capturingand moving data. Each module canreceive data from any of the threeA/Ds, a test signal generator or fromthe D/A Waveform Playback IP Mod-ule in loopback mode.

Each IP module has an associatedmemory bank for buffering data inFIFO mode or for storing data in tran-sient capture mode. All memorybanks are supported with DMAengines for easily moving A/D datathrough the PCIe interface.

These powerful linked-list DMAengines are capable of a uniqueAcquisition Gate Driven mode. In thismode, the length of a transfer per-formed by a link definition need notbe known prior to data acquisition;rather, it is governed by the length ofthe acquisition gate. This is extremelyuseful in applications where an exter-nal gate drives acquisition and theexact length of that gate is not knownor is likely to vary.

For each transfer, the DMA enginecan automatically construct metadatapackets containing A/D channel ID,a sample-accurate time stamp and datalength information. These actionssimplify the host processor’s job ofidentifying and executing on the data.

D/A W a o l y ck m b Mo laveform Playback IP ModuleThe factory-installed functions in bothmodels include a sophisticated D/AWaveform Playback IP module. Alinked-list controller allows users toeasily play back to the dual D/Aswaveforms stored in either on-boardmemory or off-board host memory.

Parameters including length ofwaveform, delay from playback trigger,waveform repetition, etc. can be program-med for each waveform.

Up to 64 individual link entriescan be chained together to create com-plex waveforms with a minimum ofprogramming.

n t l l d I u sInstalled IP Modules

The factory-installed functions in bothmodels include three A/D acquisitionand a D/A waveform playback IP mod-ules, ideally matched to the board’sanalog interfaces.

IP modules for either DDR3 orQDRII+ memories, a controller for alldata clocking and synchronizationfunctions, a test signal generator, and a

PCIe interface complete the factory-installed functions and enable thesemodels to operate as a complete turn-key solution, without the need todevelop any FPGA IP.

o ls 7 6 0 & 1 2 : M Models 71620 & 71720: T i T D r e e h e / s, C ransceiver with Three A/Ds, DUC, T wo / s D A - Cwo D/As - XMC

16

o A Also A a bvailable p c fica ioSpecificationsp c icf a ioSpecifications

Model 78620x8 PCI Express

Model 53620 3U VPXCOTS and rugged

Front Panel Analog Signal InputsInput Type: Transformer-coupled,front panel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Input: +8 dBm into50 ohms3 dB Passband: 300 kHz to 700 MHz

A/D ConvertersType: Texas Instruments ADS5485Sampling Rate: 10 MHz to 200 MHzResolution: 16 bits

D/A ConvertersType: Texas Instruments DAC5688Input Data Rate: 250 MHz max.Output IF: DC to 400 MHz max.Output Signal: 2-channel real or1-channel with frequency translationOutput Sampling Rate: 800 MHzmax. with interpolationResolution: 16 bits

Front Panel Analog Signal OutputsOutput Type: Transformer-coupled,front panel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Output: +4 dBm into50 ohms3 dB Passband: 300 kHz to 700 MHz

Sample Clock Sources: On-board clocksynthesizer generates two clocks:one A/D clock and one D/A clock

Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to810 MHz), front panel externalclock or LVPECL timing busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLLsystem reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16, independently for the A/Dclock and D/A clock

External ClockType: Front panel female SSMC con-nector, sine wave, 0 to +10 dBm,AC-coupled, 50 ohms, accepts 10to 800 MHz divider input clock orPLL system reference

Timing Bus: 26-pin connector LVPECLbus includes, clock/sync/gate/PPSinputs and outputs; TTL signal forgate/trigger and sync/PPS inputs

Model 71620 FPGAStandard: CXC6VLX130TOptional: Xilinx Virtex-6XC6VLX240T, XC6VLX365T,XC6VSX315T, or XC6VSX475T

Model 71720 FPGAStandard: Xilinx Virtex-7XC7VX485T-2Optional: Xilinx Virtex-7XC7VX330T-2 or XC7VX690T-2

Custom I/OOption -104: Installs the PMC P14connector with 20 LVDS pairs ( Model71620) or 24 pairs (Model 71720)to the FPGAOption -105: Installs the XMC P16connector configurable as one 8Xor two 4X gigabit serial links to theFPGA

MemoryModel 71620Option 150 or 160: Two 8 MBQDRII+ SRAM memory banks,400 MHz DDROption 155 or 165: Two 512 MBDDR3 SDRAM memory banks,400 MHz DDRModel 71720Type: DDR3 SDRAMSize: Four banks, 1 GB each

PCI-Express InterfaceModel 71660PCI Express Bus: Gen. 1: x4 or x8;Gen. 2: x4Model 71760PCI Express Bus: Gen. 1, 2 or 3: x4or x8; Gen. 3 available only withthe VX330T-2 or VX690T-2 FPGAs

EnvironmentalOperating Temp: 0° to 50° CStorage Temp: –20° to 90° CRelative Humidity: 0 to 95%, non-cond.

Size: Standard XMC module, 2.91 in. x5.87 in.

d 1 2 7 To ls 7 6 0 & 1 2 : Models 71620 & 71720: T ansc v r wit hr A D U Tr i T e D , ransceiver with Three A/Ds, DUC, T XMwo / s wo D/As - XMC


Model 746206U cPCI

Model 737203U cPCI

17

M de 7 6 1 Model 71621: T r e e e / s, C , Tc h hr D , D ransceiver with Three A/Ds, DDCs, DUC, T wo / s D A - Cwo D/As - XMC

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

PCIe

8Xfrom previousboard

to nextboard

sum out

sum in

VIRTEX-6 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE 1

A/D

ACQUISITION

IP MODULE 2

A/D

ACQUISITION

IP MODULE 3




METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

MUX MUX MUX

DATA PACKING &FLOW CONTROL



AURORAGIGABITSERIAL

INTERFACE

INPUT MULTIPLEXER

�

SUMMER

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

BEAMFORMER CORE

DDCDEC: 2 TO 65536

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

MUXDDC CORE DDC CORE DDC CORE

D/A

WAVEFORM

PLAYBACK

IP MODULE

toD/A

D/A loopbackTEST

SIGNALGENERATOR

MUX


toMem

Bank 4

MEMORYCONTROL


DATA UNPACKING& FLOW CONTROL

INTERPOLATOR2 TO 65536

IP CORE

8X4X 4X

The model 71621 consists of a Model71620 as described previously, but withthe addition of three multiband DDCs,one interpolator and one beamformer

DD P C rDDC IP CoresWithin each A/D Acquisition IPModule is a powerful DDC IP core.Because of the flexible input routingof the A/D Acquisition IP Modules,many different configurations can beachieved including one A/D drivingall three DDCs or each of the threeA/Ds driving its own DDC.

Each DDC has an independent32-bit tuning frequency setting thatranges from DC to ƒs, where ƒs isthe A/D sampling frequency. EachDDC can have its own unique deci-mation setting, supporting as many asthree different output bandwidths forthe board. Decimations can be program-med from 2 to 65,536 providing awide range to satisfy most applications.

The decimating filter for eachDDC accepts a unique set of user-supplied 18-bit coefficients. The 80%default filters deliver an output band-width of 0.8*ƒs/N, where N is thedecimation setting. The rejection ofadjacent-band components withinthe 80% output bandwidth is betterthan 100 dB. Each DDC delivers acomplex output stream consisting of24-bit I + 24-bit Q or16-bit I + 16-bitQ samples at a rate of ƒs/N.

IP Cores installed in the Virtex-6 FPGA.These IP Cores are in addition to thefactory-installed IP Modules describedin the Model 71620.

n l o I e oInterpolator IP CoreThe DAC5688 provides interpolationfactors of 2x, 4x and 8x. In additionto the DAC5688, an FPGA-basedinterpolator core provides additionalinterpolation from 2x to 65,536x.

The two interpolators can be com-bined to crate a total range from 2x to524,288x.

m C ra o Beamformer IP CoreIn addition to the DDCs, the 71621features a complete beamformingsubsystem. Each DDC core containsprogramable I & Q phase and gainadjustments followed by a power meterthat continuously measures the indi-vidual average power output. The timeconstant of the averaging interval foreach meter is programmable up to 8Ksamples. The power meters presentaverage power measurements for eachDDC core output in easy-to-readregisters.

In addition, each DDC core includesa threshold detector to automaticallysend an interrupt to the processor ifthe average power level of any DDCcore falls below or exceeds a program-mable threshold.

A programmable summationblock provides summing of any of thethree DDC core outputs. An additionalprogrammable gain stage compen-sates for summation change bit growth.A power meter and threshold detectblock is provided for the summedoutput. The output is then directed backinto the A/D Acquisition IP Module 1FIFO for reading over the PCIe. Forlarger systems, multiple 71621’s canbe chained together via a built-inXilinx Aurora gigabit serial interfacethrough the P16 XMC connector. Thisallows summation across channels onmultiple boards.

18

M l e 7 6 1 Model 71621: T r e , C U Tce h h e / s D D , ransceiver with Three A/Ds, DDCs, DUC, T / XMwo s - Cwo D/As - XMC



o AAlso Ao A Also A a bvailablea bvailable p c icf a ioSpecifications

Front Panel Analog Signal InputsInput Type: Transformer-coupled,front panel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Input: +8 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz


Digital DownconvertersQuantity: Three channelsDecimation Range: 2x to 65,536x intwo stages of 2x to 256xLO Tuning Freq. Resolution: 32 bits,0 to ƒsLO SFDR: >120 dBPhase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: 18-bit coefficients, 24-bitoutput, with user programmable coef-ficientsDefault Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dBstopband attenuation

D/A ConvertersType: Texas Instruments DAC5688Input Data Rate: 250 MHz max.Output IF: DC to 400 MHz max.Output Signal: 2-channel real or1-channel with frequency translationOutput Sampling Rate: 800 MHzmax. with 2x, 4x or 8x interpolationResolution: 16 bits

Digital InterpolatorInterpolation Range: 2x to 65,536xin two stages of 2x to 256x

BeamformerSummation: Three channels on-board;multiple boards can be summed viaSummation Expansion ChainSummation Expansion Chain: Onechain in and one chain out link viaXMC connector using Aurora protocolPhase Shift Coefficients: I & Qwith 16-bit resolutionGain Coefficients: 16-bit resolutionChannel Summation: 24-bitMultiboard Summation Expansion:32-bit

Front Panel Analog Signal OutputsOutput: Transformer-coupled, frontpanel female SSMC connectorsTransformer: Coil Craft WBC4-6TLB

Full Scale Output: +4 dBm into50 ohms3 dB Passband: 300 kHz to 700 MHz


Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to810 MHz), front panel externalclock or LVPECL timing busSynchronization: VCXO can belocked to an external 4 to 180 MHzPLL system reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16, independently for the A/Dclock and D/A clock



Field Programmable Gate ArrayStandard: Xilinx Virtex-6XC6VLX240TOptional: Xilinx Virtex-6XC6VLX365T, XC6VSX315T, orXC6VSX475T

Custom I/OOption -104: Installs the PMC P14connector with 20 LVDS pairs tothe FPGA

MemoryOption 150 or 160: Two 8 MBQDRII+ SRAM memory banks,400 MHz DDROption 155 or 165: Two 512 MBDDR3 SDRAM memory banks,400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen. 1: x4 or x8;Gen. 2: x4



Model 746216U cPCI

Model 736213U cPCI

19

M e 1 G z / , 1 z / Xod 1 3 : H H D A - CModel 71630: 1 GHz A/D, 1 GHz D/A - XMC

TIMING BUSGENERATOR

Clock / Sync /Gate / PPS D/A Clock/Sync Bus

VCXO

VIRTEX-6 FPGA


16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16 1616 16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12

Memory Banks 1 & 2 Memory Banks 3 & 4DDR3 option 155 DDR3 option 165

Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

40

GigabitSerial I/O

(option 105)

4X4X

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

GTXGTX LVDSGTX

a rFeatures■ Complete radar and software radio

interface solution

■ Supports Xilinx Virtex-6 LXT andSXT FPGAs

■ One 1 GHz 12-bit A/D

■ One 1 GHz 16-bit D/A

■ Up to 2 GB of DDR3 SDRAM or16 MB of QDRII+ SRAM


■ LVPECL sync bus for multimodulesynchronization

■ PCI Express (Gen. 1 & 2) interfaceup to x8




Model 71630 is a member of the Cobaltfamily of high performance XMC mod-ules based on the Xilinx Virtex-6 FPGA.A high-speed data converter, it is suit-able for connection to HF or IF ports ofa communications or radar system. Itsbuilt-in data capture and playbackfeatures offer an ideal turnkey solutionas well as a platform for developing

and deploying custom FPGA process-ing IP.

It includes 1 GHz A/D and D/A con-verters and four banks of memory. Inaddition to supporting PCI ExpressGen. 2 as a native interface, the Model71630 includes optional general pur-pose and gigabit serial card connectorsfor application-specific I/O.

e e o A/D ConverterThe front end accepts an analog HF orIF input on a front panel SSMC connectorwith transformer coupling into a TexasInstruments ADS5400 1 GHz, 12-bitA/D converter.

The digital outputs are deliveredinto the Virtex-6 FPGA for signal process-ing, data capture or for routing to othermodule resources.

e /A o r /A o e r D/A Converter D/A ConverterThe 71630 features a TI DAC5681Z1 GHz, 16-bit D/A. The converter hasan input sample rate of 1 GSPS, allow-ing it to acept full rate data from theFPGA. Additionally, the D/A includes a2x or 4x interpolation filter for applica-tions that provide 1/2 or 1/4 rate inputdata. Analog output is transformer-coupled to a front panel SSMC connector.

20

d 1 3 : z / , H Co l H A D D A - Model 71630: 1 GHz A/D, 1 GHz D/A - XMC

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4

OVIRTEX-6 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 40

I a d IP d let M sI ta d IP M dulesInstalled IP ModulesInstalled IP Modules

c i P M e q o lA/D Acquisition IP ModuleThe 71630 features an A/D Acquisi-tion IP Module for easy capture anddata moving. The IP module canreceive data from the A/D, a testsignal generator, or from the D/AWaveform Playback IP Module inloopback mode. The IP module hasassociated memory banks for buffer-ing data in FIFO mode or for storingdata in transient capture mode. Thememory banks are supported with aDMA engine for moving A/D datathrough the PCIe interface.

This powerful linked-list DMAengine is capable of a unique Acqui-sition Gate Driven mode. In thismode, the length of a transfer per-formed by a link definition need notbe known prior to data acquisition;rather, it is governed by the length ofthe acquisition gate. This is extremelyuseful in applications where anexternal gate drives acquisition andthe exact length of that gate is notknown or is likely to vary.

For each transfer, the DMA enginecan automatically construct metadatapackets containing a sample-accuratetime stamp, and data length infor-mation. These actions simplify thehost processor’s job of identifyingand executing on the data.

/ D/A W a a k lef a c IP oaveform Playback IP ModuleThe Model 71630 factory-installedfunctions include a sophisticatedD/A Waveform Playback IP module.A linked-list controller allows usersto easily play back waveforms storedin either on-board memory or off- boardhost memory to the D/A.

Parameters including length of wave-form, delay from playback trigger,waveform repetition, etc. can beprogrammed for each waveform.

Up to 64 individual link entriescan be chained together to createcomplex waveforms with a minimumof programming.

The 71630 factory-installed functionsinclude an A/D acquisition and a D/Awaveform playback IP module. Inaddition, IP modules for either DDR3

or QDRII+ memories, a controller forall data clocking and synchronizationfunctions, a test signal generator and aPCIe interface complete the factory-

installed functions and enable the71630 to operate as a completeturnkey solution, without the need todevelop any FPGA IP.

21

M e 1 G z / , 1 z / Xod 1 3 : H H D A - CModel 71630: 1 GHz A/D, 1 GHz D/A - XMC




Front Panel Analog Signal InputsInput Type: Transformer-coupled,front panel female SSMC connectors

A/D ConverterType: Texas Instruments ADS5400Sampling Rate: 100 MHz to 1 GHzResolution: 12 bits

D/A ConverterType: Texas Instruments DAC5681ZInput Data Rate: 1 GHz max.Interpolation Filter: bypass, 2x or 4xOutput Sampling Rate: 1 GHz max.Resolution: 16 bits

Front Panel Analog Signal OutputsOutput Type: Transformer-coupled,front panel female SSMC connectors

Sample Clock Sources: On-boardclock synthesizer generates twoclocks: one A/D clock and one D/Aclock

Clock SynthesizerClock Source: Selectable from on-board programmable VCXO or frontpanel external clockVCXO Frequency Ranges: 10 to945 MHz, 970 to 1134 MHz, and1213 to 1417 MHzSynchronization: VCXO can belocked to an external 4 to 200 MHzPLL system reference, typically10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16, independently for the A/Dclock and D/A clock

External ClockType: Front panel female SSMCconnector, sine wave, 0 to +10 dBm,AC-coupled, 50 ohms, accepts100 MHz to 1 GHz divider inputclock, or PLL system reference

Timing Bus: 7-pin connectors, LVPECLbus for sync and gate, one A/Dconnector and one D/A connector

External Trigger InputType: Front panel female SSMCconnector, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate ArrayStandard: Xilinx Virtex-6XC6VLX130T-2Optional: Xilinx Virtex-6XC6VLX240T-2, XC6VLX365T-2,XC6VSX315T-2, or XC6VSX475T-2

Custom I/OOption -104: Installs the PMC P14connector with 20 LVDS pairs tothe FPGAOption -105: Installs the XMC P16connector configurable as one 8Xor two 4X gigabit serial links to theFPGA

MemoryOption 150: Two 8 MB QDRII+SRAM memory banks, 400 MHzDDROption 155 or 165: Two 512 MBDDR3 SDRAM memory banks,400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen.1 or Gen.2, x4or x8


Size: Standard XMC module, 2.91 in. x5.87 in.Model 74630

6U cPCIModel 73630

3U cPCI

22

de o l 1 4 : Model 71640: C-1-Ch e annel Hz -. G 2 Ch3.6 GHz or 2-Ch ann l e annel 8 . Hz1.8 GHz , , 1 C- A/ - XM12-bit A/D - XMC

a rFeaturesa rFeatures■ Ideal radar and software radio inter-

face solution


■ One-channel mode with 3.6 GHz,12-bit A/D

■ Two-channel mode with 1.8 GHz,12-bit A/Ds

■ 2 GB of DDR3 SDRAM

■ Sync bus for multimodulesynchronization

■ PCI Express Gen. 2 interface x8




TIMING BUSGENERATOR


VIRTEX-6 FPGA


32

Gate In

Reset In

Sync Bus

Sample C k

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

3.6 GHz (1 Channel)or

1.8 GHz (2 Channel)12-Bit A/D

12

Memory Banks 1 & 2 Memory Banks 3 & 4

TTLPPS/Gate/Sync

40

GigabitSerial I/O

(option 105)

4X4X

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

GTXGTX LVDSGTX

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

Model 71640 is a member of the Cobaltfamily of high performance XMC mod-ules based on the Xilinx Virtex-6 FPGA.A high-speed data converter, it is suit-able for connection to HF or IF ports ofa communications or radar system. Itsbuilt-in data capture features offer anideal turnkey solution as well as a plat-

form for developing and deployingcustom FPGA processing IP.

It includes a 3.6 GHz, 12-bit A/Dconverter and four banks of memory.In addition to supporting PCI ExpressGen. 2 as a native interface, the Model71640 includes optional general pur-pose and gigabit serial connectors forapplication-specific I/O.

C v n eA/D ConverterThe front end accepts analog HF or IFinputs on a pair of front panel SSMCconnectors with transformer couplinginto a Texas Instruments ADC12D180012-bit A/D. The converter operates insingle-channel interleaved mode witha sampling rate of 3.6 GHz and aninput bandwidth of 1.75 GHz; or, indual-channel mode with a samplingrate of 1.8 GHz and input bandwidthof 2.8 GHz.

The ADC12D1800 provides aprogrammable 15-bit gain adjustmentallowing the 71640 to have a fullscale input range of +2 dBm to +4 dBm.A built-in AutoSync feature supports A/Dsynchronization across multiple modules.

The A/D digital outputs are deliveredinto the Virtex-6 FPGA for signal pro-cessing, data capture or for routing toother module resources.

23

M e 7 6 0 od Model 71640: Ch1-Ch nn e annel 6 Hz -. G 2 h3.6 GHz or 2-Ch an l ne annel 1 8 1.8 GHz , , 1 t D - / - XMC12-bit A/D - XMC

PCIe INTERFACE

fromA/D


FPGAGPIO


V X A A W AVIRTEX-6 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR

MEMORYCONTROLLER

8X 4X 4X 40toMem

Bank 2

toMem

Bank 1

fromA/D


A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

(Two channel mode shown)

q Mo e n l q n Mo leA/D Acquisition IP ModuleA/D Acquisition IP ModuleThe 71640 features an A/D Acquisi-tion IP Module for easy capture anddata moving. The IP module canreceive data from the A/D, or a testsignal generator. The IP module hasassociated memory banks for buffer-ing data in FIFO mode or for storingdata in transient capture mode. Insingle-channel mode, all four banksare used to store the single-channelof input data. In dual-channel mode,memory banks 1 and 2 store datafrom input channel 1 and memorybanks 3 and 4 store data from inputchannel 2. In both modes, continu-ous, full-rate transient capture of12-bit data is supported.

The memory banks are supportedwith a DMA engine for moving A/D

s l M ul os ll Mo uInstalled IP ModulesInstalled IP Modules

The 71640 factory-installed functionsinclude an A/D acquisition IP module.In addition, IP modules for DDR3memories, a controller for all data

clocking and synchronization functions,a test signal generator and a PCIeinterface complete the factory-installed

functions and enable the 71640 tooperate as a complete turnkey solution,without the need to develop any FPGA IP.

data through the PCIe interface. Thispowerful linked-list DMA engine iscapable of a unique Acquisition GateDriven mode. In this mode, the lengthof a transfer performed by a linkdefinition need not be known prior todata acquisition; rather, it is governedby the length of the acquisition gate.This is extremely useful in applicationswhere an external gate drives acquisi-tion and the exact length of that gateis not known or is likely to vary.

For each transfer, the DMA enginecan automatically construct metadatapackets containing a sample-accuratetime stamp, and data length informa-tion. These actions simplify the hostprocessor’s job of identifying andexecuting on the data.

24

de o l 1 4 : Model 71640: C-1-Ch e annel Hz -. G 2 Ch3.6 GHz or 2-Ch ann l e annel 8 . Hz1.8 GHz , , 1 C- A/ - XM12-bit A/D - XMC

o A Also A a bvailable c i a oif icifi a ioSpecificationsSpecifications



Front Panel Analog Signal InputsInput Type: Transformer-coupled,front panel female SSMC connectors

A/D ConverterType: Texas InstrumentsADC12D1800Sampling Rate: Single-channel mode:500 MHz to 3.6 GHz; dual-channelmode: 150 MHz to 1.8 GHzResolution: 12 bitsInput Bandwidth: single-channelmode: 1.75 GHz; dual-channelmode: 2.8 GHzFull Scale Input: +2 dBm to +4 dBm,programmable

Sample Clock Sources: Front panelSSMC connector

Sync Bus: Multi-pin connectors, busincludes gate, reset and in and outref clock

External Trigger InputType: Front panel female SSMCconnector, TTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS



Memory: Four 512 MB DDR3 SDRAMmemory banks, 400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen. 2:x4 or x8



Model 746406U cPCI

Model 736403U cPCI

25

o 1 5 : Tl Model 71650: T a s iv r w t r i Transceiver with T D , T / , C wo A/Ds, DUC, T wo / s X D A - Cwo D/As - XMC

D/AClock/Sync

Bus

VCXO

500 MHz12-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-6 FPGA


16

QDRIISRAM8 MB

TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

500 MHz12-BIT A/D

Sample Clk /Reference Clk In A/D

Clock/SyncBus 800 MHz

16-BIT D/A

RFXFORMR

321616

RF Out

RFXFORMR

16 16

ConfigFLASH64 MB

16

QDRIISRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII option 150

16

QDRIISRAM8 MB

1616

QDRIISRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII option 160

DDR3 option 165

TTLPPS/Gate/Sync

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

TIMING BUSGENERATOR


a rFeatures■ Complete radar and software radio

interface solution


■ Two 500 MHz 12-bit A/Ds



■ Up to 2 GB of DDR3 SDRAM or32 MB of QDRII+ SRAM




■ Optional user configurable gigabitserial interface



Model 71650 is a member of the Cobaltfamily of high performance XMC mod--ules based on the Xilinx Virtex-6 FPGA.A multichannel, high-speed data con-verter, it is suitable for connection toHF or IF ports of a communications orradar system. Its built-in data captureand playback features offer an idealturnkey solution as well as a platform

for developing and deploying customFPGA processing IP.

It includes two A/Ds, one DUC, twoD/As, and four banks of memory. Inaddition to supporting PCI Express Gen. 2as a native interface, the Model 71650includes optional general-purpose andgigabit serial card connectors for appli-cation-specific I/O.

A o r rA/D Converter oA r rA/D ConverterThe front end accepts two full-scaleanalog HF or IF inputs on front panelSSMC connectors at +5 dBm into 50ohms with transformer coupling intotwo Texas Instruments ADS5463500 MHz, 12-bit A/D converters.

The digital outputs are deliveredinto the Virtex-6 FPGA for signal pro-cessing, data capture or for routing toother module resources.

Dig a c n e e D/AsDigital Upconverter and D/Asg a n Di c e e D/AsDigital Upconverter and D/AsA TI DAC5688 DUC and D/A acceptsa baseband real or complex data streamfrom the FPGA which is optionallyinterpolated, upconverted and thendelivered to the two D/As.

When operating as a DUC, it interpo-lates and translates real or complexbaseband input signals to any IF centerfrequency up to 360 MHz. It deliversreal or quadrature (I+Q) digital outputsto the dual 16-bit D/A converter. Analogoutput is through a pair of front panelSSMC connectors.

If translation is disabled, the DAC5688acts as a dual interpolating 16-bit D/Aconverter with output sampling ratesup to 800 MHz. In both modes theDAC5688 provides interpolation factorsof 2x, 4x and 8x.

26

ode Tl 1 5 : Model 71650: T n c h a s iv r wit ransceiver with T A D U T , D , wo A/Ds, DUC, T XMwo / s wo D/As - XMC

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D Ch 1

fromA/D Ch 2

toD/A

GigabitSerial I/O

PCIe FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4

XVIRTEX-6 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

8X 4X 4X 40

The 71650 factory-installed functionsinclude two A/D acquisition and oneD/A waveform playback IP modules. Inaddition, IP modules for either DDR3

or QDRII+ memories, a controller forall data clocking and synchronizationfunctions, a test signal generator and aPCIe interface complete the factory-

installed functions and enable the 71650to operate as a complete turnkey solu-tion, without the need to develop anyFPGA IP.

s l M ul oInstalled IP Modules

c u i P M q o leA/D Acquisition IP ModulesThe 71650 features two A/D Acquisi-tion IP Modules for easy capture anddata moving. Each IP module canreceive data from either of the twoA/Ds, a test signal generator or fromthe D/A Waveform Playback IP Mod-ule in loopback mode. Each IP modulehas an associated memory bank forbuffering data in FIFO mode or forstoring data in transient capture mode.All memory banks are supportedwith DMA engines for moving A/Ddata through the PCIe interface.

These powerful linked-list DMAengines are capable of a uniqueAcquisition Gate Driven mode. Inthis mode, the length of a transferperformed by a link definition neednot be known prior to data acquisition;rather, it is governed by the length ofthe acquisition gate. This is extremelyuseful in applications where an exter-nal gate drives acquisition and theexact length of that gate is not knownor is likely to vary.

For each transfer, the DMA enginecan automatically construct metadatapackets containing A/D channel ID, asample-accurate time stamp, and datalength information. These actionssimplify the host processor’s job ofidentifying and executing on the data.

D D/A W a P ua l y k eaveform Playback IP ModuleThe Model 71650 factory-installedfunctions include a sophisticated D/AWaveform Playback IP module. Alinked-list controller allows users toeasily play back waveforms stored ineither on-board memory or off- boardhost memory to the dual D/As.

Parameters including length of wave-form, delay from playback trigger,waveform repetition, etc. can beprogrammed for each waveform. Upto 64 individual link entries can bechained together to create complexwaveforms with a minimum ofprogramming.

27

o 1 5 : Tl Model 71650: T a s iv r w t r i Transceiver with T D , T / , C wo A/Ds, DUC, T wo / s X D A - Cwo D/As - XMC

Also Av lavailable if a ioif a ioSpecificationsSpecifications




A/D Converters (standard)Type: Texas Instruments ADS5463Sampling Rate: 20 MHz to 500 MHzResolution: 12 bits

A/D Converters (option 014)Type: Texas Instruments ADS5474Sampling Rate: 20 MHz to 400 MHzResolution: 14 bits

D/A ConvertersType: Texas Instruments DAC5688Input Data Rate: 250 MHz, max.Output IF: DC to 400 MHz, max.Output Signal: 2-channel real or1-channel with frequency translationOutput Sampling Rate: 800 MHz,max. with interpolationResolution: 16 bits

Front Panel Analog Signal OutputsOutput Type: Transformer-coupled,front panel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Output: +4 dBm into50 ohms3 dB Passband: 300 kHz to 700 MHz


Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to810 MHz), front panel externalclock or LVPECL timing busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLLsystem reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16, independently for the A/Dclock and D/A clock


Timing Bus: 26-pin front panel con-nector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs;TTL signal for gate/trigger and sync/PPS inputs





PCI-Express InterfacePCI Express Bus: Gen.1 or Gen.2, x4or x8



Model 746506U cPCI

Model 736503U cPCI

28

de o l 1 5 : TModel 71651: T n ce h a s iv r wit ransceiver with T A D D , D , C C wo A/Ds, DDC, DUC, T wo D - C A wo D/As - XMC

The model 71651 consists of a Model71650 as described previously, but withthe addition of two powerful DDCsand a beamformer IP Cores installed in

the Virtex-6 FPGA. These IP Cores arein addition to the factory-installed IPmodules described in the Model71650.

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

PCIe

8Xfrom previousboard

to nextboard

sum out

sum in

V X A OVIRTEX-6 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE 1

A/D

ACQUISITION

IP MODULE 2



METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

MUX MUX



AURORAGIGABITSERIAL

INTERFACE

INPUT MULTIPLEXER

�SUMMER

DDCDEC: 2 TO 131027

DDCDEC: 2 TO 131027

BEAMFORMER CORE

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

MUXDDC CORE DDC CORE

D/A

WAVEFORM

PLAYBACK

IP MODULE

toD/A

D/A loopbackTEST

SIGNALGENERATOR

MUX


toMem

Bank 4

MEMORYCONTROL

DATA UNPACKING& FLOW CONTROL


IP CORE

8X4X 4X

I o sDDC IP Cores I o sDDC IP CoresWithin each A/D Acquisition IPModule is a powerful DDC IP core.Because of the flexible input routingof the A/D Acquisition IP Modules,many different configurations can beachieved including one A/D drivingboth DDCs or each of the two A/Dsdriving its own DDC.

Each DDC has an independent32-bit tuning frequency setting thatranges from DC to ƒs, where ƒs is theA/D sampling frequency. Each DDCcan have its own unique decimationsetting, supporting as many as twodifferent output bandwidths for theboard. Decimations can be program-med from 2 to 131,072 providing awide range to satisfy most applications.


m r C ra o eBeamformer IP CoreIn addition to the DDCs, the 71651features a complete beamformingsubsystem. Each DDC core containsprogramable I & Q phase and gainadjustments followed by a powermeter that continuously measuresthe individual average power output.The time constant of the averaginginterval for each meter is program-mable up to 8K samples. The powermeters present average power mea-

surements for each DDC core out-put in easy-to-read registers.

In addition, each DDC coreincludes a threshold detector toautomatically send an interrupt tothe processor if the average powerlevel of any DDC core falls belowor exceeds a programmable threshold.

A programmable summationblock provides summing of any ofthe two DDC core outputs. An addi-tional programmable gain stagecompensates for summation changebit growth. A power meter andthreshold detect block is providedfor the summed output. The output isthen directed back into the A/DAcquisition IP Module 1 FIFO forreading over the PCIe. For largersystems, multiple 71651’s can bechained together via a built-inXilinx Aurora gigabit serial interfacethrough the P16 XMC connector.This allows summation acrosschannels on multiple boards.

29

M e 7 6 1 od TMode 7 6 1 TModel 71651: TModel 71651: T e e ansc h ansce e h ransceiver with Transceiver with Two A D D D , D , C wo A D DD , D C, wo A/Ds, DDC, DUC, Two A/Ds, DDC, DUC, Two / s X D A - Cwo D/As - X Cwo D/As - XMCwo D/As - XMC



Also Av lavailable if a ioif a ioSpecificationsSpecifications

Front Panel Analog Signal InputsInput Type: Transformer-coupled,front panel female SSMC connectorsTransformer: Coil Craft WBC4-6TLBFull Scale Input: +5 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz

A/D Converters (standard)Type: Texas Instruments ADS5463Sampling Rate: 20 MHz to 500 MHzResolution: 12 bits

A/D Converters (option -014)Type: Texas Instruments ADS5474Sampling Rate: 20 MHz to 400 MHzResolution: 14 bits

Digital DownconvertersQuantity: Two channelsDecimation Range: 2x to 131,072xin two programmable stages of 2xto 256x and one fixed 2x stageLO Tuning Freq. Resolution: 32bits, 0 to ƒsLO SFDR: >120 dBPhase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: 16-bit coefficients, 24-bitoutput, with user programmablecoefficientsDefault Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dBstopband attenuation

D/A ConvertersType: Texas Instruments DAC5688Input Data Rate: 250 MHz max.Output IF: DC to 400 MHz max.Output Signal: 2-channel real or1-channel with frequency translationOutput Sampling Rate: 800 MHzmax. with 2x, 4x or 8x interpolationResolution: 16 bits


BeamformerSummation: Two channels on-board;multiple boards can be summed viaSummation Expansion ChainSummation Expansion Chain: Onechain in and one chain out link viaXMC connector using Aurora protocolPhase Shift Coefficients: I & Q with16-bit resolutionGain Coefficients: 16-bit resolutionChannel Summation: 24-bitMultiboard Summation Expansion:32-bit

Front Panel Analog Signal OutputsOutput: Transformer-coupled, frontpanel female SSMC connectorsTransformer: Coil Craft WBC4-6TLBFull Scale Output: +4 dBm into50 ohms3 dB Passband: 300 kHz to 700 MHz


Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to810 MHz), front panel externalclock or LVPECL timing busSynchronization: VCXO can belocked to an external 4 to 180 MHzPLL system reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16, independently for the A/Dclock and D/A clock





MemoryOption -150: Two 8 MB QDRII+SRAM memory banks, 400 MHz DDROption -155 or -165: Two 512 MBDDR3 SDRAM memory banks,400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen. 2: x4 or x8


Size: Standard XMC, 2.91 in. x 5.87 in.

Model 736513U cPCI

Model 746516U cPCI

30

M 7 -C 0 H A D - Cde 1 6 7 7 0 4 l M MModels 71660 & 71760: 4-Channel 200 MHz A/D - XMC



ONYX: VIRTEX-7 FPGA


16

CONFIGFLASH64 MB

40 Coba t48 Onyx

4X

GTX

4X8X

GTX LVDSGTX

Option-104FPGAGPIO

Option-105SerialI/O

8X

P14PMC

P16XMC

P15XMC

PCIe

GTX

P15XMC

CONFIGFLASH1 GB

ONYXOnly

COBALTOnly

PCIe

FPGAConfigBus


MANAGER

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB



16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

DDR3SDRAM512 MB

DDR3SDRAM

1 GB

TIMING BUSGENERATOR


VCXO


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


Gate / Trigger /Sync / PPS

200 MHz16 BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

200 MHz16 BIT A/D

A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16 BIT A/D

16

RF In

RFXFORMR

200 MHz16 BIT A/D

16

ta rFeatures■ Complete radar and software radio

interface solution

■ Supports Xilinx Virtex-6 LXT andSXT or Virtex-7 VXT FPGAs

■ Model 71720: GateXpress supportsdynamic FPGA reconfigurationacross PCIe

■ Four 200 MHz 16-bit A/Ds

■ Model 71660: Up to 2 GB ofDDR3 SDRAM or 32 MB ofQDRII+ SRAM; Model 71760:4 GB of DDR3 SDRAM



■ Model 71660: PCI Express (Gen. 1& 2) interface up to x8; Model71760: PCI Express (Gen. 1, 2,and 3) interface up to x8




Model 71660 is a member of the Cobaltfamily of high performance XMC mod-ules based on the Xilinx Virtex-6 FPGA.Model 71760 is a member of the Onyxfamily of high-performance modulesbased on the Virtex-7 FPGA.

These multichannel, high-speed dataconverters, are suitable for connection toHF or IF ports of a communications orradar system. Their built-in data capturefeatures offer an ideal turnkey solutionas well as a platform for developingand deploying custom FPGA processing IP.

Each model includes four A/Ds andfour banks of memory. In addition tosupporting PCI Express as a native inter-face, these models include general-purpose and gigabit serial connectors forapplication-specific I/O .

C v n e eA/D ConvertersThe front end accepts four full-scaleanalog HF or IF inputs on front panelSSMC connectors at +8 dBm into50 ohms with transformer couplinginto four Texas Instruments ADS5485200 MHz, 16-bit A/D converters.

The digital outputs are deliveredinto the FPGA for signal processing,data capture or for routing to othermodule resources.

Model 71660 Model 71760

31

o ls 7 6 0 & 1 6 : hanne z / XM 0 -C 0 H A D - CModels 71660 & 71760: 4-Channel 200 MHz A/D - XMC

ta IP ess l M ustal IP M u esInstalled IP ModulesInstalled IP Modules

The factory-installed functions in bothmodels include four A/D acquisition IPmodules.

IP modules for either DDR3 or

QDRII+ memories, a controller for alldata clocking and synchronizationfunctions, a test signal generator, anda PCIe interface complete the factory-

installed functions and enable thesemodels to operate as complete turn-key solutions without the need todevelop any FPGA IP.

A/D isit n I u sA/D Acquisition IP Modules s n I u sA/D i it A/D Acquisition IP ModulesBoth models feature four A/D Acqui-sition IP modules for easily capturingand moving data. Each IP modulecan receive data from any of thefour A/Ds or a test signal generator

Each IP module has an associatedmemory bank for buffering data inFIFO mode or for storing data intransient capture mode. All memorybanks are supported with DMAengines for easily moving A/D datathrough the PCIe interface. Thesepowerful linked-list DMA enginesare capable of a unique AcquisitionGate Driven mode. In this mode, the

length of a transfer performed by a linkdefinition need not be known prior todata acquisition; rather, it is governedby the length of the acquisition gate.This is extremely useful in applica-tions where an external gate drivesacquisition and the exact length ofthat gate is not known or is likely tovary.

For each transfer, the DMA enginecan automatically construct metadatapackets containing A/D channel ID,a sample-accurate time stamp anddata length information. These actionssimplify the host processor’s job ofidentifying and executing on the data.

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4

XVIRTEX-6/VIRTEX-7 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX

INPUT MULTIPLEXERTEST

SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4XFPGAGPIO

40 Model 7166048 Model 71760

32

M 7 -C 0 H A D - Cde 1 6 7 7 0 4 l M MModels 71660 & 71760: 4-Channel 200 MHz A/D - XMC




Front Panel Analog Signal InputsInput Type: Transformer-coupled,front panel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Input: +8 dBm into50 ohms3 dB Passband: 300 kHz to 700 MHz


Sample Clock Sources: On-boardclock synthesizer

Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to810 MHz), front panel external clockor LVPECL timing busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLLsystem reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16 for the A/D clock


Timing Bus: 26-pin front panelconnector; LVPECL bus includes,clock/sync/gate/PPS inputs andoutputs; TTL signal for gate/triggerand sync/PPS inputs

External Trigger InputType: Front panel female SSMCconnector, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync andPPS

Model 71660 FPGAStandard: Xilinx Virtex-6XC6VLX130TOptional: Xilinx Virtex-6XC6VLX240T, XC6VLX365T,XC6VSX315T, or XC6VSX475T

Model 716760 FPGAStandard: Xilinx Virtex-7XC7VX485T-2Optional: Xilinx Virtex-7XC7VX330T-2 or XC7VX690T-2

Custom I/OOption -104: Installs the PMC P14connector with 20 LVDS pairs(Model 71660) or 24 pairs (Model71760) to the FPGAOption -105: Installs the XMC P16connector configurable as one 8Xor two 4X gigabit serial links to theFPGA

MemoryModel 71660Option 150 or 160: Two 8 MBQDRII+ SRAM memory banks,400 MHz DDROption 155 or 165: Two 512 MBDDR3 SDRAM memory banks,400 MHz DDRModel 71760Type: DDR3 SDRAMSize: Four banks, 1 GB each

PCI-Express InterfaceModel 71660PCI Express Bus: Gen. 1: x4 or x8;Gen. 2: x4Model 71760PCI Express Bus: Gen. 1, 2 or 3: x4or x8; Gen. 3 available only withthe VX330T-2 or VX690T-2 FPGAs




Model 746606U cPCI

Model 737603U cPCI

33

de 4 2 0 M / h C B amf r e Xo 1 6 : - hanne Hz D o r CModel 71661: 4-Channel 200 MHz A/D with DDCs and Beamformer - XMC

BEAMFORMER CORE

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

PCIe

8Xfrom prev ousboard

to nextboard

sum out

sum in


A/D

ACQUISITION

IP MODULE 1

A/D

ACQUISITION

IP MODULE 2

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4





METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MUX MUX MUX MUX





AURORAGIGABITSERIAL

INTERFACE

INPUT MULTIPLEXER

�

SUMMER

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

MUXDDC CORE DDC CORE DDC CORE DDC CORE

TESTSIGNAL

GENERATOR



8X4X 4X

The model 71661 consists of a Model71660 as described previously, but withthe addition of four multiband DDCs,and one beamformer IP Cores installed

in the Virtex-6 FPGA. These IP Coresare in addition to the factory-installedIP Modules described in the Model71660.

I o sDDC IP CoresWithin each A/D Acquisition IPModule is a powerful DDC IP core.Because of the flexible input routingof the A/D Acquisition IP Modules,many different configurations can beachieved including one A/D drivingall four DDCs or each of the fourA/Ds driving its own DDC.

Each DDC has an independent32-bit tuning frequency setting thatranges from DC to ƒs, where ƒs isthe A/D sampling frequency. EachDDC can have its own unique deci-mation setting, supporting as many asthree different output bandwidths forthe board. Decimations can be program-med from 2 to 65,536 providing awide range to satisfy most applications.


B f e oe Be f r e P oBeamformer IP CoreBeamformer IP CoreIn addition to the DDCs, the 71661features a complete beamformingsubsystem. Each DDC core containsprogramable I & Q phase and gainadjustments followed by a power meterthat continuously measures the indi-vidual average power output. The timeconstant of the averaging interval foreach meter is programmable up to 8Ksamples. The power meters presentaverage power measurements for eachDDC core output in easy-to-readregisters.

In addition, each DDC core includesa threshold detector to automaticallysend an interrupt to the processor ifthe average power level of any DDCcore falls below or exceeds a program-mable threshold.

A programmable summationblock provides summing of any of thefour DDC core outputs. An additionalprogrammable gain stage compen-sates for summation change bit growth.A power meter and threshold detectblock is provided for the summedoutput. The output is then directed backinto the A/D Acquisition IP Module 1FIFO for reading over the PCIe. Forlarger systems, multiple 71661’s canbe chained together via a built-inXilinx Aurora gigabit serial interfacethrough the P16 XMC connector. Thisallows summation across channels onmultiple boards.

34

M 7 6 1 C l 0 A wi D and e m Mde 4 2 0 M C B amf r e XModel 71661: 4-Channel 200 MHz A/D with DDCs and Beamformer - XMC






Digital DownconvertersQuantity: Four channelsDecimation Range: 2x to 65,536x intwo stages of 2x to 256xLO Tuning Freq. Resolution: 32 bits,0 to ƒsLO SFDR: >120 dBPhase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: 18-bit coefficients, 24-bitoutput, with user programmable co-efficientsDefault Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dBstopband attenuation

BeamformerSummation: Four channels on-board;multiple boards can be summed viaSummation Expansion ChainSummation Expansion Chain: Onechain in and one chain out link viaXMC connector using Aurora protocolPhase Shift Coefficients: I & Qwith 16-bit resolutionGain Coefficients: 16-bit resolutionChannel Summation: 24-bitMultiboard Summation Expansion:32-bit

Sample Clock Sources: On-board clocksynthesizer

Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to810 MHz), front panel externalclock or LVPECL timing busSynchronization: VCXO can belocked to an external 4 to 180 MHzPLL system reference, typically10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16 for the A/D clock










Model 736613U cPCI

Model 746616U cPCI

35

o 1 6 : hanne 2 0 z / h 2 l D Ml 2 -C 0 H D t hanne D XModel 71662: 4-Channel 200 MHz A/D with 32-Channel DDC - XMC

The model 71662 consists of a Model71660 as described previously, but withthe addition of four 8-Channel DDC IPCores installed in the Virtex-6 FPGA.

These IP Cores are in addition to thefactory-installed IP Modules describedin the Model 71660.

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4


A/D

ACQUISITION

IP MODULE 1

A/D

ACQUISITION

IP MODULE 2

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MUX MUX MUX MUX





INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR



DDCCORE

DIGITALDOWN-

CONVERTER

BANK 1: CH 1-8DEC: 16 TO 8192

DDCCORE

DIGITALDOWN-

CONVERTER

BANK 2: CH 9-16DEC: 16 TO 8192

DDCCORE

DIGITALDOWN-

CONVERTER

BANK 3: CH 17-24DEC: 16 TO 8192

DDCCORE

DIGITALDOWN-

CONVERTER

BANK 4: CH 18-32DEC: 16 TO 8192

MemoryBank 4

PCIe INTERFACE

PCIe8X



GigabitSerial I/O

FPGAGPIO


4X 4X 4032MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

I o sDDC IP CoresWithin each A/D Acquisition IPModule is a powerful 8-channelDDC bank. Because of the flexibleinput routing of the A/D AcquisitionIP Modules, many different configu-rations can be achieved includingone A/D driving all 32 DDC chan-nels or each of the four A/Ds drivingits own DDC bank.

Each of the 32 channels has anindependent 32-bit tuning frequencysetting that ranges from DC to ƒs,where ƒs is the A/D sampling frequency.All of the 8 channels within a bankshare a common decimation settingthat can range from 16 to 8192,programmable in steps of 8. Forexample, with a sampling rate of200 MHz, the available output band-widths range from 19.53 kHz to10.0 MHz. Each 8-channel bank can

have its own unique decimationsetting supporting a different band-width associated with each of the fouracquisition modules.

The decimating filter for eachDDC bank accepts a unique set ofuser-supplied 18-bit coefficients. The80% default filters deliver an outputbandwidth of 0.8*ƒs/N, where N isthe decimation setting. The rejectionof adjacent-band componentswithin the 80% output bandwidth isbetter than 100 dB.

Each DDC delivers a complexoutput stream consisting of 24-bit I +24-bit Q samples at a rate of ƒs/N.Any number of channels can beenabled within each bank, select-able from 0 to 8. Each bank includesan output sample interleaver thatdelivers a channel-multiplexedstream for all enabled channelswithin a bank.

36

d 1 6 : 4 h n 2 0 M l D o l - a ne Hz / h 2 n D XMModel 71662: 4-Channel 200 MHz A/D with 32-Channel DDC - XMC






Digital DownconvertersQuantity: Four 8-channel banks,one per acquisition moduleDecimation Range: 16x to 8192x insteps of 8xLO Tuning Freq. Resolution: 32 bits,0 to ƒsPhase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: 18-bit coefficients, 24-bitoutput, with user programmablecoefficientsDefault Filter Set: 80% bandwidth,>100 dB stopband attenuation

Sample Clock Sources: On-board clocksynthesizer

Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to810 MHz), front panel external clockor LVPECL timing busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLLsystem reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16 for the A/D clock

External ClockType: Front panel female SSMCconnector, sine wave, 0 to +10 dBm,AC-coupled, 50 ohms, accepts10 to 800 MHz divider input clock,or PLL system reference





MemoryOption 155 or 165: Two 512 MBDDR3 SDRAM memory banks,400 MHz DDR




Model 736623U cPCI

Model 746626U cPCI

37

M de 4 1 2 H D A wit D Xo 1 7 : hanne G C - CModel 71670: 4-Channel 1.25 GHz D/A with DUC - XMC

a rFeaturesa rFeatures■ Complete radar and software radio

interface solution


■ Four 1.25 GHz 16-bit D/As

■ Four digital upconverters

■ Programmable output levels

■ 250 MHz max. output bandwidth



■ Dual-µSync clock/sync bus formultimodule synchronization





TIMING BUSGENERATOR


VCXOVIRTEX-6 FPGA


16


16

ConfigFLASH64 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

1616

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Clock/SyncBus A

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

Model 71670 is a member of the Cobaltfamily of high performance XMC mod-ules based on the Xilinx Virtex-6 FPGA.This 4-channel, high-speed dataconverter is suitable for connection totransmit HF or IF ports of a communi-cations or radar system. Its built-in dataplayback features offer an ideal turnkey

solution for demanding transmit appli-cations.

The 71670 includes four D/As,four digital upconverters and fourbanks of memory. In addition to support-ing PCI Express Gen. 2 as a nativeinterface, the Model 71670 includesgeneral purpose and gigabit serial con-nectors for application-specific I/O.

gi al Up v rt an Digital Upconverter and D/Ai l Up rt n g a v a Digital Upconverter and D/ATwo Texas Instruments DAC3484s pro-vide four DUC (Digital Upconverter) andD/A channels. Each channel accepts abaseband real or complex data streamfrom the FPGA and provides that inputto the upconvert, interpolate and D/Astage.

When operating as a DUC, it interpo-lates and translates real or complexbaseband input signals to a user select-able IF center frequency. It delivers realor quadrature (I+Q) analog outputs toa 16-bit D/A converter.

If translation is disabled, each D/Aacts as an interpolating 16-bit D/A withoutput sampling rates up to 1.25 GHz.In both modes, the D/A provides interpo-lation factors of 2x, 4x, 8x and 16x.Analog output is through four front panelSSMC connectors.

38

od 1 7 : hanne 1 D C Cl -C . 5 G z / h - Model 71670: 4-Channel 1.25 GHz D/A with DUC - XMC

s ll Mo uInstalled IP Moduless l M ul oInstalled IP Modules

The 71670 factory-installed functionsinclude four D/A waveform playbackIP modules, to support waveform gen-eration through the D/A converters.

IP modules for DDR3 SDRAM memo-ries, a controller for all data clockingand synchronization functions, a testsignal generator, and a PCIe interface

complete the factory-installed functionsand enable the 71670 to operate as acomplete turnkey solution, without theneed to develop any FPGA IP.

/ D/A W ve r P df a a IP aveform Playback IP ModuleThe Model 71670 factory-installedfunctions include a sophisticated D/AWaveform Playback IP module. Fourlinked list controllers support wave-form generation to the four D/Asfrom tables stored in either on-boardmemory or off-board host memory.

Data for Channel 1 and Channel 2are interleaved for delivery to a dualchannel D/A device. For this reason,they must share a common trigger/gate,sample rate, interpolation factor, andother parameters. The same rulesapply to Channel 3 and Channel 4.Parameters including length of wave-form, waveform repetition, etc. can beprogrammed for each channel.

Up to 64 individual link entriesfor each D/A channel can be chainedtogether to create complex waveformswith a minimum of programming.

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2


FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4

X A AVIRTEX-6 FPGA DATAFLOW DETAIL

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16

39

M de 4 1 2 H D A wit D Xo 1 7 : hanne G C - CModel 71670: 4-Channel 1.25 GHz D/A with DUC - XMC

Also Av lavailable c i a oif icifi a ioSpecificationsSpecifications



D/A ConvertersType: TI DAC3484Input Data Rate: 312.5 MHz max.Output Bandwidth: 250 MHz max.Output Sampling Rate: 1.25 GHzmax. with interpolationInterpolation: 2x, 4x, 8x or 16xResolution: 16 bits

Front Panel Analog Signal OutputsQuantity: Four D/A outputsOutput Type: Transformer-coupled,front panel female SSMC connectorsFull Scale Output: Programmablefrom –20 dBm (0.063 Vp-p) to +4 dBm(1.0 Vp-p) in 16 stepsFull Scale Output Programming:1.0x(G+1)/16 Vp-p, where 4-bitinteger G = 0 to 15

Clock SynthesizerClock Source: Selectable from on-board programmable VCXO, frontpanel external clock or µSync tim-ing busesSynchronization: Clocks can be lockedto a front panel 5 or 10 MHz systemreference

External ClockType: Front panel female SSMC con-nector, sine wave, 0 to +10 dBm,AC-coupled, 50 ohms, accepts 10to 500 MHz sample clock or 5 or10 MHz system reference

External Trigger InputType: Front panel female SSMC con-nector, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Timing Bus: 19-pin µSync bus connec-tor includes, clock, reset and gate/trigger inputs and outputs, CML


Custom I/OOption -104: Installs the PMC P14connector with 20 LVDS pairs tothe FPGAOption -105: Installs the XMC P16connector configurable as one 8X ortwo 4X gigabit serial links to the FPGA


PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen 2:x4 or x8;



Model 736703U cPCI

Model 746706U cPCI

40

od 1 7 : hanne 1 A wi D xt I r t - l -C . 5 G z h nde la MModel 71671: 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation - XMC

The model 71671 consists of a Model71670 as described previously, but withthe addition of four wide-range program-mable interpolation IP Cores installed

in the Virtex-6 FPGA. Installed in eachof the four channels, these IP Cores arein addition to the factory-installed IPmodules described in the Model 71670.

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2


FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16


IP CORE


IP CORE


IP CORE


IP CORE

/A WD/A WA W/ D/A W ve orm b Mod laveform Playback IP Moduleo m b Move r d laveform Playback IP ModuleThe Model 71671 factory-installedfunctions include a sophisticated D/AWaveform Playback IP module. Fourlinked-list controllers support wave-form generation to the four D/As fromtables stored in either on-boardmemory or off-board host memory.

Data for Channel 1 and Channel 2are interleaved for delivery to a dualchannel D/A device. For this reason,they must share a common trigger/gate, sample rate, interpolation factor,and other parameters. The same rulesapply to Channel 3 and Channel 4.

Parameters including length ofwaveform, waveform repetition, etc.can be programmed for each channel.

Up to 64 individual link entriesfor each D/A channel can be chainedtogether to create complex wave-forms with a minimum of programming.

41

M 7 6 1 l H / t U E e d n e po o Xde 7 : 4 n 1 2 D A wi D , xt I t r i - CModel 71671: 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation - XMC

Also Av lavailable



Model 736713U cPCI

Model 746716U cPCI

sS e nS e nsSpecificationsSpecifications

D/A ConvertersType: TI DAC3484Input Data Rate: 312.5 MHz max.Output Bandwidth: 250 MHz max.Output Sampling Rate: 1.25 GHzmax. with interpolationInterpolation: 2x, 4x, 8x or 16xResolution: 16 bits


Front Panel Analog Signal OutputsQuantity: Four D/A outputsOutput Type: Transformer-coupled,front panel female SSMC connectorsFull Scale Output: Programmablefrom –20 dBm (0.063 Vp-p) to +4 dBm(1.0 Vp-p) in 16 stepsFull Scale Output Programming:1.0x(G+1)/16 Vp-p, where 4-bitinteger G = 0 to 15

Clock SynthesizerClock Source: Selectable from on-board programmable VCXO, frontpanel external clock or µSync tim-ing busesSynchronization: Clocks can be lockedto a front panel 5 or 10 MHz systemreference

External ClockType: Front panel female SSMC con-nector, sine wave, 0 to +10 dBm,AC-coupled, 50 ohms, accepts 10to 500 MHz sample clock or 5 or10 MHz system reference

External Trigger InputType: Front panel female SSMC con-nector, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Timing Bus: 19-pin µSync bus connec-tor includes, clock, reset and gate/trigger inputs and outputs, CML

Field Programmable Gate ArrayXilinx Virtex-6 XC6VLX240T-2,XC6VLX365T-2, XC6VSX315T-2, orXC6VSX475T-2

Custom I/OOption -104: Installs the PMC P14connector with 20 LVDS pairs tothe FPGAOption -105: Installs the XMC P16connector configurable as one 8X ortwo 4X gigabit serial links to the FPGA


PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen 2:x4 or x8;



42

M e 7 6 0 - a d F od 9 : L B R TMode 7 690: L-Ba d RF TModel 71690: L-Band RF TModel 71690: L-Band RF T e h - ha ne Hz / Xr t C l 0 A D - Cer th -Cha nel 0 Hz A/D - X Cuner with 2-Channel 200 MHz A/D - XMCuner with 2-Channel 200 MHz A/D - XMC

VCXOVIRTEX-6 FPGA


16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

XTALOSC

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


RefOption 100

e stFeatures■ Accepts RF signals from 925 MHz

to 2175 MHz

■ Programmable LNA boosts LNB(low-noise block) antenna signallevels with up to 80 dB gain

■ Programmable analog downcon-verter provides I + Q basebandsignals with bandwidths rangingfrom 4 to 40 MHz



■ 2 GB of DDR3 SDRAM or 32 MBof QDRII+ SRAM


■ PCI Express (Gen. 1 & 2) interface,up to x8

■ Clock/sync bus for multimodulesynchronization



Contact Pentek for availability of ruggedand conduction-cooled versions

Model 71690 is a member of theCobalt family of high performanceXMC modules based on the XilinxVirtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable forconnection directly to the RF port of acommunications or radar system. Itsbuilt-in data capture features offer anideal turnkey solution as well as a

platform for developing and deployingcustom FPGA processing IP.

It includes an L-Band RF tuner, twoA/Ds and four banks of memory. Inaddition to supporting PCI ExpressGen. 2 as a native interface, the Model71690 includes general purpose andgigabit serial connectors for application-specific I/O.

TR RF T runerA front panel SSMC connector acceptsL-Band signals between 925 MHz and2175 MHz from an antenna LNB (lownoise block). A Maxim MAX2112 tunerdirectly converts these L-Band signalsto baseband using a broadband I/Qdownconverter.

The device includes an RF variable-gain LNA (low noise amplifier), a PLL(phase- locked loop) synthesized localoscillator, quadrature (I + Q) down-converting mixers, baseband lowpassfilters with programmable cutoff fre-quency, and variable-gain basebandamplifiers.

The fractional-N PLL synthesizerlocks its VCO to an on-board crystal,the timing generator output, or to an

external reference input between 12and 30 MHz. Together, the basebandamplifiers and the RF LNA offer a program-mable-gain range of more than 80 dB.

An integrated lowpass filter withvariable bandwidth provides band-widths ranging from 4 to 40 MHz,programmable with 8 bits of resolution.

C n e eA/D ConvertersThe analog baseband I and Q analogtuner outputs are then applied to twoTexas Instruments ADS5485 200 MHz,16-bit A/D converters. The digital out-puts are delivered into the Virtex-6FPGA for signal processing, data captureor for routing to other module resources.

43

l 1 9 TM 7 6 0 and F Model 71690: L-Band RF T r wit 2 l - une hann 2 0 M z / XMuner with 2-Channel 200 MHz A/D - XMC

PCIe INTERFACE

fromA/D (I)

fromA/D (Q)

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4

V X A WVIRTEX-6 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXERTEST

SIGNALGENERATOR

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40

The 71690 factory-installed functionsinclude two A/D acquisition IP modules.

IP modules for either DDR3 orQDRII+ memories, a controller for all

s l M ul oInstalled IP Modules

data clocking and synchronizationfunctions, a test signal generator, anda PCIe interface complete the factory-installed functions and enable the

71690 to operate as a completeturnkey solution without the need todevelop any FPGA IP.

Acqu io P M d eA/D Acquisition IP Modules Ac u io P d q M eA/D Acquisition IP ModulesThe 71690 features two A/D Acquisi-tion IP Modules for easily capturingand moving data. Each IP modulecan receive data from either of thetwo A/Ds or a test signal generator

Each IP module has an associatedmemory bank for buffering data inFIFO mode or for storing data intransient capture mode. All memorybanks are supported with DMAengines for easily moving A/D datathrough the PCIe interface. Thesepowerful linked-list DMA enginesare capable of a unique AcquisitionGate Driven mode. In this mode, the

length of a transfer performed by a linkdefinition need not be known prior todata acquisition; rather, it is governedby the length of the acquisition gate.This is extremely useful in applica-tions where an external gate drivesacquisition and the exact length ofthat gate is not known or is likely tovary.

For each transfer, the DMA enginecan automatically construct metadatapackets containing A/D channel ID,a sample-accurate time stamp anddata length information. These actionssimplify the host processor’s job ofidentifying and executing on the data.

44

de L-B R o l 1 9 : TModel 71690: L-Band RF T h -C 0 H D Cr wit 2 l A - uner with 2-Channel 200 MHz A/D - XMC

A ls Also Av lai evailable S e nsS e nsSpecificationsSpecifications



Front Panel Analog Signal InputConnector: Front panel female SSMCImpedance: 50 ohms

L-Band TunerType: Maxim MAX2112Input Frequency Range: 925 MHzto 2175 MHzMonolithic VCO Phase Noise:-97 dBc/Hz at 10 kHzFractional-N PLL Synthesizer:freqVCO = (N.F) x freqREF

where integer N = 19 to 251 andfractional F is a 20-bit binary valuePLL Reference (freqREF): Front panelSSMC connector or on-board 27 MHzcrystal (Option -100), 12 to 30 MHzLNA Gain: 0 to 65 dB, controlled by aprogrammable 12-bit D/A converterBaseband Amplifier Gain:0 to 15 dB, in 1 dB stepsBaseband Low Pass Filter: Cutofffrequency programmable from 4 to40 MHz with 8-bit resolutionDynamic Range: -75 dBm to 0 dBm


Sample Clock Sources: On-boardtiming generator/synthesizer

A/D Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to810 MHz), front panel externalclock or LVPECL timing busSynchronization: VCXO can belocked to an external 4 to 180 MHzPLL system reference, typically10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16, for the A/D clock

Timing Generator External Clock InputType: Front panel female SSMC con-nector, sine wave, 0 to +10 dBm,AC-coupled, 50 ohms, accepts 10to 800 MHz divider input clock orPLL system reference

Timing Generator Bus: 26-pin frontpanel connector LVPECL busincludes, clock/sync/gate/PPS inputsand outputs; TTL signal for gate/triggerand sync/PPS inputs

External Trigger InputQuantity: 2Type: Front panel female SSMCconnector, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate ArrayStandard: Xilinx Virtex-6XC6VLX130TOptional: Xilinx Virtex-6XC6VLX240T, XC6VLX365T,XC6VSX315T, or XC6VSX475T






Model 736903U cPCI

Model 746906U cPCI

45

Performance Graphs

A/D Performance: Models 71620, 71720, 71621, 71660,71760, 71661, 71662Spurious Free Dynamic Range

fin = 70 MHz, fs = 200 MHz, Internal Clock

Spurious Pick-up

fs = 200 MHz, Internal Clock

Two-Tone SFDR

f1 = 30 MHz, f2 = 70 MHz, fs = 200 MHz

Two-Tone SFDR

f1 = 69 MHz, f2 = 71 MHz, fs = 200 MHz

Adjacent Channel Crosstalk Crosstalk

fin Ch2 = 70 MHz, fs = 200 MHz, Ch 1 shown

Input Frequency Response

fs = 200 MHz, Internal Clock

D/A Performance: Models 71620, 71621Spurious Free Dynamic Range

fout = 70 MHz, fs = 200 MHz, Internal Clock

Spurious Free Dynamic Range

fout = 120 MHz, fs = 400 MHz, External Clock

46

od 1 1 : S I r XMl e al P e CModel 71611: Quad Serial FPDP Interface - XMC

FIBER OPTICTRANSCEIVER

VIRTEX-6 FPGA

LX240T, LX365T, SX315T or SX475T

32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

Memory Banks 1 & 2 Memory Banks 3 & 4DDR3 option 155 DDR3 option 165

40

LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P15XMC

RX TX


RX TX


RX TX


RX TX

GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4a rFeatures

■ Complete serial FPDP solution

■ Fully compliant with VITA 17.1specification

■ Up to 2 GB of DDR3 SDRAM

■ PCI Express interface up to x8

■ LVDS connections to the Virtex-6FPGA for custom I/O

Contact Pentek for availability of ruggedand conduction-cooled versions

Model 71611 is a member of theCobalt® family of high performance XMCmodules based on the Xilinx Virtex-6FPGA. A multichannel, gigabit serialinterface, it is ideal for interfacing toserial FPDP data converter boards or asa chassis-to-chassis data link.

The 71611 is fully compatible withthe VITA 17.1 Serial FPDP specifica-tion. Its built-in data transfer features

make it a complete turnkey solution.For users who require application-specificfunctions, the 71611 serves as aflexible platform for developing anddeploying custom FPGA processing IP.

In addition to supporting PCI Expressas a native interface, the Model 71611includes a general-purpose connectorfor application-specific I/O.

e al FPD I t rfaSerial FPDP Interfacee l F D I rfaa P tSerial FPDP InterfaceThe 71611 is fully compatible with theVITA 17.1 Serial FPDP specification.With the capability to support 1.0625,2.125, 2.5, 3.125, and 4.25 Gbaudlink rates and the option for multi-mode and single-mode opticalinterfaces, the board can work in virtu-ally any system. Programmable modesinclude: flow control in both receiveand transmit directions, CRC support,and copy/loop modes.

47

o 1 1 : S Xl e ial P e - CModel 71611: Quad Serial FPDP Interface - XMC


8X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK

SERIAL FPDP RX ENGINE

SERIAL FPDP TX ENGINE

MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE

to optional 512 MBSDRAM buffer

16K x 32FIFO

DMA ENGINE

SERIAL FPDP CHANNEL 1

CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE

SERIAL FPDP CHANNEL 2

RX

TX


CH 3 SERIAL FPDP CHANNEL 3

RX

TX


CH 4 SERIAL FPDP CHANNEL 4

Copy modedata path

c t np c i aSpecificationsFront Panel Serial FPDP Inputs/Outputs

Fiber Optic Connector Type: LC Laser: 850 nm (standard, otheroptions available)Copper Connector Type: MicroTwinaxFiber Optic or Copper Link Rates:1.0625, 2.125, 2.5, 3.125 or 4.25Gbaud (copper rate depends oncable langth)Fiber Optic or Copper Data Trans-fer Rates: 105, 210, 247, 309 or420 MB/sec (depending on linkrate) per serial FPDP port

Field Programmable Gate Array:Xilinx Virtex-6 XC6VLX240T,XC6VLX365T, XC6VSX315T, orXC6VSX475T


MemoryOption 155 or 165: Two 512 MBDDR3 SDRAM memory banks,400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen. 1: x4 or x8


Size: Std XMC module, 2.91 in. x 5.87 in.

o A Also A a bvailable


Model 746116U cPCI

Model 736113U cPCI


n t l o ll d I u sn t ll d I o ul sInstalled IP ModulesInstalled IP ModulesFour identical serial FPDP interfacesare installed in the FPGA. The interfacesare fully compatible with the VITA 17.1serial FPDP specification.

Each interface includes a serialFPDP TX and a serial FPDP RX engine.These are enhanced with DMAengines for efficient transfers to andfrom the board.

48

Complementary Products

od l 1 2 High-S eed ync nize D tr ion oa - P C XMCModel 7192: High-Speed Synchronizer and Distribution Board - PMC/XMCod 1 2 gh-S e ync D r n oa - C XMl Hi e d nize t io P CModel 7192: High-Speed Synchronizer and Distribution Board - PMC/XMC

PLL&

DIVIDER

Gate / Trigger Out

Sample Clk /Reference

Clk InMUX

ClkIn

RefIn

N

PROGRAMMABLEVCXO

Clock /Calibration Out

:N

BUFFER&

PROGRAMDELAYS

Clk/RefIn

Sync OutReference Clk Out

TWSI Control InReference Clk In *

Gate / Trigger OutSync OutReference Clk Out

MUX

Trig/GateIn

SyncIn

TWSICONTROL



Gate / Trigger In

Sync In

�Sync 3

�Sync 2

�Sync 1

�Sync 4

* For 71640 A/D calibration

a rFeaturesa rFeatures■ Synchronizes up to four separate

high-speed Cobalt or Onyx I/Omodules

■ Synchronizes sampling and dataacquisition for multichannel systems

■ Synchronizes gating and triggeringfunctions

■ Clock rates up to 1.8 GHz

■ Front panel MMCX connectorsfor input signals

■ Front panel µSync connectors com-patible with a range of PentekCobalt and Onyx modules

The Model 7192 High-Speed Synchro-nizer and Distribution Board synchronizesmultiple Pentek Cobalt or Onyx moduleswithin a system. It enables synchronoussampling and timing for a wide rangeof multichannel high-speed data acquisi-tion, DSP, and software radio applications.

Up to four modules can be synchro-nized using the 7192, with each receivinga common clock along with timingsignals that can be used for synchro-nizing, triggering and gating functions.

np S nInput Signalsp nn SInput SignalsModel 7192 provides three front panelMMCX connectors to accept inputsignals from external sources: one forclock, one for gate or trigger and onefor a synchronization signal. Clock signalscan be applied from an external sourcesuch as a high performance sine-wavegenerator. Gate/trigger and sync signalscan come from an external system source.In addition to the MMCX connector, areference clock can be accepted throughthe first front panel µSync output connec-tor, allowing a single Cobalt or Onyxboard to generate the clock for allsubsequent boards in the system.

t S gn sOutput Signals S nt g sOutput SignalsThe 7192 provides four front panelµSync output connectors, compatiblewith a range of high-speed PentekCobalt and Onyx modules. The µSyncsignals include a reference clock, gate/trigger and sync signals and are distributedthrough matched cables, simplifyingsystem design.

lo S g sClock Signalslo S g sClock SignalsThe 7192 can accept a user suppliedexternal clock on its front panel MMCXconnector. As an alternative to theexternal clock, the 7192 can use itson-board VCXO (programmable volt-age-controlled crystal oscillator) as theclock source. The VCXO can operatealone or be locked to a system referenceclock signal delivered to the front panelreference clock input.

The external or onboard clock canoperate at full rate or be divided andused to register all sync and gate/triggersignals as well as providing a referenceclock to all connected modules. In addi-tion, the clock is available at the ClockOut MMCX as a sample or referenceclock for other boards in the system.

49


o l 1 2 High-Spe d y onize D tr ion Bo d PMC X CModel 7192: High-Speed Synchronizer and Distribution Board - PMC/XMCo 1 2 igh-S y ze D r on o C Xl H pe d oni t i B d PM CModel 7192: High-Speed Synchronizer and Distribution Board - PMC/XMCt an y c r n t n S nGate and Synchronization Signalst n y n n a c r t n SGate and Synchronization Signals

The 7192 features separate inputs forgate/trigger and sync signals. A program-mable delay allows the user to maketiming adjustments on the gate/triggerand sync signals before they are sentto buffers for output through the µSyncoutput connectors.

a t nCalibrationa t nCalibrationThe 7192 features a calibration outputspecifically designed to work with theModels 71640 or 71740 3.6 GHz A/Dmodules and provide a signal referencefor phase adjustment across multiple D/As.

gra inProgrammingr ing aProgrammingThe 7192 allows programming of oper-ating parameters including: VCXOfrequency, clock dividers, and delaysthat allow the user to make timingadjustments on the gate and sync signals.These adjustments are made before theyare sent to buffers for output throughthe µSync connectors.

The 7192 is programmed via a TWSIcontrol interface on the first µSync connec-tor. The control interface is compatiblewith the front panel µSync connectorsof all high-speed Cobalt and Onyx mod-ules, thereby providing a single cableconnection that carries both controland timing signals.

u o e du tSupported Productsu o u te dSupported ProductsThe 7192 supports all high-speed mod-els in the Cobalt family including the71630 1 GHz A/D and D/A XMC, the71640 3.6 GHz A/D XMC and the71670 Four-channel 1.25 GHz, 16-bitD/A XMC. The 7192 will also supporthigh-speed models in the Onyx familyas they become available.

cifi a ioSpecificationsc i a oif iSpecificationsFront Panel Sample Clock/Reference Input

Connector Type: MMCXInput Impedance: 50 ohmsInput Level: 0 dBm to +10 dBm,sine waveSample Clock Frequency: 100 MHzto 2 GHzReference Frequency: 5 to 100 MHz

Front Panel Gate/Trigger & Sync InputsConnector Type: MMCXInput Level: LVTTL

Front Panel µSync Inputs/OutputsQuantity: 4Connector Type: 19-pin µHDMISignal Level: CMLSignals (µSync connector 1): Refer-ence Clock In, TWSI control In,Reference Clock Out, Gate/TriggerOut, Sync OutSignals (µSync connectors 2–4):Reference Clock Out, Gate/TriggerOut, Sync Out

Front Panel Clock / Calibration OutputConnector Type: MMCXOutput Impedance: 50 ohmsOutput Level: +6 dBm nominal,sine waveSample Clock Frequency: 100 MHzto 1.8 GHz

Programmable VCXO:Frequency Ranges: 10-945 MHz,970-1134 MHz, and 1213-1417.5 MHzTuning Resolution: 32 bitsUnlocked Accuracy: +20 ppm

PLL, Divider & Jitter CleanerType: Texas Instruments CDCM7005Frequency Dividers: 1, 2, 3, 4, 6, 8and 16

PMC/XMC Interface: Power only onPMC P1 or XMC P15


Size: Standard PMC module, 2.91 in. x5.87 in.

o A o AAlso AAlso A a ba bvailablevailable


Model 74926U cPCI

Model 73923U cPCI


50


od l 1 2 ac -mount Hig -Spe d y e S n hro r UnitModel 9192: Rack-mount High-Speed System Synchronizer Unitod 2 ac -m unt ig -S y o nitl 1 o H pe d e S n hr r UModel 9192: Rack-mount High-Speed System Synchronizer Unit

a rFeaturesa rFeatures■ Synchronizes up to twelve separate

high-speed Cobalt or Onyx I/Omodules

■ Synchronizes sampling and dataacquisition for multichannel systems


■ Clock rates up to 1.8 GHz

■ Rear panel SMA connectors forinput signals

■ Rear panel µSync connectorscompatible with a range of PentekCobalt and Onyx modules

PLL&

DIVIDER

Gate / Trigger Out

Sample Clk /Reference

Clk InMUX

ClkIn

RefIn

:N

PROGRAMMABLEVCXO

Clock Out 1

:N

BUFFER&

PROGRAMDELAYS

ClkRefIn

Sync OutReference Clk Out

TWSI Control InReference Clk In *


MUX

Trig/GateIn

SyncIn

TWSICONTROL


Gate / Trigger In

Sync In

�Sync 2

�Sync 1

�Sync 12

* For 71640 A/D calibration

�Sync 3through

�Sync 11

Clock Out 2

Clock Out 12

CLOCKSPLITTER

Clock Out 3throughClock Out 11

External Clk In

MUX

USB-TO-TWSIINTERFACE

USB

The Model 9192 Rack-mount High-SpeedSystem Synchronizer Unit synchronizesmultiple Pentek Cobalt or Onyx moduleswithin a system. It enables synchronoussampling and timing for a wide rangeof multichannel high-speed data acquisi-tion, DSP, and software radio applications.

Up to twelve boards can be synchro-nized using the 9192, with each receivinga common clock along with timingsignals that can be used for synchro-nizing, triggering and gating functions.

p nn SInput SignalsModel 9192 provides four rear panelSMA connectors to accept input signalsfrom external sources: two for clock,one for gate or trigger and one for asynchronization signal. Clock signalscan be applied from an external sourcesuch as a high performance sine-wavegenerator. Gate/trigger and sync signalscan come from an external system source.In addition to the SMA connector, a

reference clock can be accepted throughthe first rear panel µSync output connec-tor, allowing a single Cobalt or Onyxboard to generate the clock for allsubsequent boards in the system.

S nt g st S gn sOutput SignalsOutput SignalsThe 9192 provides four rear panelµSync output connectors, compatiblewith a range of high-speed PentekCobalt and Onyx boards. The µSyncsignals include a reference clock, gate/trigger and sync signals and are distrib-uted through matched cables, simplifyingsystem design.

lo S g slo S g sClock SignalsClock SignalsThe 9192 can accept a user suppliedexternal clock on its rear panel SMAconnector. As an alternative to theexternal clock, the 9192 can use itsonboard VCXO (programmable voltagecontrolled crystal oscillator) as theclock source. The VCXO can operate

51


M de 9 9 : ack-m unt igh-S e Sys m y onize nitModel 9192: Rack-mount High-Speed System Synchronizer UnitM e 9 9 : k h e S s m y n ze d ac -m unt ig -S y o i nitModel 9192: Rack-mount High-Speed System Synchronizer Unit

alone or be locked to a system referenceclock signal delivered to the rear panelreference clock input.

The on-board or external clock canoperate at full rate or can be dividedand used to register all sync and gate/trigger signals as well as providing areference clock to all connected boards.In addition, the clock is available attwelve Clock Out SMAs as a sample orreference clock for other boards in thesystem.

t y n n a c r t n SGate and Synchronization SignalsThe 9192 features separate inputs forgate/trigger and sync signals. A program-mable delay allows the user to maketiming adjustments on the gate/triggerand sync signals before they are sent tobuffers for output through the µSyncoutput connectors.

a t nCalibrationThe 9192 features twelve calibrationoutputs specifically designed to workwith the 71640 or 71740 3.6 GHz A/Dboard and provide a signal reference forphase adjustment across multiple D/As.

cifi a ioSpecificationsc i a oif iSpecificationsFront Panel Sample Clock/Reference Input

Connector Type: SMAInput Impedance: 50 ohmsInput Level: 0 dBm to +10 dBm,sine waveSample Clock Frequency: 100 MHzto 2 GHzReference Frequency: 5 to 100 MHz

Rear Panel Gate/Trigger & Sync InputsConnector Type: SMAInput Level: LVTTL

Rear Panel µSync Inputs/OutputsQuantity: 12Connector Type: 19-pin µHDMISignal Level: CMLSignals (µSync connector 1): Refer-ence Clock In, TWSI control In,Reference Clock Out, Gate/TriggerOut, Sync OutSignals (µSync connectors 2-12):Reference Clock Out, Gate/TriggerOut, Sync Out

Rear Panel Clock / Calibration OutputsQuantity: 12Connector Type: SMAOutput Impedance: 50 ohmsOutput Level: +6 dBm nominal at1400 MHz, sine waveSample Clock Frequency: 100 MHzto 1.8 GHz

Programmable VCXO:Frequency Ranges: 10-945 MHz,970-1134 MHz, and 1213-1417.5 MHzTuning Resolution: 32 bitsUnlocked Accuracy: +20 ppm

PLL, Divider & Jitter CleanerType: Texas Instruments CDCM7005Frequency Dividers: 1, 2, 3, 4, 6, 8and 16

Power: 120VACEnvironmental

Operating Temp: 0° to 50° CStorage Temp: –20° to 90° CRelative Humidity: 0 to 95%, non-cond.

Size: Standard 1U Rack-mount, 19 in. x1.75 in.

gra inProgrammingr ng aProgrammingThe 9192 allows programming ofoperation parameters including: VCXOfrequency, clock dividers, and delaysthat allow the user to make timingadjustments on the gate and sync signals.These adjustments are made before theyare sent to buffers for output throughthe µSync connectors.

The 9192 is programmed via a rearpanel USB connector or a TWSI controlinterface on the first µSync connector.The control interface is compatible withthe front panel µSync connectors of allhigh-speed Cobalt and Onyx modules,thereby providing a single cableconnection that carries both controland timing signals.

u o e du tSupported Productsu o u te dSupported ProductsThe 9192 supports all high-speed mod-els in the Cobalt family including the71630 1 GHz A/D and D/A XMC, the71640 3.6 GHz A/D XMC and the71670 Four-channel 1.25 GHz, 16-bitD/A XMC. The 9192 will also supporthigh-speed models in the Onyx familyas they become available.

52


od l 8 3 S te Synchr zer and Di rib on oar - IeModel 7893: System Synchronizer and Distribution Board - PCIeod 8 3 e S nchr r and i ib ar - el S t y ze D r on o IModel 7893: System Synchronizer and Distribution Board - PCIe

a rFeatures■ Synchronizes up to eight separate

Cobalt or Onyx boards

■ Up to eight 7893s can be linkedtogether to synchronize up to64 boards

■ Synchronizes sampling, dataacquisition and playback for multi-channel systems


■ Onboard programmable sampleclock generator

■ Output clock rates up to 800 MHz

■ Front panel SMA connectors forTTL input signals and clock outputs

■ Single-slot PCIe format

PLL&

DIVIDER

CLKIN

PROGRAMVCXO

Clock Out 1N

BUFFER&

PROGRAMDELAYS

TTLSync / PPS B In

Timing Bus Out 2through

Timing Bus Out 7

USBINTERFACE

USB

Sample Clk A

Sample Clk BGate / Trig AGate / Trig B

Sync / PPS ASync / PPS B

Timing Bus In

Sample C k ASample Clk BGate / Trig AGate / Trig BSync / PPS A

Sync / PPS B

Timing Bus Out 1

Sample C k ASample Clk BGate / Trig AGate / Trig BSync / PPS A

Sync / PPS B

Timing Bus Out 8

MUX

TTLSync / PPS A In

MUX

MUX

MUX

TTLGate / Trig In

MUX

Sample C k /Reference Clk In

Clock Out 2

Clock Out 3

Clock Out 4

N

: N

N

N

Gate / Trig A

Gate / Trig B

Sync / PPS A

Sync / PPS B

MUX

USB Sync / PPS

USB Gate / Trig

REFCLKIN

CONTROLVOLTAGE

Sample Clk A

Sample Clk B

Sample C k A

Sample C k B

Control

USB Gate / Trig

USB Sync / PPS

Model 7893 System Synchronizer andDistribution Board synchronizes multiplePentek Cobalt and Onyx boards withina system. It enables synchronous sampling,playback and timing for a wide range ofmultichannel high-speed data acquisition,DSP and software radio applications.

Up to eight boards can be synchro-nized using the 7893, each receiving acommon clock up to 800 MHz alongwith timing signals that can be used forsynchronizing, triggering and gatingfunctions.

For larger systems, up to eight 7893’scan be linked together to provide synchro-nization for up to 64 Cobalt or Onyxboards.

p aInput SignalsThe Model 7893 provides four front panelSMA connectors to accept LVTTL inputsignals from external sources: two forSync/PPS and one for Gate/Trigger. Inaddition to the synchronization signals,a front panel SMA connector acceptssample clocks up to 800 MHz or, in analternate mode, accepts a 10 MHzreference clock to lock an onboardVCXO sample clock source.

The 7893 also accepts the 26-pinTiming Bus connector used on Cobaltand Onyx boards. This input allows a

single Cobalt or Onyx board to gener-ate the timing and clock signals for the7893 for distribution of up to eight addi-tional boards. This input can also be usedto link multiple 7893’s for larger systems.

t S gn sOutput Signals S nt g sOutput SignalsThe 7893 provides eight timing busoutput connectors for distributing allneeded timing and clock signals tothe front panels of Cobalt and Onyxboards via ribbon cables. The 7893locks the Gate/Trigger and Sync/PPSsignals to the system’s sample clock.The 7893 also provides four front panelSMA connectors for distributing sampleclocks to other boards in the system.

lo S g sClock Signalslo S g sClock SignalsThe 7893 can accept a clock fromeither the front panel SMA connectoror from the timing bus input connector.In addition, the board is equipped witha programmable onboard VCXO clockgenerator which can free run or belocked to a user supplied, 10 MHz,typical, system reference. In all cases,the sample clock can be divided by 1,2, 4, 8 or 16 prior to distribution to theClock Out SMAs or the timing busoutput connectors.

53


M de 7 9 : ys em S hroni r and ist ibuti B rd - PCModel 7893: System Synchronizer and Distribution Board - PCIeM 7 9 : s m oni t i B d PCde y e S hr r and is ibut r - Model 7893: System Synchronizer and Distribution Board - PCIe e cUSB Interface e c USB Interface

The 7893 is programmed via a USBinterface. In addition to status andcontrol, the USB interface can be usedto generate Gate/Trigger and Sync/PPSsignals for distribution to all connectedboards.

y i a a a e icPhysical Characteristicsi a ay a e icPhysical CharacteristicsThe 7893 is a single-slot PCIe sizeboard which can be mounted in anyPCI or PCIe slot. The board receivespower from a standard six-pin PCIepower connector and uses the PCI orPCIe slot solely for physical mounting,with no electrical connections.

u o e dSupported Productsu o e dSupported ProductsThe 7893 supports a wide range ofproducts in the Cobalt family includingthe 78620 and 78621 three-channel A/D,200 MHz transceivers, the 78650 and78651 two-channel A/D, 500 MHztransceivers, the 78660, 78661 and78662 four-channel 200 MHz A/Ds,and the 78690 L-Band RF Tuner. The7893 also supports the Onyx 78760four-channel 200 MHz A/D and willsupport all complementary models inthe Onyx family as they become available.

p cifica ioSpecificationsp c icif a ioSpecificationsSample Clock/Reference Clock Input

Type: Front panel female SMCconnectorSignal: Sine wave, 0 to +10 dBm,AC-coupled, 50 ohms, accepts 10 to800 MHz sample clock or 4 to180 MHz PLL system reference,typically 10 MHz

TTL Gate/Trigger InputType: Front panel female SMCconnectorSignal: LVTTLFunction: Programmable functionsinclude gate and trigger

TTL Sync/PPS Input AType: Front panel female SMCconnectorSignal: LVTTLFunction: Programmable functionsinclude sync and PPS

TTL Sync/PPS Input BType: Front panel female SMCconnectorSignal: LVTTLFunction: Programmable functionsinclude sync and PPS

Timing Bus InType: One rear 26-pin connectorSignals: LVPECL bus includes:Sample Clock A & B In, Gate/TriggerA & B In, and Sync/PPS A & B In

Clock SynthesizerClock Source: Selectable from on-board programmable VCXO (10 to800 MHz), front panel externalclock or LVPECL timing busSynchronization: VCXO can belocked to an external 4 to 180 MHzPLL system reference (front panelReference Clock Input), typically10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8,or 16 for each of five on-boardclock buses.

Sample Clock OutputType: Four front panel female SMCconnectors, each can be indepen-dently dividedOutput Level: +9 dBm, nominal, sinewave

Timing Bus OutType: Eight rear 26-pin connectorsSignals: LVPECL bus includes:Sample Clock A & B Out, Gate/Trig-ger A & B Out, and Sync/PPS A & BOut

Control: Rear USB input for connectingto motherboard on-board USB 8-pinheader

Power: Rear 8-pin connector compat-ible with PCIe power connectors


Size: Half-length PCIe card, 4.38 in. x7.13 in.

54

Coming Soon!

odel 1 5 : TModel 71750: Tde To l 1 5 : Model 71750: T ansceiv r w th ransceiver with Tn ce h a s iv r w t ransceiver with T A D , DU , Two A/Ds, DUC, T A D U T , D , wo A/Ds, DUC, Two / s - XMCwo D/As - XMC / XMwo s - Cwo D/As - XMC

a rFeaturesa rFeatures■ Complete radar and software radio

interface solution

■ Supports Xilinx Virtex-7 VXT FPGAs







■ PCI Express (Gen. 1, 2, and 3)interface up to x8



de o l 1 4 odel 1 4 Model 71641 Model 71641 . G 3 3. G 3.6 GHz or3.6 GHz or Hz1. G1. GHz1.8 GHz1.8 GHz , , - /2 b A2-b A/12-bit A/D12-bit A/D h D B amf r e wit D s o r with DD s B amfor er with DDCs and Beamformer with DDCs and Beamformer - X C - X C - XMC - XMC

a rFeatures■ Ideal radar and software radio inter-

face solution


■ One-channel mode with 3.6 GHz,12-bit A/D

■ Two-channel mode with 1.8 GHz,12-bit A/Ds


■ Sync bus for multimodulesynchronization

■ PCI Express Gen. 2 interface x8



TIMING BUSGENERATOR


VIRTEX-6 FPGA


32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

3.6 GHz (1 Channel)or

1.8 GHz (2 Channel)12-Bit A/D

12


TTLPPS/Gate/Sync

40

GigabitSerial I/O

(option 105)

4X4X

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

GTXGTX LVDSGTX

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

GigabitSerial I/O(option 105)

GTXGTX LVDSGTX

FPGAGPIO(option 104)

PCIeGen. 3 x8

P14PMC

P16XMC

P15XMC

4X4X

VIRTEX-7 FPGA

VX330T, VX485T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

48 32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

VCXO

TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus


TTLPPS/Gate/Sync

TIMING BUSGENERATOR


D/AClock/Sync

Bus

500 MHz12-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

500 MHz12-BIT A/D

A/DClock/Sync

Bus 800 MHz16-BIT D/A

RFXFORMR

321616

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

55

Customer Information

Placing an OrderPlacing an OrderPlacing an OrderPlacing an OrderPlacing an OrderWhen placing purchase orders for Pentek products, pleaseprovide the model numbers and descriptions used in thiscatalog. You may place your orders by letter, telephone,email or fax; you should confirm a verbal order by mail,email or fax.

All orders should specify a purchase order number, bill-to and ship-to address, method of shipment, and a contactname and telephone number.

U.S. orders should be made out to Pentek, Inc. andmay be placed directly at our office address, or c/o ourauthorized sales representative in your area.

International orders may be placed with us, or with ourauthorized distributor in your country. They have pricing andavailability information and they will be pleased to assist you.

Prices and Price QuotationsPrices and Price QuotationsPrices and Price QuotationsPrices and Price QuotationsPrices and Price QuotationsAll prices are F.O.B. factory in U.S. dollars. Shipping chargesand applicable import, federal, state or local taxes, are paidby the purchaser.

We’re glad to respond to your request for price quotation— just contact the corporate office, or your local represen-tative. Price and delivery quotations are valid for 30 days,unless otherwise stated.

Quantity discounts for large orders are available and willbe included in our price quotation, if applicable.

TTTTTermsermsermsermsermsTerms are Net 30 days for accounts with established credit; untilcredit is established, we require prepayment, or will ship C.O.D.

ShippingShippingShippingShippingShippingFor new orders, we normally ship UPS ground with shippingcharges prepaid and added to our invoice. If you are in ahurry, we will ship UPS Red, UPS Blue, FedEx, or the carrierof your choice, as you request.

Order Cancellation and ReturnsOrder Cancellation and ReturnsOrder Cancellation and ReturnsOrder Cancellation and ReturnsOrder Cancellation and ReturnsAll orders placed with Pentek are considered binding andare subject to cancellation charges. Hardware productsincluded in this catalog may be returned within 30 daysafter receipt, subject to a restocking charge. Before returninga product, please call Customer Service to obtain a ReturnMaterial Authorization (RMA) number. Software purchasesare final and we cannot allow returns.

WWWWWarrantyarrantyarrantyarrantyarrantyPentek warrants its products to conform to published speci-fications and to be free from defects in materials andworkmanship for a period of one year from the date ofdelivery, when used under normal operating conditions andwithin the service conditions for which they were furnished.

The obligation of Pentek arising from a warranty claimshall be limited to repairing or, optionally, replacing withoutcharge any product which proves to be defective within theterm and scope of the warranty.

Pentek must be notified of the defect or nonconformitywithin the warranty period. The affected product must bereturned with shipping charges and insurance prepaid.Pentek will pay shipping charges for the return of product tobuyer, except for products returned from outside of the USA.

Limitations of WLimitations of WLimitations of WLimitations of WLimitations of WarrantyarrantyarrantyarrantyarrantyThis warranty does not apply to products which have beenrepaired or altered by anyone other than Pentek or itsauthorized representatives.

The warranty does not extend to products that have beendamaged by misuse, neglect, improper installation, unautho-rized modification, or extreme environmental conditions.

Pentek specifically disclaims merchantability or fitnessfor a particular purpose. We will not be held liable for inci-dental or consequential damages arising from the sale, use,or installation of any of our products. Under any circum-stances Pentek’s liability under this warranty will not exceedthe purchase price of the product.

Extended WExtended WExtended WExtended WExtended WarrantyarrantyarrantyarrantyarrantyYou may purchase an extended warranty on our hardwareproducts for a fee of 1% of the list price per month of cover-age, or 10% of the list price per year of coverage.

All Pentek software products (excluding 3rd-party prod-ucts) include free maintenance and free upgrades for oneyear. Extended software maintenance is available for one,two, and three years, starting after the first year.

SerSerSerSerService and Repairvice and Repairvice and Repairvice and Repairvice and RepairBefore returning a product for service and repair, pleasecontact Customer Service to obtain a Return MaterialAuthorization (RMA) number and have the following infor-mation available: model number, serial number, name andaddress of person returning the product and a description ofthe problem experienced.

Carefully package the product in its original antistaticmaterial, if it is still available, and ship it to us: prepaid (ifwithin the US) or free domicile DDP (if outside the US).Show the RMA number on the outside of the package andinclude a written description of the malfunction.

When the work is completed, we will return the productto you free of charge, along with a statement of work done, ifunder warranty. Out-of-warranty work will be charged on amaterial and service time basis, and we will be happy toquote you a cost estimate for the repair and return shippingbefore proceeding.

Copyright © 2011, 2012 Pentek, Inc. All rights reserved. Contents of this publication may not be reproduced without written permission. Specifications and pricesare subject to change without notice. Pentek, ReadyFlow, GateFlow, SystemFlow, Cobalt and Onyx are tradenmarks or registered trademarks of Pentek, Inc.

Other trademarks are properties of their respective owners.

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