PRESENTATION

ON

COMPUTER ORGANISATION AND ARCHITECTURE

Submitted by : RAVI RANJAN (CS Deptt)

REGISTER TRANSFER AND LANGUAGEA register transfer is defined as the transfer of information b/w register with the help of common bus

• BUS : Group of wire carrying information from one place to another

• Register : Register is defined as group of flip flop with each flip flop capable of storing 1 byte

Register A Register B Register C Register D

Bus lines

TYPES OF REGISTERS :

1. accumulator (AC)2. Program counter (PC)3. Temporary register (TR)4. Instruction register (IR)5. Data register (DR)6. Address register (AR)7. Input register (INPR)8. Output register (OUTR)

Register symbol No of bits Register name Function register

DR 16 DATA REGISTER Hold memory operand

AR 12 ADRESS REGISTER Hold address memory

AC 16 ACCUMULATOR REGISTER

Processor register

IR 16 INSTRUCTION REGISTER

Hold instruction code

PC 12 PROGRAM REGISTER Hold address

TR 16 TEMPORARY REGISTER

Hold temporary data

INPR 8 INPUT REGISTER Hold input character

OUTR 8 OUTPUT REGISTER Hold output character

Shift register

A register that is capable of shifting data one bit at a time is called a shift register. The logical configuration of a serial shift register consists of a chain of flip-flops connected in cascade, with the output of one flip-flop being connected to the input of its neighbour.

The basic data movements possible within a four-bit shift register

TYPES OF REGISTERS :

1. accumulator (AC)2. Program counter (PC)3. Temporary register (TR)4. Instruction register (IR)5. Data register (DR)6. Address register (AR)7. Input register (INPR)8. Output register (OUTR)

BUS AND MEMORY TRANSFER

The purpose of buses is to reduce the number of "pathways" needed for communication between the components, by carrying out all communications over a single data channel.

The construction of a bus system for four registers :

S1 S0 Register selected 0 0 A 0 1 B 1 0 C 1 1 D

Memory Transfer

When the information is transfer from memory , it is called read and when the information is stored in memory it is called write operation

Memory read : A transfer information into DR from the memory word M selected by the address in AR

Memory Write : A transfer information from R1 into the memory word M selected by the address in AR

NOTE : in both operation the memory word is specified by an address. This memory word is represented by symbol ( M).

COMBINATIONAL CIRCUITS :

Combinational logic is used in computer circuits to do Boolean algebra on input signals and on stored data. Practical computer circuits normally contain a mixture of combinational and sequential logic. For example, the part of an arithmetic logic unit, or ALU, that does mathematical calculations is constructed using combinational logic. Other circuits used in computers, such as

1. half adders 2. full adders3. half subtractors4. full subtractors5. multiplexers6. encoders 7.decoders

ADDERS : an adder or is a digital circuit that performs addition of numbers.

Half adder : The simplest combinational circuit which performs the arithmetic addition of two binary digit is a half adder.

Truth table for Half adderINPUTS OUTPUTS

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Contd :

LOGIC DIAGRAM :

FULL ADDER : A combination that performs addition of 3 bits (2 significant bit) and 1 previous carry is known as full adder.

Truth table for full adder :INPUTS OUTPUTS

A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

S = A’B’C+A’BC’+AB’C’+AB’C’+ABCC = A’BC+AB’C+ABC’+ABC

LOGIC DIAGRAM :

K MAP for full adder :

0 1 0 1

1 0 1 0

ABC

01

00 01 11 10

K map for sum

K map for carry

0 0 1 0

0 1 1 1

ABC 00 01 11 10

01

HALF – SUBTRACTOR : A half subtractor is a combinational circuit that subtracts 2 bits & produce their difference.

Truth table

INPUTS OUTPUTS

MINUENED SUTRAHEND DIFFERENCE BORROW

X Y B DOUT

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

D = X’Y+XY’B = X’Y

FULL SUBTRACTOR : It is a combinational circuit that perform substrac- tion involving 3 bit and the borrow from the previous stage. TRUTH TABLE

INPUTS OUTPUTS

X Y BIN D BOUT

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

S = X’Y’B+X’YB’+XY’B’+XYB

K – MAP for sum :

0 1 0 0

1 1 1 0

BXY

00 01 11 10

01

LOGIC SYMBOL

DECODERS : A decoder is a combinational circuit that performs or that converts binary information for n output lines to max of 2n uni-output lines.

X

Y

A 3*8 decoder has three inputs and eight outputs (Z0 to Z7 )

TRUTH TABLE :

INPUTS OUTPUTSA0 A1 A2 Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

LOGIC DIAGRAM :

ENCODER:

An encoder is a combinational circuit that produce a reverse operation from that of a decoder.

An encoder consist of 2n input lines & output lines which operates the binary code for 2n input variables. Ex of encoder – Octal to binary encoder which consist of 8 input lines, one each for the octal digit & 3 output lines that generate binary number . It is constructed with OR gate.

TRUTH TABLE:

INPUTS OUTPUTS

D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM :

MULTIPLEXER : The term multiplexer means many into one. A digital multiplexer is a combinational circuit that select binary information from one of Many input lines & direct it to a single output lines.

The selection of particular input lines is controlled by a set of selectionLines for n selection lines. There are 2n input lines each of four input i=0 to i=3 applied to one output of AND gate. Selection line S1 & S0 are decoded to select a particular AND gate.

4*1 MUX

INPUT

S0 S1

TRUTH TABLE OF 4*1 MULTIPLEXER :

S1 S0 X

0 0 D0

0 1 D1

1 0 D2

1 1 D3

The other 3 AND gates has a least n input equal to zero . The OR gate output is equal to Value of I2 and providing a path from a select input

LOGIC DIAGRAM :

BUS ARCHITECTURE:

Bus is a group of wires used to carry binary information ,it is collection Of parallel wires of transmitting address data and control signals.

Memory & input output devices connected to CPU through a group ofLines are called bus.

These lines are meant to carry information.

There are three types of buses :1. Address bus ( 16 lines)2. Data bus (8 lines)3. Control bus (5 lines)

ADDRESS BUS :

The address bus is group of 16 lines generally identified as A0 to A15,

the address bus is unidirectional bit flow in one directional. The microprocessor unit uses address bus to identify a peripheral memory location. It is identified by binary numbers. Address bus is used to carry 16 bit address.

CPU

I/ODEVICES

OR MEMORY

16 LINES

8 LINES

5 LINES

Address bus

Data bus

Control bus

Data bus :

It is a group of 8 lines used for data flow. These lines are bi-directionalData flow in both direction between microprocessor & memory & Peripheral devices. The microprocessor uses data bus to tranfer in the binary information.

8085Micro-

processorData bus

memory input output

Control bus :

The control bus carries commands from the cpu & returns status signals from the device.

BUS ARCHITECTURE:

1. ISA - Industry Standard Architecture2. EISA - Extended Industry Standard Architecture3. MCA - Micro Channel Architecture4. Local bus

ISA bus : It stands for INDUSTRY STANDARD ARCHITECTURE . It is a 24 address line & 16 data line bus. It does not take full advantage of 32 bit address bus & 32 bit data bus of a 32 bit microprocessor. This reduces the data transfer rule of the system.

ISA bus is a standard bus architecture that allows 16 bits at a time to flow betweenMotherboard circuit and an expansion slot card & its associated driver.

EISA bus :

It uses 32 bit address bus and 32 bit data bus to fulfill the needs of a 32 bit microprocessor data transfer rate. It is twice of that of ISA. MCA bus :

Micro channel architecture has been developed by IBM. Micro channel Architecture Bus possess the same types of signals and accomplishes the same functions as the EISA, but the 2 are completely incompatible. MCA boards are smaller and use different edge connectors.

BUS ARBITRATION :

1. Serial arbitration2. Parallel arbitration

In a single bus architecture when more than one device requests the bus, a controller called bus arbiter decides who gets the bus, this is called the bus arbitration. Arbitration is mostly done in favor of a master micro processor with the highest priority.

Serial arbitration : serial arbitration is also known as daisy chain arbitration. Serial bus uses the same line to transfer different data bits of same of the same byte. Typically they have one data line and the bits are send one after the other as a packet. The usb and IEEE 1394 bus architecture are examples of serial bus.

Parallel arbitration : Buses that transfer several data bits at the same time are called parallel bus. It is desirable to have wide buses because large chunks of data can be transferred quickly when multiple lines can be used. Parallel buses usually have 8,16,32 and 64 data lines. The ISA,PCI and EISA buses are example of parallel

data bus.

Dynamic arbitration algorithm : This algorithm is followed in three steps:

1. Time slice : In this algorithm the time slice of the bus time is fixed length and allocates sequentially to each processor in round robin manner irrespective of the location of the unit in the system. Each unit is given the same amount of time to communicate it with the system bus and no preference is given to any unit.

2. LRU : (Least recent use) The device that has not used the system bus for longer period has been given highest priority. No processor is given the preference as the priority change dynamically so that each processor can access the system.

3. FIFO: First In First Out queue is established in the same order as the request are received from the processor. Each processor has to wait in the queue for its term to use the system bus on FIFO manner.

Micro operation : The operation of data on registers are called micro operation . The function built into register are example of micro operation .i. Shiftii. Loadiii. Cleariv. Incrementv. Decrement and elementary operation perform all the information stored in one Or more register “R” during 1 cycle.

Computer system micro operation perform 4 types: i. Register transfer micro operationii. Arithmetic micro operationiii. Logic micro operationiv. Shift micro operation