co ban ve msp430.doc

1

I. Tng quan v MSP430:MSP 430 l h vi iu khin cu trc RISC 16-bit c sn xut bi cng ty Texas Instruments. MSP l ch vit tt ca MIXED SIGNAL MICROCONTROLLER. L dng vi iu khin siu tit kim nng lng, s dng ngun thp, khong in p ngun cp t 1.8V 3.6V. MSP 430 kt hp cc c tnh ca mt CPU hin i v tch hp sn cc module ngoi vi. c bit Chp MSP 430 l gii php thch hp cho nhng ng dng yu cu trn tn hiu.

Nhng c tnh ca dng MSP 430 bao gm: in p ngun: 1.8V 3.6 V. Mc tiu th nng lng cc thp: Ch hot ng: 270 A ti 1MHz, 2,2 V. Ch ch: 0.7 A. Ch tt (RAM vn c duy tr): 0.1 A. Thi gian nh thc t ch Standby nh hn 1s.

Cu trc RISC-16 bit, Thi gian mt chu k lnh l 62.5 ns

Cu hnh cc module Clock c bn: Tn s ni ln ti 16 MHz vi 4 hiu chnh tn s +- 1%. Thch anh 32 KHz. Tn s lm vic ln ti 16 MHz. B cng hng. Ngun to xung nhp bn ngoi. in tr bn ngoi. Timer_A 16 bit vi 3 thanh ghi hnh, 3 thanh ghi so snh rng 16 bit Timer_B 16 bit vi 3 thanh ghi hnh, 3 thanh ghi so snh rng 16 bit

Giao din truyn thng ni tip:

H tr truyn thng ni tip nng cao UART, t ng d tm tc Baud. B m ha v gii m IrDA (Infrared Data Associatio). Chun giao tip ng b SPI. Chun giao tip I2C. B chuyn i ADC 10 bit, 200 ksps vi in p tham chiu ni, Ly mu v cht. T ng qut knh, iu khin chuyn i d liu. Hai b khuch i thut ton (hot ng) c th nh cu hnh (i vi MSP 430x22x4). Bo v st p. B np chng trnh. Module m phng trn chip. Cc thnh vin ca dng MSP 430 bao gm:

MSP430F2232: 8KB + 256B Flash Memory 512B RAM. MSP430F2252: 16KB + 256B Flash Memory 512B RAM. MSP430F2272: 32KB + 256B Flash Memory 1KB RAM. MSP430F2234: 8KB + 256B Flash Memory 512B RAM. MSP430F2254: 16KB + 256B Flash Memory 512B RAM. MSP430F2274: 32KB + 256B Flash Memory 1KB RAM.MSP430 c s dng v bit n c bit trong nhng ng dng v thit b o c s dng hoc khng s dng LCD vi ch ngun nui rt thp. Vi ch ngun nui t khong 1,8 n 3,6v v 5 ch bo v ngun.

Vi s tiu th dng rt thp trong ch tch cc th dng tiu th l 200uA, 1Mhz, 2.2v; vi ch standby th dng tiu th l 0.7uA. V ch tt ch duy tr b nh Ram th dng tiu th rt nh 0.1uA.MSP430 c u th v ch ngun nui. Thi gian chuyn ch t ch standby sang ch tch cc rt nh (< 6us). V c tch hp 96 kiu hnh cho hin th LCD. 16 bit thanh ghi, 16 bit RISC CPU.C mt c im ca h nh MSP l khi MCU khng c tn hiu dao ng ngoi, th MSP s t ng chuyn sang hot ng ch dao ng ni.Kiu chn thit k:TAPACKAGED DEVICES

PLASTIC 38-PIN TSSOP

(DA)

PLASTIC40-PINQFN

(RHA)

-- 4 0C to 85CMSP430F2232IDA

MSP430F2252IDA

MSP430F2272IDA

MSP430F2234IDA

MSP430F2254IDA

MSP430F2274IDA

MSP430F2232IRHA

MSP430F2252IRHA

MSP430F2272IRHA

MSP430F2234IRHA

MSP430F2254IRHA

MSP430F2274IRHA

-- 4 0C to 105CMSP430F2232TDAw

MSP430F2252TDAw

MSP430F2272TDAw

MSP430F2234TDA

MSP430F2254TDA

MSP430F2274TDA

MSP430F2232TRHAw

MSP430F2252TRHAw

MSP430F2272TRHAw

MSP430F2234TRHA

MSP430F2254TRHA

MSP430F2274TRHA

Bng 1: Kiu thit k MSP430S chn ca cc loi MSP 430:

Hnh 1: Cc kiu chn ca MSP430.II. MSP430F2274:

S khi ca vi iu khin MSP 430F2274:

Hnh 2: S khi ca MSP 430F2274Cu trc chung ca MSP430:

Hnh 3: Cu trc chung ca MSP430Tm hiu v CPU ca MSP430F2274:CPU c kin trc RISC (Reduced Intruction Set Computer) l mt kin trc vi x l theo hng n gin ha tp lnh. Cc lnh c xy dng c th thc hin vi ch 1 chu k my. Mt khc bus d liu v bus a ch (c rng 16 bt) tch di nhau iu ny gip cho qu trnh c d liu v m lnh c th din ra ng thi do nng cao hiu sut lm vic ca vi x l.CPU gm 16 thanh ghi 16 bit. R0-15 c cc chc nng c bit. Cc thanh ghi cn li c s dng vi mc ch chung. CPU c s khi nh sau:

Hnh 4: kin trc RISC ca CPUCc ch nh a ch:MSP 430 c 7 ch nh a ch: + Ch thanh ghi. + Ch ch s. + Ch nh a ch k hiu. + Ch nh a ch tuyt i. + Ch nh a ch thanh ghi gin tip. + Ch nh a ch tng t ng. + Ch nh a ch tc thi.

Vng a ch:

Vng nh c th nh a ch c dung lng l 128 KB.Hnh 5: S vng nh chng trnh v d liua. B nh chng trnh v d liu Flash/ ROM: a ch bt u ca b nh chng trnh v d liu Flash/ ROM ph thuc vo dung lng hin thi v s thay i ca thit b, a ch kt thc l 0x1FFFF.b. RAM: Vng nh RAM bt u t a ch 0200h, a ch kt thc ph thuc vo dung lng hin thi v s thay i ca thit b. RAM c th s dng cho c hai m v d liu

c. Cc module ngoi vi: Vng a ch t 0100h 01FFh l vng a ch ca cc module ngoi vi 16 bt. Vng a ch t 010h 01Fh c ng k cho cc module ngoi vi 8 bt.

d. Vng a ch ca cc thanh ghi c bit (SFRs): Mt vi thit b ngoi vi c h tr bi cc thanh ghi c chc nng c bit, c nh a ch byte v bao gm 16 byte thp ca vng a ch.T chc b nh: Hnh 6: T chc b nh

Byte c th nm vng a ch chn hoc l. Word ch nm vng a ch chn, khi s dng cu trc word ch c vng a ch chn c s dng. Byte thp ca 1 word lun l vng a ch chn. Byte cao ca word nm a ch l tip theo.

B nh c th c m rng thm ch vt qu s a ch c th nh a ch trc tip, y l mt u im ca b nh c cu trc kiu RISC. B nh c chia thnh cc Bank, ti mt thi im ch c mt Bank c truy xut.Chc nng cc chn:

Bng 2: Bng chc nng cc chn.

Chn P1.0/TACLK/ADC10CLK (29):

Chn xut / nhp s.

Ng vo xung clock TACLK ca Timer A.

B chuyn i xung ca ADC10

Chn P1.1/TA0 (30):

Chn xut / nhp s.

Timer_A: Ng vo CCI0A ch capture, ng ra OUT0 ch so snh.

Chn P1.1/TA0 (31):

Chn xut / nhp s.


Chn P1.3/TA0 (32):

Chn xut / nhp s.


Chn P1.4/SMCLK/TCK (33):

Chn xut / nhp s.

Ng ra SMCLK (Sub-Main clock) ca khi to dao ng ni.

Ng vo kim tra xung clock TCK .

Chn P1.5/TA0/TMS (34):

Chn xut / nhp s

Ng ra OUT0 caTimer_A ch so snh.

TSM: Ng vo la chn ch kim tra.

Chn P1.6/TA1/TDI/TCLK (35):

Chn xut / nhp s

TA1: ng ra OUT1ca Timer A ch so snh.

TDI: Ng vo kim tra d liu.

TCLK: Ng vo kim tra xung clock.

Chn P1.7/TA2/TDO/TDI (36):

Chn xut / nhp s

TA2: ng ra OUT2 ca Timer A ch so snh:.


TDO: Ng ra kim tra d liu.

Chn P2.0/ACLK/OA0I0 (6):

Chn xut / nhp s.

Ng ra xung clock ACLK.

Ng vo tng t A0 ca knh ADC10.

Chn P2.1/TAINCLK/SMCLK/A1/OA0O (7):

Chn xut / nhp s.

Timer_A.

Knh ADC10: Ng vo knh tng t A1, ng ra knh tng t OA0.

Xung clock INCLK ca Timer_A

Xung clock ch SMCLK


Chn xut / nhp s.

Ng vo tng t A1 knh ADC10

Ng vo CCI0B ca Timer_A ch capture.

Ng ra OUT0 ca knh ADC10 ch so snh.

Ng vo tng t A2

Chn P2.3/TA1/A3/VREF-/VeREF-/OA1I1/OA1O (27):

Chn xut / nhp s.

Ng vo CCI1 ca Timer_A.

Ng ra OUT1 knh ADC10 ch so snh

Ng vo tng t A3 ca knh ADC10.

in p tham chiu m VREF-/ VeREF- Chn P2.4/TA2/A4/VREF+/VeREF+/OA1I0 (28):

Chn xut / nhp s.

Ng vo tng t A4 ca knh ADC10

Ng ra OUT2 ca Timer_A ch so snh.

in p tham chiu dng VREF+/ VeREF+ Chn P2.5/ROSC (40):

Chn xut / nhp s.

Ng vo in tr ngoi nh ngha tn s DCO.

Chn XIN/ P2.6 (3):

Ng vo kt ni vi dao ng thch anh.

Chn xut/ nhp s.

Chn XUOT/P2.7 (2):

Ng vo kt ni vi dao ng thch anh.

Chn xut/nhp s.

Chn P3.0/UCB0STE/UC0CLK/A5 (9):

Chn xut / nhp s.

Chn cho php truyn d liu USCI_B0 khi hot ng ch t.

Ng vo tng t A5 ca knh ADC10

Chn P3.1/UCB0SIMO/UCB0SDA (10):

Chn xut / nhp s.

Ng vo USCI_B0 khi hot ng ch slave, ng ra khi hot ng ch master trong ch SPI.

Chn d liu SDA I2C trong ch I2C.

Chn P3.2/UCB01SOMI/UCB0SCL (11):

Chn xut / nhp s.

Ng ra USCI_B0 khi hot ng ch t, ng vo khi hot ng ch ch trong ch SPI.

Xung clock SCL I2C trong ch I2C.

Chn P3.3/UCB0CLK/UCA0STE (12):

Chn xut / nhp s.

Xung clock USCI_B0

Cho php truyn d liu USCI_A0 trong ch t.

Chn P3.4/UCA0TXD/UCA0SIMO (23):

Chn xut / nhp s.

Chn truyn d liu ni tip USCI_A0 trong ch UART.

Ng vo ch t, ng ra ch ch trong ch SPI.

Chn P3.5 UCA0RXD/UCA0SOMI (24):

Chn xut / nhp s.

Ng vo nhn d liu USCI_A0 trong ch UART.

Ng ra ch t/ ng vo ch ch trong ch SPI.

Chn P3.6 / A6/OA0I2 (25):

Chn xut / nhp s.

Ng vo tng t A6 ca knh chuyn i ADC10.

Ng vo tng t OA0I2 ca knh OA0.

Chn P3.7 / A7/OA1I2 (26):

Chn xut / nhp s.


Ng vo tng t OA1I2 ca knh OA1.

Chn P4.0/TB0 (15):

Chn xut / nhp s.

Ng vo CCI0A ca Timer_B ch capture, ng ra OUT0 ch so snh.

Chn P4.1/TB1 (16):

Chn xut / nhp s.

Ng vo CCI1A ca Timer_B ch capture. Ng ra OUT1 ch so snh.

Chn P4.2/TB2 (17):

Chn xut / nhp s.

Ng vo CCI2A ca Timer_B ch capture. Ng ra OUT2 ch so snh.

Chn P4.3/TB0/A12/OA0O (18):

Chn xut / nhp s.

Ng vo CCI0B ca Timer_B ch capture. Ng ra OUT0 ch so snh.


Chn P4.4/TB1/A13/OA1O (19):

Chn xut / nhp s.

Timer_B: Ng vo CCI1B ch capture. Ng ra OUT1 ch so snh.


Chn P4.5/TB2/A14/OA0I3 (20):

Chn xut / nhp s.

Timer_B: Ng ra OUT0 ch so snh.


Chn P4.6/TBOUTH/A15/OA1I3 (21):

Chn xut / nhp s.

Timer_B.


Chn P4.7/TBCLK (22):

Chn xut / nhp s.

Ng vo nhn xung TBCLK ca timer_B.

Chn RST/NMI/SBWTDIO (5):

Chn Reset tc ng mc thp hoc cm ngt.

Chn TEST/SBWTCK (37):

Chn DVCC (38,39), AVCC (14): Chn cp ngun VCC Chn DVSS (1,4), AVSS (13): Chn cp mass

Chn P1.0/TACLK/ADC10/CLK (29):

Chn xut / nhp s. TACLK: Ng vo nhn xung clock cho Timer A. ADC10: Ng vo tng t A10. CLK: Ng vo b chuyn i xung clock t ngun xung ngoi.

Chn P1.1/TA0 (30): Chn xut / nhp s. Timer_A, lu tr: Ng vo CCI0A, so snh: Ng ra OUT0.

Chn P1.1/TA0 (31): Chn xut / nhp s. Timer_A, lu tr: Ng vo CCI1A, so snh: Ng ra OUT1.

Chn P1.3/TA0 (32): Chn xut / nhp s. Timer_A, lu tr: Ng vo CCI2A, so snh: Ng ra OUT2. Chn P1.4/SMCLK/TCK (33):

Chn xut / nhp s. SMCLK (Sub-Main clock): Ng ra ca khi to dao ng ni, cung cp cho cc module ngoi vi. TCK: Ng vo kim tra xung clock cho vic lp trnh.

Chn P1.5/TA0/TMS (34):

Chn xut / nhp s

TA0: Timer_A ch so snh, ng ra OUT0.

TSM: Ng vo la chn ch kin tra. Chn P1.6/TA1/TDI/TCLK (35):

Chn xut / nhp s

TA1: Timer A,ch so snh: ng ra OUT1.


TCLK: Ng vo kim tra xung clock.

Chn P1.7/TA2/TDO/TDI (36):

Chn xut / nhp s

TA2: Timer A,ch so snh: ng ra OUT2.


TDO: Ng ra kim tra xung clock.

Chn P2.0/ACLK/OA0I0 (6):

Chn xut / nhp s. Ng ra h thng xung clock ACLK, ADC10. Ng vo knh tng t A0/OA0. Ng vo knh tng t I0.


Chn xut / nhp s. Timer_A. Knh ADC10: Ng vo knh tng t A1, ng ra knh tng t OA0. Chn P2.2/TAINCLK/SMCLK/A1/OA0O (8):

Chn xut / nhp s. Timer_A. Lu tr ng vo CCI0B, nhn BLS. Ng ra OUT0 ca knh ADC10 ch so snh. Ng vo knh tng t A2/OA0. Ng vo knh tng t I1. Chn P2.3/TA1/A3/VREF-/VeREF-/OA1I1/OA1O (27):

Chn xut / nhp s. Timer_A. Ng vo CCI1 ch lu tr. Ch so snh: ng ra OUT1 knh ADC10. Ng vo knh tng t A3. Ng vo in p tham chiu m. Chn P2.4/TA2/A4/VREF+/VeREF+/OA1I0 (28):

Chn xut / nhp s. in p tham chiu dng . Chn P2.5/ROSC (40):

Chn xut / nhp s. Ng vo in tr ngoi nh ngha tn s DCO. Chn XIN/ P2.6 (3):

Ng vo kt ni vi dao ng thch anh. Chn xut/ nhp s. Chn XUOT/P2.7 (2):

Ng vo kt ni vi dao ng thch anh. Chn xut/nhp s. Chn P3.0/UCB0STE/UC0CLK/A5 (9):

Chn xut / nhp s. Chn cho php truyn d liu khi ch USCI_B0. Ng vo nhn xung ca USCI_A0. Ng ra knh ADC10. Ng vo knh tng t A5. Chn P3.1/UCB0SIMO/UCB0SDA (10):

Chn xut / nhp s. Ng vo ch t USCI_B0. Ng vo ch ch trong ch SPI. D liu SDA I2C trong ch I2C. Chn P3.2/UCB01SOMI/UCB0SCL (11):

Chn xut / nhp s. Ng ra ch t USCI_B0. Ng vo ch ch trong ch SPI. Xung clock SCL I2C trong ch I2C. Chn P3.3/UCB0CLK/UCA0STE (12):

Chn xut / nhp s. Cho php truyn d liu trong ch t USCI_A0. Chn P3.4/UCA0TXD/UCA0SIMO (23):

Chn xut / nhp s. Chn truyn d liu ni tip USCI_A0 trong ch UART. Ng vo ch t, ng ra ch ch trong ch SPI. Chn P3.5 UCA0RXD/UCA0SOMI (24):

Chn xut / nhp s. Ng vo nhn d liu USCI_A0 trong ch UART. Ng ra ch t/ ng vo ch ch trong ch SPI. Chn P3.6 / A6/OA0I2 (25):

Chn xut / nhp s. Ng vo tng t A6 ca knh chuyn i ADC10. Ng vo tng t I2 ca knh OA0. Chn P3.7 / A7/OA1I2 (26):

Chn xut / nhp s. Ng vo tng t A7 ca knh chuyn i ADC10. Ng vo tng t I2 ca knh OA1. Chn P4.0/TB0 (15):

Chn xut / nhp s. Timer_B, ch lu tr: Ng vo CCI0A, ch so snh: Ng ra OUT0.

Chn P4.1/TB1 (16):

Chn xut / nhp s. Timer_B, ch lu tr: Ng vo CCI1A, ch so snh: Ng ra OUT1. Chn P4.2/TB2 (17):

Chn xut / nhp s. Timer_B, ch lu tr: Ng vo CCI2A, ch so snh: Ng ra OUT2. Chn P4.3/TB0/A12/OA0O (18):

Chn xut / nhp s. Timer_B, ch lu tr: Ng vo CCI0B, ch so snh: Ng ra OUT0. Ng vo tng t A12 ca knh chuyn i ADC10, ng ra tng t OA0.

Chn P4.4/TB1/A13/OA1O (19):

Chn xut / nhp s. Timer_B, ch lu tr: Ng vo CCI1B, ch so snh: Ng ra OUT1. Ng vo tng t A13 ca knh chuyn i ADC10, ng ra tng t OA1.

Chn P4.5/TB2/A14/OA0I3 (20):

Chn xut / nhp s. Timer_B, ch so snh: Ng ra OUT0.

Ng vo tng t A14 ca knh chuyn i ADC10, ng vo tng t I3 caOA0.

Chn P4.6/TBOUTH/A15/OA1I3 (21):

Chn xut / nhp s. Timer_B. Ng vo tng t A15 ca knh chuyn i ADC10, ng vo tng t OA0.

Chn P4.7/TBCLK (22):

Chn xut / nhp s. Ng vo nhn xung TBCLK ca timer_B. Chn RST/NMI/SBWTDIO (5):

Chn Reset tc ng mc thp hoc cm ngt. Chn TEST/SBWTCK (37):

Chn DVCC (38,39), AVCC (14): Chn cp ngun VCC Chn DVSS (1,4), AVSS (13): Chn cp massCu trc cc thanh ghi:Bn thanh ghi u tin t R0 R3 c ch nh lm thanh ghi b m chng trnh, con tr ngn xp, thanh ghi trng thi, constant Generator. Cc thanh ghi cn li l nhng thanh ghi s dng mc ch chung.Cc thit b ngoi vi c kt ni ti CPU s dng d liu, a ch, bus iu khin.

Hnh 8: Cu trc thanh ghi

Cc thanh ghi c chc nng c bit:Tt c cc ngt v module cho php truy xut BIT u c tp trung vng a ch thp nht. Cc bt ca cc thanh ghi chc nng c bit khng c cho php ti mt mc ch chc nng vt l ca thit b. Phn mm n gin c cung cp vi sp xp ny.

Thanh ghi cho php ngt 1 v 2:Trong :- WDTIE Cho php ngt Whatchdog Timer: Khng hot ng:\ nu ch whatchdog c la chn. Hot ng nu ch timer c la chn.

- OFIE : Cho php dng b pht xung.- NMIIE : Cm khng cho php ngt c.Cu trc xut nhp:Chp MSP 430F2274 c th ln ti 8 port xut nhp t P1 P7. Mi port c 8 chn. Mi chn u c nhng chc nng c bit c th nh hng lm u vo hoc u ra, c th c truy sut hoc iu khin.

Ports P1 v P2 c kh nng ngt. Mi ngt c cu hnh ring theo cnh ln hoc cnh xung ca sn xung hoc theo tn hiu vo tng ng vi cc vector ngt.

c tnh xut nhp bao gm:

+ Chc nng c bit ca cc chn khng ph thuc vo vic lp trnh.

+ C th la chn lm OUTPUT hoc INPUT.

+ P1 v P2 c cu hnh ring cho tn hiu ngt.

+ Khng ph thuc thanh ghi output hay input.

+ Cu hnh c in tr ko.Hot ng xut nhp:Hot ng xut nhp d liu c lp trnh bng phn mm.Thanh ghi Input PxIN: Khi c la chn lm u vo. Gi tr mi bt ca thanh ghi tng ng vi tn hiu.Bit = 0 u vo mc thp.Bit = 1 tn hiu mc cao.Thanh ghi u ra PxOUT:Khi khng s dng in tr ko, v c nh hng lm u gia. Gi tr cc bt ca thanh ghi tng ng:

Bit =0 u ra mc thp.

Bit = 1 u ra mc cao.Nu cho php in tr ko, gi tr ca bt tng ng vi in tr c la chn:

Bit = 0 khi in tr ko xung.

Bt = 1 khi in tr ko ln.Thanh ghi nh hng PxDIR:Cc chn ca mi port c nh hng lm u ra hoc u vo phc thuc vo gi tr cc bt ca thanh ghi PxDIR:Nu bit = 0 chn c nh hng lm u vo.Nu bit = 1 chn c nh hng lm u ra.Thanh ghi cho php in tr ko:Mi bt ca thanh ghi PxREN cho php hoc khng cho php in tr ko:Bit = 1 in tr ko ln. Bit = 0 in tr ko xuNg.

Thanh ghi la chn chc nng PxSEL v PxSEL2:Cc chn ca mi port u c nhiu chc nng tng ng vi cc module ngoi vi khc nhau. Mi bt ca thanh ghi PxSEL v PxSEL2 c s dng la chn chc nng l cc port xut nhp hoc chc nng c bit. PxSEL2PXSELChc nng ca chn

00Chc nng xut nhp

01Module u tin c la chn

10ng k trc

11Module ngoi vi th 2 c la chn

Ch : Khi PxSEL =1 cc ngt ca P1, P2 b cm. Khi bt k bit no ca thanh ghi P1SELx hoc P2SELx c set, cc ngt tng ng vi cc chn ny s b cm.Cc ngt P1 v P2:Mi chn ca port P1 v P2 u c kh nng ngt. Cc ngt c cu hnh bi cc thanh ghi PxIFG, PxIE V PxIES. Tt c cc chn ca port P1 mt nguyn nhn tng ng vi mt vector ngt. Tt c cc chn ca port 2 c nhiu hn mt nguyn nhn khc nhau tng ng vi 1 vector. C th s dng thanh ghi PxIFG xc nh nguyn nhn cc ngt port P1 v P2.a) Thanh ghi c ngt P1IFG v P2IFG:

- Mi bit ca thanh ghi PxIFGx l mt c ngt tng ng vi chn xut/ nhp v khi c cnh xung tn hiu ti cc chn. Tt c cc c ngt ca thanh ghi PxIFGx i hi mt ngt tng ng vi cc bit PxIE v GIE c set. Mi c ngt i hi phi reset bng phn mm. Phn mm cng c th set c ngt:

+ Bit =0 Khng c ngt no ang ch.

+ Bit =1 C 1 ngt ang ch c phc v.Ch : Khi thay i thanh ghi PxOUT v PxDIP c ngha l bn ang set c ngt tng ng.

b) Thanh ghi la chn ngt theo sn xung P1IES, P2IES: - Mi bit ca thanh ghi PxIES la chn ngt theo cnh ln hay cnh xung tng ng vi mi chn xut/ nhp:

+ Bit = 0 C ngt c set khi c cnh ln ca xung.

+ Bit = 1 C ngt c set khi c cnh xung ca xung.c) Thanh ghi cho php ngt P1IE v P2IE:- Mi bt PxIE cho php hay cm ngt v lin quan n c ngt tng ng:

+ Bit = 0: Cm ngt.

+ Bit = 1: Cho php ngt.

a ch cc thanh ghi xut/nhp s:MSP 430 c cu hnh lm vic vi BYTE, iu ny s gy kh khn cho ngi lp quen lm vic vi BIT. c th lm vic vi BIT ta phi nh ngha li a ch ca thanh ghi iu khin PORT.

Bng 3: a ch thanh ghi xut nhpB nh thi:

MSP 340 c hai b nh thi 16 Bit l Timer_A v Timer_B n cng ng thi ng vai tr l b m.

Timer_A:c tnh ca Timer_A:L mt b Timer/Counter 16 bit. Vi ba thanh ghi lu tr v 3 thanh ghi so snh. L mt Timer a chc nng. m thi gian, so snh, PWM . Timer_A cng c kh nng ngt khi counter m trn hoc mi thanh ghi m trn. Cc c tnh chnh ca Timer_A bao gm:+ L mt Timer/counter 16 Bit khng ng b vi 4 ch hot ng.

+ C th la chn v cu hnh ngun xung

+ Hai ti 3 thanh ghi c th cu hnh capture/compare

+ Cu hnh u ra vi ch PWM

+ Cht ng vo v ng ra khng ng b

Hnh 9: S khi ca Timer_A

Timer hot ng ch Counter 16 Bit: ch Counter gi tr thanh ghi TAR tng hoc gim theo cnh ln ca xung clock (ty thuc vo ch hot ng). Gi tr ca thanh ghi TAR c th c ghi hoc c bi phn mm. N c kh nng to ra mt ngt khi m trn.Thanh ghi TAR c th b xa khi set bit TACLR. Vic set bit TACLR ng thi cng xa gi tr la chn cho b chia xung hoc ch m ln hay m xung.

La chn ngun xung v b chia xung:Timer c th la chn ngun t xung t ACLK, SMCLK hoc s dng ngun xung ngoi thng qua TACLK hoc INCLK. Ngun xung c la chn nh bt TASSELx. Cc ngun xung c chn c th c chia 2, 4 hoc 8. B chia xung c reset khi set bit TACLR.

Kch hot Timer:Timer c th c kch hot hoc kch hot li bng cc cch sau y:

+ Timer m khi MCx > 0 v ngun xung c kch hot.+ Khi timer ang hot ng ch m ln hoc m xung. C th dng timer bng cch ghi TACCR0 = 0. Timer s kch hot tr li khi gi tr ghi vo TACCR0 khc 0. Gi tr m ln s bt u t 0.Cc ch hot ng ca Timer:Timer hot ng 4 ch : Ch dng, ch m ln, ch tip tc, ch m ln/xung. Cc ch ny c la chn bng bit MCx.MCxModeHot ng

00StopTimer c tm dng

01UpTimer m t 0 ti gi tr nh ca TACCR0

10ContinuousTimer m t 0 ti 0FFFFh

11Up/downTimer m t 0 n gi tr nh ca TACCR0 ri m v 0

Cc ngt ca Timer_A:

C hai ngt c to ra do Timer_A:+ Vector ngt TACCR0 cho TRCCR0 CCIFG.+ Vector ngt TAIV cho tt c cc c ngt CCIFG khc v TAIFG. Trong ch lu tr CCIFG c set khi gi tr ca timer c lu tr do thanh ghi TACCRx. Trong ch so snh bt k c CCIFG c set nu TAR m ti gi tr TACCRx. C th s dng phn mm set hoc xa bt k c ngt CCIFG no. Tt c cc c ngt CCIFG yu cu mt ngt khi bit CCIE v GIE c set.Ngt TACCR0 CCIFG l ngt ca Timer_A c mc u tin cao nht. C ngt TACCR0 CCIFG t ng reset khi ngt TACCR0 c phc v.

Hnh 10: C ngt ch trong ch so snh v lu trThanh ghi iu khin Timer_A:

Bng 4: Bng lit k cc thanh ghi iu khin Timer_AThanh ghi iu khin TACTL:

+ Bit 15-10: Khng s dng.+ TASSELx Bit 9-8: La chn ngun xung clock:

00TACLK

01ACLK

10SMCLK

11INCLK

+ Idx Bit 7-6: La chn b chia trc:

00/1

01/2

10/4

11/8

+ MCx Bit 5-4: La chn ch hot ng:00 Dng ch 01 Ch ln010 Tip tc ch 011 Ch ln/xung+ TACLR Bit 2: Xa Timer_A. Khi bit ny c set, gi tr m, gi tr b chia trc u c reset.+ TAIE Bit 1: Cho php ngt. Khi bit =1 cho php ngt, bit = 0 cm ngt.

+ TAIFG Bit 0: C ngt ca Timer_A:

Bit = 0 Khng c ngt no ang ch

Bit = 1 C ngt ang ch phc v

Cc thanh ghi cn li cc bn c th tham kho trong datasheet.Timer_B:Timer_B l b nh thi 16 bt c th hot ng 2 ch Timer v counter. Timer_B p ng a chc nng capture/ so snh, PWM. Timer_B cng c kh nng to ra ngt khi n m trn, hoc cc thanh ghi capture/ so snh.Cc c tnh ca Timer_B:+ L mt Timer/counter 16 Bit khng ng b vi 4 ch hot ng.

+ C th la chn v cu hnh ngun xung.+ C t 3 ti 7 thanh ghi c th cu hnh capture/compare.+ Cu hnh u ra vi ch PWM.+ Cht ng vo v ng ra khng ng b.

Hnh 11: S khi ca Timer_B

Nhng im ging v khc nhau giu Timer_A v Timer_B:Timer_B mang y c im ca Timer_A ngoi ra Timer_B c cc c tnh c bit sau:+ Kch thc ca Timer c th lp trnh c c di 8, 10, 12 hoc 16 Bit.

+ Thanh ghi TBCCRx l 2 b m c th c nhm li.

+ Tt c cc u ra ca Timer_B u c th t trng thi tng tr cao.

+ Chc nng ca bit SCCI khng c thc hin trong Timer_B.Hot ng ca Timer_B:Timer hot ng ch Counter: Khi hot ng ch m gi tr thanh ghi TBR tng hoc gim (ty thuc vo ch hot ng) theo cnh ln ca xung clock. Thanh ghi TBR c th ghi hoc c. Timer_B c th to ra ngt khi m trn.Thanh ghi TBR cng c th c xa bng cch set bit TBCLR. Khi bt ny c set ng thi cng reset li gi tr ca b chia v gi tr m.

Ch : Bn nn dng hot ng ca Timer trc khi mun chnh sa. Nhng thay i ghi vo TRB s c thc thi ngay lp tc v vy nu thay i gi tr khi timer ang hot ng c th hot ng ca n khng cn chnh xc. C th c gi tr ca Timer khi n ang hot ng. di thanh ghi TBR:Xung cp cho Timer c th ly t ngun xung ACLK hoc SMCLK hoc t ngun xung ngoi TBCLK. Ngun xung c la chn nh bit TBSSELx, ngun xung c la chn c th c chi trc 2, 4, hoc 8. Gi tr ca b chia b reset khi set bit TBCLR.

2.1.4.2.4 Kch hot timer:Timer c th c khi ng hoc khi ng li bng cc cch sau:

+ Timer m khi MCx >0 v ngun xung clock hot ng.

+ Khi timer hot ng mt trong hai ch up, up/down. C th dng hot ng ca timer bng cch t TBCL0=0. Timer c kch hot tr li khi gi tr ny khc 0. Khi kch hot tr li gi tr ca timer bt u t 0.

Cc ch hot ng ca Timer:Timer_B hot ng 4 ch , cc ch c la chn nh bit MCx.

MCxModeHot ng

00StopTm dng Timer

01UpTimer m t 0 ti gi tr nh ca TBCL0

10ContinuousTimer m t 0 ti gi tr c la chn bi bt CNTLx

11Up/downTimer m t 0 n gi tr nh ca TBCL0 ri m xung v 0

Cc ngt ca Timer_B:Timer_B c th to ra 2 ngt:+ Vector ngt TBCCR0 cho TBCCR0 CCIFG.+ Vector ngt TBIV cho cc c ngt CCIFG v TBIFG.

Vector ngt TBCCR0:Vector ngt TBCCR0 l ngt c mc u tin cao nht do Timer_B to ra. C ngt TBCCR0 CCIFG t ng reset khi ngt TBCCR0 c phc v.

Hnh 12: C ngt TBCCR0

Cc thanh ghi ca Timer_B:

Bng 5: Thanh ghi ca Timer_B

Thanh ghi iu khin TBCTL:+ Bit 15: khng s dng + CNTLx Bit 12-11: di ca b m:00 16-bit,TBR(max) = 0FFFFh

01 12-bit,TBR(max) = 0FFFh

1010-bit,TBR(max) = 03FFh

118-bit,TBR(max) = 0FFh

+ TBSSELx bit 9-8: La chn ngun xung clock:00TBCLK

01ACLK

10SMCLK

11o TBCLK+ IDx Bit 7-6: la chn b chia xung:

00/1

01/2

10/4

11/8

+ MCx Bit 5-4: La chn ch iu khin:00 Dng ch

01Ch ln

10Tip tc ch

11Ch ln/xung

+ TBCLR : Xa Timer_B Khi bit ny c set, gi tr b m, b chia xung u c xa v 0.

+ TBIE Bit 1: Cho php ngt Timer_B. Bit =1 cho php ngt, bit = 0 cm ngt.

+ TBIFG Bit 0: C ngt. Bit = 0 khng c ngt no ch, bit = 1 c ngt ang ch phc v. Khi ngt c phc v Bit t ng c xa v 0.

B khuch i thut ton OA:

MSP 430 c 2 b khuch i thut ton vi nhiu knh khc nhau.c tnh ca cc b khuch i thut ton:

+ Ngun n, hot ng ch dng thp.+ C th la chn cu hnh bng phn mm.+ Phn mm c th la chn in tr bc thang phn hi cho PGA

Hnh 13: S khi ca OACc knh chuyn i ADC:MSP 430 c 2 knh chuyn i ADC 10 bit, ADC10 v ADC12.Knh chuyn i ADC10:Cc c tnh ca knh chuyn i ADC10:+ Tc chuyn i ln nht ln hn 200ksps.

+ B chuyn i 10 bit n khng b li m.+ Ly mu v cht vi thi gian ly mu c lp trnh.

+ Qu trnh chuyn i c khi to bng phn mm hoc Timer_A.+ C th s dng phn mm la chn in p tham chiu (1.5V hoc 2.5V).+ C th la chn in p tham chiu ni hoc in p tham chiu ngoi.+ C 8 knh u vo tng t, ring vi MSP 340x22xx c ti 12 knh u vo tng t.+ Cc knh chuyn i cho cm bin nhit bn trong, Vcc, v in p tham chiu ngoi.+ La chn ngun xung clock.

+ T ng iu khin qu trnh huyn i d liu v lu kt qu chuyn i .

Hnh 14: S khi ca ADC10

Hot ng ca b chuyn i ADC10:Knh ADC10 chuyn i mt tn hiu tng t sang tn hiu s c di 10 bit, kt qu chuyn i c lu vo thanh ghi ADC10MEM. S dng in p tham chiu VR+ v VR- xc nh gii hn trn v gii hn di ca b chuyn i. Kt qu chuyn i s c gi tr NADC = 03FFh khi Vinput > = VR+ (khi y) hoc NADC = 0 khi Vinput< = VR-. Kt qu chuyn i c tnh bng cng thc nh sau:

B chuyn i ADC10 c iu khin bi 2 thanh ghi ADC10CTL0 v ADC10CTL1. ADC10ON l bit cho php chuyn i. Khi bn mun thay i cc gi tr iu khin chuyn i bn phi t ENC = 0. Khi iu chnh xong lu set bit ENC = 1 qu trnh chuyn i bt u.La chn ngun xung clock ADC10CLK:

la chn ngun xung iu khin ta s dng bit ADC10SSELx. C th s dng b chia trc bng bit ADC10DIVx. ADC10CLK c th ly xung t cc ngun SMCLK, MCLK, ACLK hoc s dng bi xung ni ADC10OSC phc v ring cho n.Tn s chuyn i c th ln ti 5-MHz, nhung gi tr ny cng ty thuc vo ngun cp, nhit v thay i do lp trnh. Phi lun cp xung clock trong qu trnh chuyn i, nu ngt ngun xung b chuyn i khng hot ng hoc kt qu chuyn i khng chnh xc.

Hnh 15: B a hp ng vo ADC10

Knh chuyn i ADC10 c tt c 12 ng vo tng t, 8 ng vo tng t ngoi v 4 ng vo ni, cc ng vo c la chn chuyn i bng b a hp.La chn knh tng t:Cc ng vo tng t Ax, VeREF+, and VREF + ng thi cng l cc chn xut/nhp. Cc chn ny l dng cng CMOS, khi c la chn lm ng vo chuyn i c th to ra dng in k sinh c gi tr rt nh t Vcc v GND. C th cm khuch i dng k sinh ny bng cch s dng bit ADC10Aex.in p tham chiu:Ta c th la chn in p tham chiu ni bng cch set bit REFON = 1, khi REFON = 0 la chn in p tham chiu ngoi VRFE+. Bit RFE2_5V la chn gi tr in p tham chiu ni. Khi REF2_5V = 1in p tham chiu ni l 2.5 V. Khi REF2_5V = 0 in p tham chiu ni l 1.5 V.c tnh cng sut thp ca in p tham chiu ni:Mi thit k ca MSP 430 u hng ti tiu ch tit kim nng lng. Knh ADC10 t chuyn sang ch tit kim nng lng khi in p tng t ng vo khng i, n kch hot tr li khi cn thit. Khi khng c ngun xung clock dng chuyn i bng 0.Thi gian ly mu v chuyn i:Bit SHTx c s dng la chn thi gian ly mu, thi gian ly mu c th l 4, 8, 16 hoc 64 chu k xung, thi gian chuyn i l 13 chu k xung.

Hnh 16: Thi gian ly mu

Tnh ton thi gian ly mu:Khi SAMPCON = 0 tt c cc ng vo tng t Ax u trng thi tng tr cao. Khi SAMPCON = 1 tn hiu tng t ng vo c a qua mt mch lc thng thp RC. S tng ng nh sau:

Ni tr ca ngun Rs v Ri nh hng n thi gian ly mu. Thi gian ly mu ti thiu c th c tnh theo phng trnh sau y:

Vi gi tr ln nht Ri =2 k, Ci = 27 pF phng trnh trn tng ng vi:Nu Rs = 10k th thi gian ly mu ln hn 2.47 s.

Khi s dng b m tham chiu trong ch burst th thi gian ly mu phi ln hn thi gian tnh ton trn v thi gian thit lp ca b m.

V d, nu in p tham chiu ngoi VRef =1.5V, RS = 10 k, tsample ln hn than 2.47s, khi ADC10SR = 0, hoc 2.5 s khi ADC10SR = 1. Khi thi gian thit lp ca b m c tnh ton nh sau:

Trong SR: l tc qut ca b m.

Ch chuyn i:B chuyn i tng t sang s ADC10 c 4 ch hot ng c la chn bng bt CONSEQx.

Ngt ca ADC10: Mt ngt c to ra do knh ADC10, ADC10IFG c set khi bt u qu trnh chun i, kt qu chuyn i c lu vo ADC10MEM. Khi qua trnh chuyn i hon thnh c ngt ADC10IFG s to ra mt ngt, c ngt t ng reset khi ngt c phc v.

Hnh 17: Ngt ADC10Cc thanh ghi ca ADC10:

Bng 6: Thanh ghi ADC10

a) Thanh ghi iu khin ADC10CTL0: L thanh ghi 16 bit c s nh sau:

+ Trong SREFx 15-13 la chn in p tham chiu:

+ SHTx l bit la chn thi gian ly mu v gi:

+ ADC10SR Bit 10 l bt la chn tc ly mu:Bit = 1 tc ~ 50 ksps

Bit = 0 tc ~200 ksps

+ REFOUT Bit 9 Ng ra tham chiu:

Bit = 0 Ng ra tham chiu off

Bit = 1 Ng ra tham chiu on

+ REF2_5V Bit 6 La chn in p tham chiu:Bit = 0 Vref = 1.5 V

Bit = 1 Vref = 2.5 V

+ ADC10ON Bit 4:

Bit = 0 ADC10 off

Bit = 1 ADC10 on

+ ADC10IE Bit 3 Cho php ngt ADC10:Bit = 0 cm ngt

Bit = 1 cho php ngt

+ ADC10IFG Bit 2 C ngt:Bit =0 bo khng c ngt no i phc v

Bit = 1 Bo c ngt i phc v

+ ENC Bit 1 Bt cho php chuyn i:Bit = 0 cm chuyn i

Bit =1 cho php chuyn ib)Thanh ghi iu khin ADC10CTL1:

+ INCHx Bit 15- 12 : La chn ng vo:

+ ADC10DIVx Bit 7-5 La chn ngun b chia xung:

+ SSELx Bit 4-3 La chn ngun xung clock

c)Thanh ghi lu kt qu chuyn i ADC10MEM:

Kt qu 10 bit chuyn i c lu tr bn phi. Bit 9 l MSB. Bit 10-15 lun lun l 0.Knh chuyn i ADC12:ADC12 l knh chuyn i 12 bt c cc c tnh nh sau:+ Tc chuyn i ln hn 200-ksps.+ B chuyn i 12 bit n khng b li m.+ Ly mu v cht vi thi gian ly mu c lp trnh.

+ Qu trnh chuyn i c khi to bng phn mm hoc Timer_A, Timer_B.+ C th s dng phn mm la chn in p tham chiu (1.5V hoc 2.5V).+ C th la chn in p tham chiu ni hoc in p tham chiu ngoi.

+ C 8 knh u vo tng t, ring vi MSP 340x22xx c ti 12 knh u vo tng t.

+ Cc knh chuyn i cho cm bin nhit bn trong, Vcc, v in p tham chiu ngoi.

+ La chn ngun xung clock.

+ T ng iu khin qu trnh huyn i d liu v lu kt qu chuyn i, thanh ghi lu kt qu chuyn i l thanh ghi 16 bit.+ 18 ngt ADC12.

Hnh 18: S khi ca knh chuyn i tng t sang s ADC12

Tnh ton kt qu chuyn i s dng cng thc:

La chn ngun xung:

la chn ngun xung iu khin ta s dng bit ADC12SSELx. C th s dng b chia trc bng bit ADC12DIVx. ADC12CLK c th ly xung t cc ngun SMCLK, MCLK, ACLK hoc s dng bi xung ni ADC12OSC phc v ring cho n.

Tn s chuyn i c th ln ti 5-MHz, nhung gi tr ny cng ty thuc vo ngun cp, nhit v thay i do lp trnh. Phi lun cp xung clock trong qu trnh chuyn i, nu ngt ngun xung b chuyn i khng hot ng hoc kt qu chuyn i khng chnh xc.

Hnh 19: B a hp ng vo ADC12

Knh chuyn i ADC12 c tt c 12 ng vo tng t, 8 ng vo tng t ngoi v 4 ng vo ni, cc ng vo c la chn chuyn i bng b a hp.

in p tham chiu:Ta c th la chn in p tham chiu ni bng cch set bit REFON = 1, khi REFON = 0 la chn in p tham chiu ngoi VRFE+. Bit RFE2_5V la chn gi tr in p tham chiu ni. Khi REF2_5V = 1in p tham chiu ni l 2.5 V. Khi REF2_5V = 0 in p tham chiu ni l 1.5 V.

Ngt ADC12:Knh ADC12 c 18 ngun ngt bao gm:

+ ADC12IFG0-ADC12IFG15.+ Trn ADC12IFG0-ADC12IFG15.+ Trn thi gian chuyn i ADC12TOV, ADC12.Khi qu trnh chuyn i hon thnh bt ADC12IFGx c set v kt qu chuyn i c lu vo thanh ghi ADC12IFGx. Khi mt ngt c to ra.Cc thanh ghi iu khin ADC12:

Bng 7: Thanh ghi iu khin ADC 12Thanh ghi iu khin ADC12CTL0:\

Knh chuyn i s sang tng t DAC12:L knh chuyn i 12 bit. Tuy nhiu n c th c cu hnh 8 bit hoc 12 bit.

Nhng c tnh ca knh chuyn i DAC12 bao gm:

+ C th s dng in p tham chiu ni v in p tham chiu ngoi.+ phn gii 8 hoc 12 bit.+ Lp trnh thi gian v cng sut ngun.+ Kh nng cp nht d liu ng b cho nhiu knh DAC.

Hnh 20: S khi ca knh chuyn i DAC12Hot ng ca knh chuyn i DAC12:

Knh chuyn i s sang tng t DAC12 c th cu hnh hot ng ch 8 bit hoc 12 bit bng cch s dng bit DAC12RESx. Bit DAC12IR la chn in p tham chiu. Bt DAC12 cho php ngi s dng la chn d liu kiu nh phn tiu chun hay 2s-compliment.

Khi s dng kiu nh dng d liu kiu nh phn tiu chun, in p u ra c tnh nh sau:

Trong ch 8 bit, gi tr ln nht ca DAC12_xDAT l 0FFh. Trong ch 12 bit gi tr ti a ca DAC12_xDAT l 0FFFh.in p tham chiu ca knh DAC12:C th la chn in p tham chiu ngoi hoc in p tham chiu ni vi 2 mc in p tham chiu 1.5 V v 2.5 V. in p tham chiu c la chn bng bit DAC12SREFx. Khi DAC12SREFx = {0,1} s dng in p tham chiu VREF+ DAC12SREFx = {2,3} s dng in p VeREF+ .Ngt ca DAC12:

Vector ngt ca DAC 12 c chia s vi b iu khin DMA, v vy xc nh nguyn nhn gy ra ngt bn phi kim tra c ngt DAC12IFG v DMAIFG.

Bit DAC12IFG c set khi DAC12LSELx > 0 v d liu DAC12 c cht. Khi DAC12LSELx = 0 Bit DAC12IFG khng c set.

Vic set bit DAC12IFG ch nh rng DAC12 sn sng cho qu trnh chuyn i mi. Nu c 2 bt DAC12IFG v GIE c set s to ra mt tn hiu ngt. C ngt DAC12IFG khng t ng reset bn phi t li n bng phn mm.Cc thanh ghi DAC12:

Bng 8: Thanh ghi DAC12a)Thanh ghi iu khin DAC12_xCTL:

+ DAC12OPS Bit 15 la chn ng ra DAC12: Bit = 0 ng ra DAC12_0 l chn P6.6, ng ra DAC12_1 l chn P6.7.Bit = 1 ng ra DAC12_0 l chn VeREF+, ng ra DAC12_1 l chn P6.5.+ SREFx Bt 14-13: La chn in p tham chiu:

00VREF+

01VREF+

10VeREF+

10VeREF++ RES Bit 12: La chn phn gii:Bit = 0 : phn gii 12 bit

Bit = 1 : phn gii 8 bit

+ CALON Bit 9: Bit hiu chnh trn:Bit = 0: Khng hiu chnh

Bit = 1: Tin hnh hiu chnh

+ DAC12IR Bit 8: Bit dng set in p tham chiu ng vo v phm vi in p ra:Bit = 0: Nhn 3 in p tham chiu

Bit = 1: Gi nguyn gi tr in p tham chiu+ DAC12 Bit 7-5 Ci t cc thng s ca b khuch i:

+ DAC12DF Bit4: nh dng d liu DAC12:Bit = 0 D liu kiu nh phn

Bit = 1 D liu kiu b 2 (2s complement)+ DAC12IE Bit3: Cho php ngt DAC12:

Bit = 0 Cm ngt

Bit = 1 cho php ngt+ DAC12IFG Bit 2: C ngt DAC12:

Bit = 0 Khng c ngt no ch

Bit = 1 C ngt ang ch phc v

+ DAC12ENC Bit 1: Cho php chuyn i DAC12, khi bit DAC12ENC > 0 cho php chuyn i, khi DAC12ENC = 0 khng cho php chuyn i.b)Thanh ghi d liu DAC12_xDAT:

+ DAC12_xDAT l thanh ghi 16 bit. Trong Bit 15-12 khng s dng nhng bit ny lun bng 0. + DAC12Data Bit 11-0 l bit d liu.

H thng xung clock v b pht xung:H thng xung clock ca MSP 430f2274 c chia thnh nhiu khi khc nhau, mi module s cung cp xung clock cho cc khi ngoi vi ng dng tng ng.

MSP 430 c thit k p ng yu cu tit kim nng lng nn thch anh ngoi c s dng c tn s 32768 HZ. Nhng chng ta c th thay i tn s hot ng bng b iu khin tn s dao ng DCO(DCO_digitally-controlled oscillator).

Trong MCLK: L xung clock s dng cho CPU.SMCLK: H thng xung clock s dng cho cc module ngoi vi.

Thanh ghi iu khin DCOCTL:

DCOx : Bit 7-5 l bt la chn tn s xung. C 8 gi tr xung khc nhau c nh ngha nh thanh ghi RSELx MODx : Bit 4-0 BIT la chn b iu ch. Nhng bit ny thng c nh ngha s dng tn s fDCO+1 trong khong thi gian l 32 chu k. Khong thi gian cn li (32-MDO) tn s fDCO c s dng. Khng th s dng cc bt ny khi DCOx=7.Thanh ghi iu khin h thng xung BCSCTL1:

+ XT2OFF Bit 7: Bit iu khin b pht xung XT2:Bit =0 XT2 on

Bit = 1 XT2 off. Nu n khng c s dng cho MCLK hoc SMCLK+ XTSBit 6: L bt la chn ch :Bit = 0 la chn ch tn s thpBit = 1 la chn ch tn s cao

+ DIVAx Bit 5-4: Cc bt la chn b chia cho ACLK

00

/101 /2

10

/411

/8+ RSELxBit 3-0 La chn di tn s. C sn 16 di tn s khc nhau. Gi tr di tn s thp nht c la chn khi RSELx = 0. Bt RSEL3 c b qua khi DCOR=1.Thanh ghi iu khin BCSCTL2:

+ SELMxBit 7-6 Bt la chn ngun xung cho MCLK:00 DCOCLK

01 DCOCLK

10 2CLK khi b pht xung XT2 c sn trn chp. LFXT1CLK hoc VLOCLK khi b pht xung XT2 khng c sn trn chp.

11 FXT1CLK hoc VLOCLK

+ DIVMxBit 5-4Bt la chn b chia cho MCLK:

00

/1

01

/2

10

/4

11

/8

+ SELS

Bit3 Bit la chn ngun SMCLK:Bit =0 DCOCLK

Bit = 1XT2 khi b pht xung XT2 c sn trn chp. LFXT1CLK hoc VLOCLK khi b pht xung XT2 khng c sn trn chp+ DIVSxBit 2-1Bt la chn b chia cho SMCLK :

00 /1

01 /2

10

/4

11

/8

+ DCORBit 0 Bt la chn in tr DCO:Bit = 0 in tr ni

Bit = 1 in tr ngoi

Thanh ghi cho php ngt IE1:

OFIF

BIT 1

Bit =1 Cho php ngt

Bit =0 Khng cho php ngt

Cc bt cn li c s dng cho module khc.

Thanh ghi c ngt:

OFIFGBit 1Bit =0 Khng c ngt no ang c phc ph

Bit =1 C ngt ang c phc vCc bt cn li c th c s dng bi cc module khc.

Moun eZ430-RF2500:

Cng c pht trin eZ430-RF2500:eZ430-RF2500:

eZ430-RF2500 L mt th giao tip USB v truyn nhn d liu khng dy. eZ430-RF2500 c pht trin da trn MSP 430F2274 kt hp vi chp CC2500 truyn nhn tn hiu tn s RF 2.4 GHz, tch hp sn cm bin nhit . Do c im dng MSP 430 c nhng u th v nng lng nn p ng c nhng nhu cu trong thit b di ng. MSP430 dng ngun 3.6V nn trong thit k ny c th s dng pin Lithiun 3.7 V.

B eZ430-RF2500T l mt sn phm c th lm vic vi u cm USB nh mt h thng c lp vi cm bin bn ngoi. Hoc s dng thit k m rng vi nhng module ngoi vi. Vi Giao din g li USB cho php sn phm c th truyn v nhn d liu t xa t my tnh c nhn s dng truyn nhn nhn ni tip UART

c tnh ca eZ430-RF2500:

+ Giao din lp trnh v g li.+ C sn 21 chn.

+ Mt tch hp cao, MSP 430 c ngun cc thp siu tit kim nng lng.

+ Hai chn xut/ nhp kt ni vi hai led xanh v cho php ngi lp trnh m phng trc quan.

+ Mt nt nhn dng m phng trc quan.

Hnh 21: Board eZ430-RF2500 USB

Hnh 22: Board eZ430-RF2500 dng PIN

Chc nng cc chn:

Nhng c tnh c bit ca MSP 430 bn c th tham kho trong phn gii thiu chi tit trn. MSP 430 c s dng xy dng board eZ430-RF2500. Ngoi ng dng truyn nhn tn hiu t xa, board cn ly ra 18 chn cho ngi lp trnh thc hnh v pht trin nhng ng dng ring ca mnh.

Hnh 23: S chn board eZ430-RF250Chc nng cc chn board eZ430-RF2500

PinChc nngM t

1GNDMass

2VccChn ngun Vcc 1.8V - 3.6V

3P2.0 / ACLK / A0 / OA0I0Chn xut/nhp s, ng ra xung clock ACLK, ng vo tng t A0 knh ADC10

4P2.1 / TAINCLK / SMCLK / A1 /A0OChn xut/nhp s, ng vo analog A1 knh ADC10, xung clock INCLK ca Timer_A, xung clock ch SMCLK

5P2.2 / TA0 / A2 / OA0I1Xut/nhp, ng vo tng t A2 ca knh ADC10, ng vo CCI0B ca Timer_A ch capture, ng ra OUT0 ch so snh.

6P2.3 / TA1 / A3 / VREF / VeREF OA1I1 / OA1OXut/nhp, ng vo tng t A3 knh ADC10, in p tham chiu m VREF / VeREF , ng vo CCI1B ca Timer_A, ng ra OUT1 ch so snh.

7P2.4 / TA2 / A4 / VREF+ / VeREF+/ OA1I0Chn xut/nhp s, ng vo tng t A4 knh ADC10, ng ra OUT2 Timer_A ch so snh, ng vo/ra in p tham chiu.

8P4.3 / TB0 / A12 / OA0OChn xut/nhp s, ng vo tng t A12 knh ADC10, ng vo CCI0B Timer_B ch capture, ng ra OUT0 ch so snh

9P4.4 / TB1 / A13 / OA1OChn xut/nhp s, ng vo tng t A13 knh ADC10, ng vo CCI1B Timer_B ch capture, ng ra OUT1 ch so snh

10P4.5 / TB2 / A14 / OA0I3Chn xut/nhp s, ng vo tng t A14 knh ADC10, ng ra OUT0 ca Timer_B ch so snh

11P4.6 / TBOUTH / A15 / OA1I3Chn xut/nhp s, ng vo tng t A15 knh ADC10, chuyn mch t TB0 sang TB3 ng ra tng tr cao.

12GNDMass

13P2.6 / XIN (GDO0)Chn xut/nhp s, kt ni thch anh

14P2.7 / XOUT (GDO2)Chn xut/nhp s, kt ni thch anh

15P3.2 / UCB0SOMI / UCB0SCLChn xut/nhp s, ng ra ch t, ng vo ch ch USCI_B0 trong ch SPI, ngun xung clock SCLI2C trong I2C mode

16P3.3 / UCB0CLK / UCA0STEChn xut/nhp s, ng vo xung clock USCI_B0, ng ra cho php truyn d liu USCI_A0 trong ch t

17P3.0 / UCB0STE / UCA0CLK / A5Chn xut/nhp s, ng vo tng t A5 knh ADC10, xung USCI_A0, chn cho php truyn tn hiu USCI_B0 trong ch t

18P3.1 / UCB0SIMO / UCB0SDAChn xut/ nhp s, , ng ra ch t, ng vo ch ch USCI_B0 trong ch SPI, d liu SDAI2C trong I2C mode

Bng 9: Chc nng cc chn board eZ430-RF2500

Chc nng cc chn Battery Board

PINChc nngM t

1P3.4 / UCA0TXD / UCA0SIMO

Chn xut/nhp s, chn truyn d liu USCI_A0 trong ch UART, ng vo ch t, ng ra ch ch trong ch SPI

2GND

Mass

3RST / SBWTDIO

Chn reset tch cc mc thp

4TEST / SBWTCK

La chn ch kim tra cho chn JTAG ca port 1.

5VCC (3.6V)

Ngun Vcc 3.6V

6P3.5 / UCA0RXD / UCA0SOMIChn xut/nhp s, chn nhn d liu USCI_A0 trong ch UART, ng vo ch t, ng ra ch ch trong ch SPI

Bng 10 : Chc nng cc chn Battery Board

Thng s k thut:

MSP430F2274:Thng sMINTYPMAXUNIT

iu kin lm vic

in p1.83.6V

Nhit -4085oC

Dng tiu th

Ch hot ng ti 1MHz, 2.2V270390A

Ch ngh0.71.4A

Ch tt duy tr RAM0.10.5A

Tn s lm vic

Vcc 3.3V16MHz

Bng 11: Cc thng s k thut ca MSP430F2274

CC2500:+ Tn s: 2.4 GHz.

+ Tc : 500 kbps.+ Dng tiu th thp.Thng siu kinMINTYPMAXUNIT

iu kin lm vic

in p1.83.6V

Dng tiu th

Tn hiu vo RX 250 kbps

Dng ti u16.6mA

Optimized sensitivity18.8mA

Tn hiu vo RX 30 dB 250 kbpsDng ti u13.3mA

Optimized sensitivity15.7mA

Dng tiu th TX (0 dBm)21.2mA

Dng tiu th

TX (-12 dBm)11.1mA

c tnh tn s

Tn s24002483.5MHz

D liu1.2500kbps

Cng sut ng ra-300dBm

nhy 10 kbps

Dng ti u , 2-FSK, 230-kHz-99dBm

Lc thng di RX, 1% PER101dBm

nhy 250 kbps nhy ti u-87dBm

Dng ti u, 500-kHz RX-89dBm

Bng 12: Cc thng s k thut ca CC2500S mch eZ430-RF2500:

Hnh 24: S nguyn l ca USB

Hnh 25: S nguyn l ca USB

Hnh 25: S nguyn l ca board eZ430-RF2500TChip CC2500:

Gii thiu:CC2500 l chp thu pht sng v tuyn RF tn s 2.4 GHz. Chip s dng ngun thp tit kim nng lng c th s dng pin. Thch hp vi nhng thit b di ng iu khin bng cng ngh khng dy, thit b in t dn dng, iu khin chi, chut v bn phm khng dy, cc ng dng iu khin t xa khc.B thu pht c tch hp vi cu hnh modem di gc cao. Modem h tr nhiu hnh thc iu ch tn hiu khc nhau trong cu hnh d liu ln ti 500 Kbaud.

CC2500 h tr phn cng cho vic x gi d liu.

Tch hp cm bin nhit .Thng CC2500 kt hp vi mt chip vi x l v cc linh kin th ng khc thc hin chc nng iu khin.

Phn cng bao gm 20 chn:

Hnh 26: S chn ca CC2500

+ Chn 4, 9, 11, 14, 15, 18: L cc chn ngun ni ln Vcc.+ Chn 16, 19 ni GND.+ Chn 8, 10 ni vi thch anh.Chc nng chi tit cc chn cn li nh sau:

Bng 13: Chc nng cc chn CC2500

+ Chn 1: SCLK chn u vo s, chn u vo nhn xung clock v giao din cu hnh ni tip

+ Chn 2: u ra s. Giao din cu hnh ni tip. Khi CSn mc cao th chn c chc nng ca mt chn thng thng.

+ Chn 3: GDO2: u ra s. L chn u ra cho mc ch s dng chung

- Kim tra tn hiu.

- Trng thi tn hiu FIFO.- Xa chn c ch nh.- Chn u ra ca xung clock sau khi c chia xung t XOSC.- Chn truyn d liu ni tip RX.+ Chn 4: Chn ngun DVDD. S dng ngun t 1.8 ti 3.6V

+ Chn 5: DCOPUL: Chn ngun 1.6-2V. Chn ny ch s dng cp ngun + ring cho CC2500 khng s dng chung cho cc thit b khc.

+ Chn 6: GDO0:Chn vo ra s. Ngoi cc chc nng nh chn 3 n cn c vai tr l chn truyn nhn ni tip RX v TX.

+ Chn 7: CSn: L chn u vo la chn.

+ Chn 8, 10: XOSC_Q1, XOSC_Q2: Chn ni thch anh.+ Chn 9, 11, 14, 15: Chn ngun cp ngun 1.8-3.6V cho khi Analog.+ Chn 12 RF_P: L chn truyn nhn tn hiu RF. L chn u vo trong ch truyn, chn u ra trong ch nhn.

+ Chn 13 RF_N: C chc nng nh chn 12 nhng tn hiu b o.

+ Chn 16, 19: GND.+ Chn 17 RBIAS: Chn vo ra tng t.

+ Chn 20 SI: Chn ng vo s. Giao din cu hnh ni tip.

Cu to ca chp:

Hnh 27: Cu to CC2500

Nguyn l hot ng:

CC2500 ng vai tr l b nhn. Tn hiu c khuch i bi b khuch i LNA v b i pha vung gc gim tn hiu xung tn xung tn s trung bnh (IF) sau tn hiu c s ha bi cc b chuyn i ADC. Tn hiu a ti mch t ng iu chnh li (AGC).Nhng linh kin s dng trong mch in ng dng:SBng 14: Nhng linh kin s dng trong mch in

S mch in c th nh sau:

Hnh 28: S mch in

Gi tr in hnh ca cc linh lin c s dng trong mch:Bng 15: Gi tr ca cc linh lin c s dng trong mchPhn mm bin dch v np chng trnh (The IAR Embedded Workbench IDE):i vi MSP430 chng ta c 2 phn mm bin dch v np chng trnh l:+ The IAR Embedded Workbench IDE.

+ CCE.S dng 2 ngn ng Assembly v C/C++. y nhm nghim cu ch gii thiu phn mm The IAR Embedded Workbench IDE.

Cch ci t phn mm:Trong mi b th nghim MSP430 c mt a CD gii thiu cho ta 2 phn mm The IAR Embedded Workbench IDE v CCE. Cch ci t v mt chng trnh demo o nhit mi trng t xa.

Sau khi b a vo my, ta vo a CD; F:\Software nhp p vo file FET_R511.exe bt u qu trnh ci t. Sau khi nhp vo ta thy mn hnh c:

Nhp v ch Setup phn mm bt u c ci t. Sau mn hnh s xut hin nh sau v bm Next, sau bm Accept: Chn th mc ci t phn mm (ta nn nguyn),sau bm Next:Chn Full ri bm Next s ra mn hnh nh sau ri bm Next:Sau bm Next, ci t phn mm vo my:Cui cng bm Finish, hon tt qu trnh ci t.

Ngoi mn hnh Destop v: Start/ All Programs / IAR Systems / IAR Embedded Workbench Kickstart for MSP430 V4.10E nhp p v IAR Embedded Workbench bt u chy chng trnh IAR Embedded Workbench.Sau khi ci t xong phn mm, chng ta bt u ci t thit b (Ch : Phi ci t xong phn mm ri mi ci t thit b).Ci t thit b:Cm eZ430-RF2500 vo cng USB ca my tnh. Gc bn phi pha di destop s xut hin:

My tnh xc nhn c 1 cng mi. Sau s xut hin:

My tnh xc nhn chip ca MSP430 theo chun UART. Sau mn hnh s xut hin:

My tnh t ng tm a mi. Chn No, not this time ri nhp Next. Mn hnh s xut hin:

Chn Install the software automatically (Recommended) ri tip tc bm Next (Ch thc hin c lnh ny khi ci t phn mm IAR Embedded Workbench Kickstart for MSP430 V4.10E). Mn hnh s xut hin:

Bm Continue Anyway cho my tnh tip tc tm cng mi. Khi qu trnh ny xong, my tnh nhn c thit b eZ430 RF2500.

kim tra coi my tnh ng nhn thit b eZ430 RF2500 ta tip tc lm theo cch sau. mn hnh Destop v: Start / My Computer.

Nhp chut phi ta chn Manage. Mn hnh s xut hin:Sau chn vo Device Manager. Mn hnh s xut hin:

Mn hnh pha bn phi ta m tab: Port (COM & LPT). Khi mn hnh s xut hin:

Ta thy trong tab: Port (Com & LPT) c dng MSP430 Application UART (COM 5). Cho bit rng my tnh nhn thit b eZ430 RF2500. y COM 5 ch l ni cm thit b, c ngha my tnh nhn thit b eZ430 RF2500 cng USB s 5.

Ta xong phn ci t thit b, phn tip theo l lm theo s dng phn mm, cch to 1 Project mi v cch thm vo 1 Project c.

Hng dn s dng phn mm (The IAR Embedded Workbench IDE):Gii thiu:

IAR Embedded Workbench IDE l phn mm h tr y cc cng c lp trnh cho dng sn phm MSP 430. khun kh mt ti liu hng dn s dng xin c gii thiu ti cc bn mt vi c tnh ca phn mm nh sau:

+ Trnh bin dch cp cao c ti u ha MSP430 IAR C/C++.

+ H tr trnh bin dch MSP430 IAR Assembler.

+ Cng c g li mnh IAR C-SPY debugger.

Sau khi ci t xong click vo ng link th mn hnh s xut hin biu tng sau:

Hnh 29: Ca s khi ng IAR Embedded Workbench IDEClick vo biu tng ta c mn hnh son tho nh sau:

Hnh 30: Mn hnh ca IAR Embedded Workbench IDE

Gii thiu ca s son tho ca chng trnh:

Hnh 31: Thanh cng c son thoIAR Embedded Workbench IDEHng dn to New Project:

Tt ca s Startup . to mt Project trc tin bn phi ng ht cc Workspace v Project c sn . Chn File / close Workspake. Sau bn vo Window / close All Editor Tabs .

Hnh 32: ng Workspace c sn

Hnh 33: ng tt c Editor Tabs

to mt Project ta chn Project / Create New Project. Hp thoi xut hin:

Hnh 34: Ca s to project mi

Kim tra Tool chain chn MSP430 sau lick OK. Mt ca s mi hin ra bn t tn File ri Save hon thnh cc bc to mt Project mi. Bn nn to sn mt th mc mi trong a cng lu nhng Project ca mnh.

Hnh 35: Ca s Save chng trnh

Project s xut hin trong vng lm vic .

Hnh 36: Ca s vng lm vic

Bn phi Save vng lm vic mt ln na. Chn File / Save Workspace, mt hp thoi xut hin yu cu bn chn ni lu vng lm vic. Bn nn chn Save vo cng th mc vi Project to.

Hnh 37: Hp thoi New Workspake

Bn to mt Workspace, bn c th to nhiu Project khc nhau trong cng mt vng lm vic. Nh vy bn to thnh cng mt Project mi, bn c th bt u lp trnh trong vng son tho.

Hnh 38: Ca s son tho

Thit lp cc thng s cho Project:

thit lp cc thng s cho Project bn Click Baitap1-Debug trn ca s Workspace sau vo Project / Options .Ty chn Target trong category General Options c hin th . Ca s Device cho chng ta chn loi chip cn lp trnh , bn hy chn MSP 430F2274.

Hnh 39: Ci t cc ty chn

Chn C/C++Compiler trong Category hin th trang ty chn bin dch, chn ngn ng lp trnh C .

Hnh 40: Setting compiler options

Chn Debugger trong Category. Trong ca s Driver chn FET Debugger chn tnh nng g li v np xung cho vi iu khin sau click OK.

Hnh 41: DebuggerBin dch v kim tra:Sau khi son tho chng trnh bc tip theo l bin dch v kim tra li. bin dch chng trnh bn chn Project / Compile, chng trnh bin dch thnh cng s hin ln ca s nh sau:

Hnh 45: Bin dch v kim tra thnh cng np chng trnh cho vi iu khin Bn chn Project / Debug, sau khi np thnh cng bn chn Debug / Go. Ca s ny ch hin ra khi bn np thnh cng, bn c th tm dng hoc thot bng tc lnh Break v Stop Debugging.

Hnh 46: Np chong trnhThm Project vo Workspace:Nh gii thiu trn bn c th to nhiu project trong cng mt Workspace hoc add cc project c sn trong th vin vo vng lm vic ca bn. Bn c th s dng cc ngn ng lp trnh khc nhau cho cc project trong cng mt vng lm vic, y l mt trong nhng tnh nng u vit ca IAR Embedded Workbench IDE gip ngi lp trnh so snh v la chn gii php lp trnh ti u.

add files bn Chn Project-> Add Files, hp thoi hin ra yu cu bn chn file cn thm vo, chn file sau click OK hon tt. Bn c th Add mt hoc nhiu files kt qu ta c mt vng lm vic vi nhiu projet mi nh sau:

Hnh 47: Thm Project vo Workspace

Hnh 48: Thm vo thnh cngTp lnh C s dng lp trnh:

Tp lnh C c vit da trn help ca phn mm IAR Embedded Wowkbench. Bn c th s dng tt c cc lnh v hm C c bn, ngoi ra IAR Embedded Wowkbench cn h tr mt s hm chc nng c bit.

Cc kiu d liu c bn:Khi lp trnh bn phi lu ti cc php ton c th trn s, tnh ton vi s m hoc p kiu d liu. Bn c th khai bo mt bin cc b hoc bin ton cc. Bin ton cc nh hng ti ton b chng trnh cn bin cc b ch c gi tr trong hm hoc khi lnh m bn khai bo n. Sau y l cc kiu d liu c bn.

Kiu d liuKch thc

(Byte)

char1

Unsigned char1

signed char1

int2

unsigned int2

signed int2

short int2

unsigned short int2

signed short int2

long int4

signed long int4

unsigned long int4

float4

double8

long double10

Trong chng trnh i khi ta cn gp cc t kha c bit.const: l t kha khai bo hng s, c ngha l gi tr ca bin khng thay i.

volatile: khai bo trc tn bin l mt loi bin khng b thay i bi phn mm, bn thn bin gip ti u ha li c cu chng trnh.

shifts: dch chuyn bit.

Ton t quan h v logic:Ton t quan h dng kim tra mi quan h gia hai bin hay gia mt bin v mt hng.

Ton t quan h.Ton t ngha

>Ln hn

>=Ln hn hoc bng

Dch phi bit

_BYTE = 0xff;

// nh ngha Port 2 l xut volatile unsigned int a;

// Bin khai bo trong RAM

{

a=0xA4BC;

// Gn a = A4BC MoRongP2(a);

// M rng tng 2 vi 16 bit ca a }

}

void MoRongP2(unsigned int e)

// Hm m rng tng th 2 {

volatile unsigned int f,g,h;

// Bin khai bo trong RAM f=0x8000;

// Gn f=8000 g=16;

// Cho g=16 while(g>0)

// Trong khi g>0 th thc hin {

h = e&f;

// h = e and f if ( h == f)

// Nu h=f {

_P3_OUT->_BIT.b2=1;

// bit 2 port 3 l mc 1 }

Else

// ngc li h khng =f {

_P3_OUT->_BIT.b2=0;

// bit 2 port 3 mc 0 }

_P2_OUT->_BIT.b4=0; // bit 4 port 2 mc 1(xung clock) _P2_OUT->_BIT.b4=1; // bit 4 port 2 mc 0 f=f>>1;

// Xoay phi f g--;

// Gim g i 1 }

_P3_OUT->_BIT.b0=0;

// bit 04 port 3 mc 1(xung cht) _P3_OUT->_BIT.b0=1;

// bit 04 port 3 mc 1 }3.4.3 Cc bi tp v Led n:Bi 1: iu khin 16 led chp tt.

Lu :Kt ni phn cng:+ Ni 16 bit ca tng m rng th 2 vi 16 Led n.Chng trnh:#include "msp430x22x4.h" // Khai bo chip

void Delay(unsigned int Value);

// Khai bo hm Delayvoid MoRongP2(unsigned int e);

// Khai bo hm m rng tng 2union reg {

// Khai bo 1 byte 8 bit struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;

unsigned char _BYTE;

};

union reg* _P3_DIRECT = (union reg*)0x1A ;

union reg* _P3_OUT = (union reg*)0x19 ;


union reg* _P2_OUT = (union reg*)0x29 ;int main(void)

// Chng trnh chnh {

WDTCTL = WDTPW + WDTHOLD;// Dng ngt

_P3_DIRECT->_BYTE = 0xff;


volatile unsigned int n;

// Bien khai bo trong RAM

{

for(;;)

// Vng lp v nh {

n=0xffff;

// 16 Led sng MoRongP2(n);

// Gi hm m rng tng 2 vi gi tr n Delay(10000);

// Gi hm delay vi gi tr 10000 n=0x0000;

// 16 Led tt MoRongP2(n);

Delay(10000);

}

}}void MoRongP2(unsigned int e)

// Hm m rng tng 2 {


f=0x8000;

g=16;

while(g>0)

{

h = e&f;

if ( h == f)

{

_P3_OUT->_BIT.b2=1;

}

else

{

_P3_OUT->_BIT.b2=0;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}

void Delay(unsigned int Value)

// Hm delay {

volatile unsigned int l = 0;

for(l=Value; l>0; l--);

}Bi 2: iu khin im sng chy 16 Led n:

Lu :

Kt ni phn cng:+ Ni 16 bit ca tng m rng th 2 vi 16 Led n.Chng trnh:#include "msp430x22x4.h" // Khai bo chip





unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};





// Chng trnh chnh {




volatile unsigned int n,p;


{

for(;;)

// Vng lp v nh {

n=0x0001;

// Gn n = 0001; p=16;

// Cho p =16; while(p>0)

// Trong khi p>0 th {

MoRongP2(n);

// Gi hm m rng tng 2 vi gi tr n Delay(10000);

// Gi hm Delay vi gi tr 10000

n=n_BIT.b2=1;

}

else

{

_P3_OUT->_BIT.b2=0;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}


// Hm delay {



}Bi 3: iu khin im sng chy 32 Led n:

Lu :

Kt ni phn cng:+ Ni 16 bit ca tng m rng th 2 vi 16 Led n.+ Ni 16 bit ca tng m rng th 3 vi 16 Led n cn li.

Chng trnh:#include "msp430x22x4.h" // Khai bo chip



// Khai bo hm m rng tng 2

void MoRongP3(unsigned int i);



unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};union reg* _P4_DIRECT = (union reg*)0x1E ;

union reg* _P4_OUT = (union reg*)0x1D ;





int main(void)

// Chng trnh chnh {





volatile unsigned int n,m,q,p;


{

for(;;)

// Vng lp v nh {

n=0x0001;

p=16;

while(p>0)

{

MoRongP2(n);

Delay(10000);n=n_BIT.b2=0;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}void MoRongP3(unsigned int i)

// Hm m rng tng 3 {

volatile unsigned int j,k,l;

j=0x8000;

k=16;

while(k>0)

{

l = i&j;

if ( l == j)

{

_P4_OUT->_BIT.b4=1;

}

else

{

_P4_OUT->_BIT.b4=0;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

j=j>>1;

k--;

}

_P4_OUT->_BIT.b6=0;

_P4_OUT->_BIT.b6=1;

}


// Hm delay {



}Bi 4: iu khin 32 Led n sng dn:

Lu :Kt ni phn cng:+ Ni 16 bit ca tng m rng th 2 vi 16 Led n.

+ Ni 16 bit ca tng m rng th 3 vi 16 Led n cn li.

Chng trnh:#include "msp430x22x4.h" void MoRongP2(unsigned int e);



union reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};

union reg* _P4_DIRECT = (union reg*)0x1E ;






int main(void)

// Chng trnh chnh {

WDTCTL = WDTPW + WDTHOLD;




volatile unsigned int o,n,q,m,p,t,s; for(;;)

{

n=0x0000;

m=0x0001;

q=16;

while (q>0)

{

n=n|m;

MoRongP2(n) Delay(10000);;

m=m_BIT.b2=0;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}

void MoRongP3(unsigned int i)

// Hm m rng tng 3 {


j=0x8000;

k=16;

while(k>0)

{

l = i&j;

if ( l == j)

{

_P4_OUT->_BIT.b4=1;

}

else

{

_P4_OUT->_BIT.b4=0;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

j=j>>1;

k--;

}

_P4_OUT->_BIT.b6=0;

_P4_OUT->_BIT.b6=1;

}


// Hm DeLay {



}3.4.4 Cc bi tp v Led 7 on:Bi 1: m t 0 999 hin th Led 7 on:

Lu :

Kt ni phn cng:+ Kt ni 8 bit u ca knh m rng th 2 vi 7 on v du chm thp phn ca Led 7 on.

+ Kt ni 8 bit u ca knh m rng th 3 vi 8 transistor iu khin qut Led.

Chng trnh:#include "msp430x22x4.h" void Delay(unsigned int Value);

void MoRongP2(volatile unsigned int e);

void MoRongP3(volatile unsigned int i);

void Hex_BCD();

// Khai bo hm chuyn i Hex - BCDvoid HienThi();

// Khai bo hm HienThiunion reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};







volatile unsigned char baydoan[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};// Khai bo m Led 7 onvolatile unsigned int nghin,tram,chuc,dvi,bien,n;

int main(void)

// Chng trnh chnh {





for(;;)

{

bien=0;

for(bien=0;bien0)

{

h = e&f;

if ( h == f)

{

_P3_OUT->_BIT.b2=0;

}

else

{

_P3_OUT->_BIT.b2=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}


// Hm m rng tng 3 {


j=0x80;

k=8;

while(k>0)

{

l = i&j;

if ( l == j)

{

_P4_OUT->_BIT.b4=0;

}

else

{

_P4_OUT->_BIT.b4=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

j=j>>1;

k--;

}

_P4_OUT->_BIT.b6=0;

_P4_OUT->_BIT.b6=1;

}Bi 2: ng h s hin th Led 7 on:

Lu :Kt ni phn cng:+ Kt ni 8 bit u ca knh m rng th 2 vi 7 on v du chm thp phn ca Led 7 on.

+ Kt ni 8 bit u ca knh m rng th 3 vi 8 transistor iu khin qut Led.Chng trnh:#include "msp430x22x4.h"




void Hex_BCD();

void HienThi();

union reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};







volatile unsigned char baydoan[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};

volatile unsigned int CHGio,DVGio,CHPhut,DVPhut,CHGiay,DVGiay;

volatile unsigned long bien;

int main(void)

// Chng trnh chnh {

WDTCTL = WDTPW + WDTHOLD




for(;;)

{

CHGio=0;DVGio=0;CHPhut=0;DVPhut=0;CHGiay=0;DVGiay=0;

for(bien=0;bien0)

{

h = e&f;

if ( h == f)

{

_P3_OUT->_BIT.b2=0;

}

else

{

_P3_OUT->_BIT.b2=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}


// Hm m rng tng 3 {


j=0x80;

k=8;

while(k>0)

{

l = i&j;

if ( l == j)

{

_P4_OUT->_BIT.b4=0;

}

else

{

_P4_OUT->_BIT.b4=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

j=j>>1;

k--;

}

_P4_OUT->_BIT.b6=0;

_P4_OUT->_BIT.b6=1;

}3.4.5 Cc bi tp v LCD:Bi 1: Hin th ch Th nghim VDK MSP 430 trn 2 dng bng cch lit k.

Lu :

Kt ni phn cng:+ Ni chn 10 eZ430-RF2500T iu khin chn E ca LCD.

+ Ni chn 8 ca eZ430-RF2500T iu khin chn RW ca LCD.

+ Ni chn 6 ca eZ430-RF2500T iu khin chn RS ca LCD.

+ Kt ni 8 bit sau ca tng m rng th nht vi 8 ng d liu LCD.

Chng trnh:#include "msp430x22x4.h"


void MoRongP1(volatile unsigned int a);

void DKLCD();

// Khai bo hm iu khin LCDvoid DLLCD();

// Khai bo hm ghi d liu LCDunion reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};







// Chng trnh chnh {





MoRongP1(0x00);

Delay(500);

MoRongP1(0x01);

// Lnh xo mn hnh DKLCD();

MoRongP1(0x38);

// Cho php hin 2 dng DKLCD();

MoRongP1(0x0C);

// Tt con tr DKLCD();

MoRongP1(0x83);

// Hin ch Thi Nghiem dng 1 ct 3 DKLCD();

MoRongP1('T');

DLLCD();

MoRongP1('h');

DLLCD();

MoRongP1('i');

DLLCD();

MoRongP1(' ');

DLLCD();

MoRongP1('N');

DLLCD();

MoRongP1('g');

DLLCD();

MoRongP1('h');

DLLCD();

MoRongP1('i');

DLLCD();

MoRongP1('e');

DLLCD();

MoRongP1('m');

DLLCD();

MoRongP1(0xC2);

// Hin ch VDK MSP430 dng 2 ct 2 DKLCD();

MoRongP1('V');

DLLCD();

MoRongP1('D');

DLLCD();

MoRongP1('K');

DLLCD();

MoRongP1(' ');

DLLCD();

MoRongP1('M');

DLLCD();

MoRongP1('S');

DLLCD();

MoRongP1('P');

DLLCD();

MoRongP1('4');

DLLCD();

MoRongP1('3');

DLLCD();

MoRongP1('0');

DLLCD();

}void DKLCD()

// Hm iu khin LCD {

_P2_OUT->_BIT.b3=1;

// _P4_OUT->_BIT.b3=1;

_P4_OUT->_BIT.b5=0;

Delay(50);

_P4_OUT->_BIT.b5=1;

Delay(5);

}

void DLLCD()

// Hm ghi d liu LCD {

_P2_OUT->_BIT.b3=0;

_P4_OUT->_BIT.b3=1;

_P4_OUT->_BIT.b5=0;

Delay(50);

_P4_OUT->_BIT.b5=1;

Delay(5);

}void MoRongP1(unsigned int a)// Hm m rng tng th 1 {

volatile unsigned int b,c,d;

b=0x8000;

c=16;

while(c>0)

{

d = a&b;

if ( d == b)

{

_P3_OUT->_BIT.b1=0;

}

else

{

_P3_OUT->_BIT.b1=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

b=b>>1;

c--;

}

_P3_OUT->_BIT.b3=0;

_P3_OUT->_BIT.b3=1;

}

void Delay(unsigned int Value)// Hm Delay {



}Bi 2: Hin th ch MSP 430 SPKT TPHCM trn 2 dng bng cch dng mng:

Lu :

Kt ni phn cng:

+ Ni chn 10 eZ430-RF2500T iu khin chn E ca LCD.

+ Ni chn 8 ca eZ430-RF2500T iu khin chn RW ca LCD.

+ Ni chn 6 ca eZ430-RF2500T iu khin chn RS ca LCD.

+ Kt ni 8 bit sau ca tng m rng th nht vi 8 ng d liu LCD.Chng trnh:#include "msp430x22x4.h


void MoRongP1(volatile unsigned int a);

void DKLCD();

// Khai bo hm iu khin LCDvoid DLLCD();

// Khai bo hm ghi d liu LCDunion reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};







volatile unsigned char ChuLCD1[]={'M','C','U',' ','4','3','0'}; // Mng ch dng 1volatile unsigned char ChuLCD2[]={'S','P','K','T',' ','T','P','H','C','M'}; // Mng ch dng 2volatile unsigned int n,m;int main(void)

// Chong trnh chnh {





MoRongP1(0x00);

Delay(500);

MoRongP1(0x01);// Lnh xo mn hnh

DKLCD();

MoRongP1(0x38);// Cho php hin 2 dng DKLCD();

MoRongP1(0x0C);// Tt con tr DKLCD();

MoRongP1(0x84);// Hin MCU 430 dng 1 ct 4 DKLCD();

for(n=0;n_BIT.b3=1;

_P4_OUT->_BIT.b5=0;

Delay(50);

_P4_OUT->_BIT.b5=1;

Delay(5);

}

void DLLCD()

// Hm ghi d liu LCD {

_P2_OUT->_BIT.b3=0;

_P4_OUT->_BIT.b3=1;

_P4_OUT->_BIT.b5=0;

Delay(50);

_P4_OUT->_BIT.b5=1;

Delay(5);

}void MoRongP1(unsigned int a)// Hm m rng tng th 1 {

volatile unsigned int b,c,d;

b=0x8000;

c=16;

while(c>0)

{

d = a&b;

if ( d == b)

{

_P3_OUT->_BIT.b1=0;

}

else

{

_P3_OUT->_BIT.b1=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

b=b>>1;

c--;

}

_P3_OUT->_BIT.b3=0;

_P3_OUT->_BIT.b3=1;

}

void Delay(unsigned int Value)// Hm Delay {



}3.4.6 Cc bi tp v Led ma trn:Bi 1: Hin ch A bng phng php lit kLu :

Kt ni phn cng:+ Kt ni 8 bit sau ca knh m rng th 2 vi 8 hng ca Led ma trn.

+ kt ni 8 bit sau ca knh m rng th 3 vi 8 transitor iu khin ct.





union reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};







// Chng trnh chnh {





for(;;) { MoRongP3(0x00);

// Chng lem MoRongP2(0xC1);

// a m vo ct th nht

MoRongP3(0x01);

// Cho php sng ct th nht Delay(100);

// Thi gian qut Led MoRongP3(0x00);

MoRongP2(0xB7);

// a m vo ct th hai

MoRongP3(0x02);

// Cho php sng ct th hai Delay(100);

MoRongP3(0x00);

MoRongP2(0x77);

// a m vo ct th ba MoRongP3(0x04);

// Cho php sng ct th ba Delay(100);

MoRongP3(0x00);

MoRongP2(0xB7);

// a m vo ct th t MoRongP3(0x08);

// Cho php sng ct th t Delay(100);

MoRongP3(0x00);

MoRongP2(0xC1);

// a m vo ct th nm MoRongP3(0x10);

// a m vo ct th nm Delay(100);

MoRongP3(0x00);

}

void MoRongP2(unsigned int e)

// Hm m rng tng 2 {


f=0x8000;

g=16;

while(g>0)

{

h = e&f;

if ( h == f)

{

_P3_OUT->_BIT.b2=0;

}

else

{

_P3_OUT->_BIT.b2=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}


// Hm m rng tng 3 {


j=0x8000;

k=16;

while(k>0)

{

l = i&j;

if ( l == j)

{

_P4_OUT->_BIT.b4=0;

}

else

{

_P4_OUT->_BIT.b4=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

j=j>>1;

k--;

}

_P4_OUT->_BIT.b6=0;

_P4_OUT->_BIT.b6=1;

}


// Hm Delay {



}Bi 2: Hin ch A bng phng php mng

Lu :

Kt ni phn cng:

+ Kt ni 8 bit sau ca knh m rng th 2 vi 8 hng ca Led ma trn.






void HienThi();

union reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};union reg* _P4_DIRECT = (union reg*)0x1E ;






volatile unsigned char matran[]={0xC1,0xB7,0x77,0xB7,0xC1}; // M ma trn ch Aint main(void)

// Chng trnh chnh {





for(;;)

{

bien=0;

m=0x0001;

while(bien_BIT.b2=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}


// Hm m rng port tng 3 {


j=0x8000;

k=16;

while(k>0)

{

l = i&j;

if ( l == j)

{

_P4_OUT->_BIT.b4=0;

}

else

{

_P4_OUT->_BIT.b4=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

j=j>>1;

k--;

}

_P4_OUT->_BIT.b6=0;

_P4_OUT->_BIT.b6=1;

}


// Hm DeLay {



}Bi 3: Hin ch THANH CONG chy t phi sang tri

Lu :Kt ni phn cng:

+ Kt ni 8 bit sau ca knh m rng th 2 vi 8 hng ca Led ma trn.






void HienThi();

union reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};







volatile unsigned char matran[]={0x7F,0x7F,0x01,0x7F,0x7F,0x01,0xEF,0xEF,0xEF,0x01,0xC1,0xB7,0x77,0xB7,0xC1,0x01,0xBF,0xDF,0xEF,0x01,0x01,0xEF,0xEF,0xEF,0x01,0xFF,0xFF,0x83,0X7D,0X7D,0X7D,0XBB,0x83,0X7D,0X7D,0X7D,0X83,0x01,0xBF,0xDF,0xEF,0x01,0x83,0x7D,0x65,0x6D,0xA3,0xFF,0xFF,0x7F,0x7F,0x01,0x7F,0x7F,0x01,0xEF}; //M ma trnTHANHCONGvolatile unsigned int n,p,m;int main(void)

// Chng trnh chnh {





for(;;)

{

n=0;

while(n_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

f=f>>1;

g--;

}

_P3_OUT->_BIT.b0=0;

_P3_OUT->_BIT.b0=1;

}


// Hm m rng Port tng 3 {


j=0x8000;

k=16;

while(k>0)

{

l = i&j;

if ( l == j)

{

_P4_OUT->_BIT.b4=0;

}

else

{

_P4_OUT->_BIT.b4=1;

}

_P2_OUT->_BIT.b4=0;

_P2_OUT->_BIT.b4=1;

j=j>>1;

k--;

}

_P4_OUT->_BIT.b6=0;

_P4_OUT->_BIT.b6=1;

}


//Hm Delay {



}3.4.7 Cc bi tp v nt nhn:Bi 1: Dng P2.2 lm nt nhn. Khi nhn nt nhn th Led P1.0 sng, khng nhn th Led P1.0 tt. Dng P2.3 l ngun 3.5V ca vi iu khin. Lu :

Chng trnh:

#include "msp430x22x4.h"

union reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};



union reg* _P2_IN = (union reg*)0x28 ;

union reg* _P1_DIRECT = (union reg*)0x22 ;


void main(void)

// Chng trnh chnh{


_P1_DIRECT->_BIT.b0 = 1;



// nh ngha P2.2 l ng vo

while (1)

{

_P2_OUT->_BIT.b3 = 1;

// Set P2.3 ln 1

if (1 & _P2_IN->_BIT.b2)

// Kim tra P2.2 nu = 1

{

_P1_OUT->_BIT.b0 = 1; // Set P1.0 = 1

}

else

{

_P1_OUT->_BIT.b0 = 0; // Ngc li P1.0 = 0

}

}

}Bi 2: To 3 nt nhn, Up, Down, ReSet. Nhn Up th bin tng ln 1 v Led P1.0 sng, nhn Down th bin gim i 1 v Led P1.1 sng, nhn Reset bin v 0. Dng P2.3 lm nt nhn Up, dng P2.2 lm nt nhn Down, dng P4.3 lm nt nhn Reset, dng P4.5 l ngun 3.5V ca vi iu khin. Hin th trn 2 Led 7 on.Lu :

Kt ni phn cng:+ Kt ni 8 bit u ca knh m rng th 2 vi 7 on v du chm thp phn ca Led 7 on.

+ Kt ni 8 bit u ca knh m rng th 3 vi 8 transistor iu khin qut Led.Chng trnh:

#include "msp430x22x4.h"

void MoRongP2(unsigned int e);


void HienThi();


union reg {

struct bit {

unsigned char b0:1;

unsigned char b1:1;

unsigned char b2:1;

unsigned char b3:1;

unsigned char b4:1;

unsigned char b5:1;

unsigned char b6:1;

unsigned char b7:1;

}_BIT;


};



union reg* _P4_IN = (union reg*)0x1C ;




union reg* _P2_

co ban ve msp430.doc

Documents