cms fed testing update 28-06-2002 m. noy j. leaver imperial college silicon group
DESCRIPTION
CMS FED Testing Picture of the DAC evaluation board DAC Line driver UTP out LVTTL data in, from level converterTRANSCRIPT
CMS FED TestingUpdate 28-06-2002
M. Noy & J. LeaverImperial College
Silicon Group
CMS FED Testing
Currently:
SEQSI LVDS LVTTLDAC
Evaluation board
UTP
UTP
Opto-Tx
Optical FibreOpto-
Rx
I2C master
I2C control
Coax8 bit oscilloscope
GPIB
VME
PC
LVDSLVTTLLine driver +
(optional) level shift
Network
I2C slave
CMS FED Testing Picture of the DAC evaluation board
DAC
Line driver
UTP out
LVTTL data in, from level
converter
CMS FED Testing Picture of the key link components
Opto-Tx Opto-Rx
I2Ccable
Single ended output
to scope
UTP from DAC/line
driver
Optical fibre
CMS FED Testing
DAC
scope
UTPUTP
Vout
Opto-TxDAC Evaluation Board Line driver
Opto-Rx
101110110101
CMS FED TestingSignal before the link
200mV (V+-V- =400mV ) differential signal with no offset.higher bandwidth ringing and faster rise/fall time.Time scale is relative to the scope trigger point on all plots.
CMS FED TestingSignal after the link
Single ended, with offset.No ringing but slower rise/fall times
CMS FED Testing
Signal noise/jitter after the link
Note:no scale on the width of the line. This is an impression of the infinite persistence scope trace => spread unknown. (Measurements are real).
CMS FED TestingRise time, 10% to 90% of full scale.
CMS FED TestingFall time 90% to 10% of full scale
CMS FED TestingLinearity: link is being operated in the linear region of the Tx/Rx
Settings: x0, x1, x2, x3, x4, x5=0,0,0,0,1 (recommended by CERN)
000 01
CMS FED TestingSample APV25 pair of multiplexed frames with simulated 1 MIP signal
CMS FED TestingMultiplexed APV25 header with zero pipeline address
6 start bitspipeline
address (16 bits)2 error
bits2x12x25ns bits =
CMS FED TestingZoom in of the 1 MIP signal upon its pedestal
Approx:
Pedestal value here is 509 lsbs, 4096 levels in 405mV0.099mV/lsb
1 MIP 4096/8=512 lsbs
Total signal=570+(405/4096)*(509+512)=570+0.099*1021=671mV
We attached a heating element and a thermocouple to the laser package and used the following PID equation to stabilise the temperature through a feedback loop.
W = P [ (Ts - T0) + D d (Ts- T0) /dt + I (Ts - T0)dt]
The temperature was varied between 30ºC and 40ºC in ~1ºC steps. The output of the Rx was recorded after a stabilisation time, for some measurement time.
CMS FED TestingTemperature Control
Laser threshold bias current behaves like
Ith=I0exp(T/T0)Which implies
IthIth T/T0
And (after a few lines and other things!)
Vout -Reff G Rx l Ith T/T0
Typical parameter values yield an expected (@ 34.1°C)
Vout/T -90.8 mV/°C
CMS FED TestingTemperature Measurements
CMS FED TestingTemperature Measurement Results
Approximated with a linear fit V=mT+C
Where m = -(89.8 1.8) mV/°C
and C = (4137 62) mV
Good agreement with expected value (of
90.8mV/°C), but some of the parameters are loosely
defined
Temperature stabilisation is good, with random fluctuations of the order 0.02°C. There is some unknown systematic error, that does not exceed 0.44°C.
Have statistics of 150x500 voltage points and 150 temperature points per temperature setting.
Statistical errors are too small to account for the largest random deviation, probably spurious.
We could repeat the whole measurement again using smaller T steps, but probably won’t due to time constraints.
CMS FED TestingTemperature Measurement Errors
CMS FED TestingSummary
Have a complete working single fibre, possible to drive 4 with identical signals using the current Opto-Tx.
Possible to obtain a further 2 of the 4 channel prototypes from CERN complete 12 channels could in principle be driven with identical signals.
Dependence of laser operation on temperature is now better understood, and fine temperature control is possible. We feel confident that a system such as the one we have will allow sufficient temperature stability for the fed testing needs.
Work is in progress to produce an application specific version of the SEQSIsimpler operationlonger RAM pipelineclean/synchronous stop from VMEpossible stepping through
Future Work
Have 1 (untested) Opto-Rx emulator to drive the analogue stage of the FED directly over copper (I.e. eliminating the optical link)
Verify DAC Linearity: Summer student(?)
More thought into a test vectors and their comparison with the FED output
CMS FED Testing