cmos op-amp power optimization in all regions of inversion using geometric programming pablo aguirre...
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CMOS Op-Amp Power Optimization in All Regions of Inversion Using Geometric Programming
Pablo Aguirre and Fernando SilveiraIIE – FING
Universidad de la RepúblicaMontevideo, Uruguay.
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Outline
IntroductionGeometric Programming (GP) and the
gm/ID ratioRelaxed GPProof of concept: The intrinsic AmplifierDesign Example: The Miller AmplifierConclusions
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Introduction
Automatic analog circuit synthesis: since 1980's Broad classification of techniques: Simulation-based or
Equation-based. Optimization methods: we want to assure a global
optimum. Three main methods: Branch and bound (B&B), Simulated annealing (SA) and
Convex optimization B&B and SA: slow, computational effort grows exponentially
with problem size. SA does not guarantee global optimum in practice.
Convex optimization: Pros: extremely efficient, can cope with 100’s of vars. and 1000’s
of constraints in seconds. Cons: Eqs. must be formulated in posynomial form.
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GP and the gm/ID ratio
GP Problem:
Monomials:
Posynomials:
x: vector real positive varsc,c
k: ≥0; a
ik real
GP problems can be cast into convex form. Therefore, convex optimization methods guarantee a global solution or will unambiguosly detect that the GP problem is unfeasible.
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GP and the gm/ID ratio
ACM [Cu98]:
Inv. coeff:
gm/ID ratio: KEY PARAMETER IN ANY ANALOG DESIGN
Present on most measurements of analog performance [Si04]:
•Gain•Speed•Noise•Offset
• …
The larger the gm/ID ratio, the more power efficient the transistor is [Si96].
Power efficiency
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GP and the gm/ID ratio
Posynomial equality: NOT VALID IN GP
CONVEXSET
CONCAVESET
(≤ 1)
(≥ 1)
Let’s pose the relation between gm/ID ratio and if as a posynomial:
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Where are we? Where are we heading?
Prior ART: Hershenson et al. [He01] and Mandal et al. [Ma01]: First
report on GP applied to analog CMOS design. STRONG INVERSION ONLY MODELS, therefore not true global optimum.
Brodersen et al. [Va04]: GP on all regions. Uses branch and bound algorithm on top of GP. Looses the computational efficiency of GP.
This work: We look for an efficient solution to the posynomial equality of the gm/ID ratio in the case of POWER OPTIMIZATION.
This problem is intrinsic to the physics of the MOS transistor. Does not depends on the model used.
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Relaxed GP
Original Problem:
Global optimum: xs
if hi(xs)=1 for all i, then xs is also an optimum for the original GP
monomials
posynomials
Relaxed GP:
ValidNot valid
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Relaxed GP
What does this mean?• Algorthim side: We relaxed the
original GP, now we can solve it as any other GP.
• Circuit side: We artifically increased the set of feasible transistors (shaded area).
How do we use this on our problem?
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Relaxed GP
How do I know that a power optimization algorithm will not use transistors that don’t really exist?
Because we know that the larger the gm/ID ratio, the more power efficient a transistor will be.Therefore, it is reasonable to assume that the power optimization will always find its solution on the curve
How do we use this on our problem?
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Proof of Concept: The Intrinsic Amplifier
The most simple amplifier We don’t need GP to solve it,
but its simplicity gives a clear picture on how the idea works.
Goal: Synthesize an intrinsic amp. with optimal power consumption that complies with a GBW constraint for a given CL.
Design eqs.:
Design vars.: ID, W, L, if, gm/ID
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Proof of Concept: The Intrinsic Amplifier
Synthesis results for 4 different cases.
GP assures that these solutions are the global optimal solutions to the relaxed problem.
They all comply with the gm/ID ratio equality constraint (they are on the curve).
Therefore, these solutions are also the global optimal solutions to the original problem: Those are real transistors, we are done.
Are these four cases just a coincidence?
CL=1pF
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The Intrinsic Amplifier: Method Scope
Are these four cases just a coincidence? No, formal proof on the paper.
Which is the scope of this approach? Power consumption dictated by gm requirements.
Out of scope example: Consumption imposed by Slew-rate
In these cases: The exception is easily noticed. Increasing the computational effort and complexity around the
initial non-valid solution, we can find a valid global optimum. Ex.: Branch and bound [Va04], Tightening [Bo05].
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Design Example: The Miller Amplifier
Two stage Miller Amplifier
Goal: Optimize power consumption for a given GBW, PM and CL
Other constrains included: Gain, Output swing, Area, etc.
Hershenson [He01] deeply analize how to pose all the equations in monomial/posynomial form.
We used expressions valid in all regions of operation (e.g. intrinsic capacitances).
Design variables:W1,W2,W3, W4, W5=W6, L1, L2, L3, L4=L5=L6, ID1, ID2, (gm/ID)1, (gm/ID)2=3, if1, if2=if3, if4=if5=if6, Cm
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Design Example: The Miller Amplifier
Two relaxed constraints: (gm/ID)1 and (gm/ID)2
All the solutions on the curve, i.e. the idea works in more complex designs.
Most optimums on moderate inversion: Expected result. Nevertheless it is important to confirm the need for a model valid in all regions of inversion.
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Conclusions
GP applied in CMOS power optimization with true (all regions) global optimum.
Posynomial characteristic of the gm/ID curve efficiently handled.
This work confirms that power optimums usually lie on moderate inversion region.
Future work: Work on the exceptions to handle them efficiently. Inclusion of short channel effects (this work: long
channel models only).
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Acknowledgments
PDT - Programa de Desarrollo Tecnológico - Uruguay
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References
[He01] M. Hershenson, S. Boyd, and T. Lee, “Optimal design of a cmos op-amp via geometric programming," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 1, pp. 1-21, Jan. 2001.
[Ma01] P. Mandal and V. Visvanathan, “Cmos op-amp sizing using a geometric programming formulation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 1, pp. 22-38, Jan. 2001.
[Va04] J. Vanderhaegen and R. Brodersen, “Automated design of operational transconductance ampliers using reversed geometric programming," in Proceedings on 41st Design Automation Conference, vol. I, Jun. 2004, pp. 133-138.
[Si96] F. Silveira, D. Flandre, and P. G. Jespers, “A (gm/ID) based methodology for the design of cmos analog ircuits and its application to the synthesis of a silicon-on-insulator micropower OTA," IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1314-1319, Sep. 1996.
[Cu98] A. Cunha, M. Schneider, and C. Galup-Montoro, “An MOS transisotr model for analog circuit design," IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
[Bo05] S. Boyd, S. J. Kim, L. Vandenberghe, and A. Hassibi, “A tutorial on geometric programming," Stanford University and University of California Los Angeles, Tech. Rep., 2005. [Online]. Available: http://www.stanford.edu/~boyd/gptutorial.html
[Si04] F. Silveira and D. Flandre, Low Power Analog CMOS for Cardiac Pacemakers Design and Optimization in Bulk and SOI Technologies, ser. The Kluwer International Series In Engineering And Computer Science. Boston: Kluwer Academic Publishers, Jan. 2004, vol. 758, ISBN 1-4020-7719-X.
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CMOS Op-Amp Power Optimization in All Regions of Inversion Using Geometric Programming
Pablo Aguirre and Fernando SilveiraIIE – FING
Universidad de la RepúblicaMontevideo, Uruguay.