cmos leakage reduction using laser spike annealing · 3 avs west coast junction technology group...

1 AVS West Coast Junction Technology Group Meeting July 16, 2009

CMOS Leakage Reduction using Laser Spike Annealing

Presented by: Jeff Hebb, Ph.D.

Contributors: David Owen, Yun Wang, Shrinivas Shetty, Van Le,

Shaoyin Chen, Andy Hawryluk

Ultratech, Inc.

July 17, 2009


Outline

•Introduction

•Advantages of high annealing temperatures

•HK+MG

•Role of stress for advanced CMOS

•Extendibility to alternate device structures


LSA System Architecture

System is designed to minimize within-die and within-wafer variations

Hot chuck

x-y stage

Emission

Detector

CO2 Laser

λλλλ = 10.6um

Reflective

Optics

Control

AlgorithmTemperature

Conversion

10kHz

P-polarized

LSA Key Attributes

1. Within-die uniformity

•Long wavelength,

•p-polarized

•Brewster angle

2. Wafer-to-wafer repeatability

•Temperature feedback control

3. Low stress

•Flexible dwell time

•Effective stress dissiptaion


Performance (Speed)

Cell

phone

Desktop

PC

Laptop

PC

NetbookSmartphone

SmartbookFeature

phone

Leakage and Power Requirements for Advanced Devices

Key Highlights

•Trends toward multi-media

“connected” devices have

placed unprecedented

demands on simultaneous

power and leakage

•Leakage reduction is

critical for:

• Battery life

• Cooling requirements

Le

ak

ag

e

Low High

Lo

wH

igh


Laser Spike Annealing for USJ Formation

• Thinner Tox_inv due to reduced

poly depletion

• Improved Id due to reduced series

resistance

• Reduced SCE due to ultra-shallow

junction

• Multiple steps being used to

maximize gains from LSA

• Tradeoff’s between leakage and

speed by reverse oxide scaling,

junction re-optimization, etc

Dopant profile

control

Gate Activation

Poly Depletion Reduction

USJ

Formation

SD Rs

reduction


Outline

•Introduction


•HK+MG




Higher temperatures of LSA gives lower leakage

• Typically, an increase in LSA peak temperature of 100C reduces leakage by 2-5X, depending on device integration (e.g, Adachi et al. Toshiba, IEDM 2005).

Ioff

Ion

No LSA LSA To

LSA, To+100C

0.0%

2.0%

4.0%

6.0%

8.0%

10.0%

1150 1200 1250 1300

LSA Process Temperature (oC)

Ion

gain

@ c

on

sta

nt

Ioff

NMOS Ion gain over RTA baseline1

TI Data (Chen et al., RTP2007)

2-5x leakage

reduction


Multiple LSA steps for leakage reduction

Isolation

Gate Ox

Gate Formation

S/D Extension & Halo

SW Spacer Formation

SMT Process

Deep S/D Implantation

S/D spike RTA

Ni Silicidation

BEOL Process

Device Flow

Possible

LSA

Insertion

Points:

Multiple LSA steps is mainstream for advanced nodes

PMOS leakage reduction of 3-4X

using two-step LSA (Fujitsu, IEDM

2007)


Vt Variability & Leakage Reduction For Low Power Application (Samsung Results)

Reduced leakage

distribution

Lower Vt

variability

Improved ring

oscillator

performance

H. Lee et al, Samsung, IEDM2008

LSA/Implant optimization gives leakage reduction and improved uniformity


Outline

•Introduction


•HK+MG




LSA Compatibility with High K + Metal Gate

10X Leakage

Reduction

Transistor Delay

Leakag

e

•LSA demonstrated to be compatible with “gate first” HK+MG integration

•Pattern suppression still effective for HK+MG due to small thickness of

metal gate

0

0.2

0.4

0.6

0.8

1

1.2

0 10 20 30

Reflectance (%)

Pro

ba

bility D

en

sity

LSA w/o

Hi-k/Met

LSA w/i

Hi-k/Met

Lamp w/o

Hi-k/Met

Map of Die

Reflectance with LSA

Gate first process with LSA

LSA

Lamp

X. Chen et al., IBM, VLSI 2008


High-k Morphology & Leakage Improvement

*source: D.H. Triyoso, to be published in APL

(b) Leakage characteristics

RTA 1000C 5s

LSA 1325C,

0.8ms

(a) AFM morphology


Outline

•Introduction


•HK+MG




Wafer Stress in LSA

Side view - Wafer held flat on vacuum chuck

scan

θθθθ

LSA

Top view: Simulated stress during LSA. Less

than 5% of the wafer area is stressed

Temperature gradients•Minimal pattern effects give uniform

stress

Stress dissipation•Stress is localized - minimizes

thermal shock.

•Stress is dissipated by rest of the

wafer and to wafer chuck

Dwell time• Dwell time flexibility allows low

wafer warpage for critical process

steps


0

0.02

0.04

Overlay Error (µm)

Dwell Time

RMS X Error

RMS Y Error

No LSA

400µs

800µs

Relationship Between Stress & Overlay

Overlay requirements

becoming tighter at advanced

nodes

Shetty et al (Ultratech & TI), IWJT2009

45nm 32nm 22nm65nm 15nm

ITRS Roadmap

• LSA dwell time flexibility critical for compatibility with e-SiGe at sub-65nm

• Same principles apply for Si:C for sub-32nm


Low Dwell Time for Overlay Improvement

• Dislocation formation scales exponentially with T and t1/2, so reducing time is beneficial

for reducing overlay errors

• Dislocation formation will become more severe as Ge concentration is increased

Warpage & stress are reduced at low dwell times

−∝

kT

EN

dt

tdN an

eff exp)(

0τ

(*Houghton, et al, JAP 1991)

0

100

200

300

400

0 1 2 3

Mo

bil

ity

(c

m2/V

·s)

90nm 65nm 45nm 32nm

Stress (GPa)

*S. Thompson VLSI’06

17%

23%

30% Ge


Overview of Coherent Gradient Sensing System

• Measurement technology: Lateral shearing interferometer

� >700,000 points (310 µµµµm per pixel)

� Rapid image capture, no scanning

• Analysis and algorithms� Full analysis in less than 2 minutes

� Full wafer stress variations can be correlated to die-level issues

3


• Coherent Gradient Sensing (CGS) system used to measure wafer level stress at 16 process points in a 65nm DSP process flow

• Measurement points span ~120 process steps from wafer start through source-drain anneal

• Within-wafer and wafer-to-wafer stress variations were characterized

for each process or set of processes

• Correlations between electrical parameters & stress were explored

• Parameters: PMOS & NMOS drive current, leakage current, drain current and threshold voltage

• Data used to identify which process steps and stress metrics to which electrical performance is most sensitive

Stress Fingerprinting and Correlation to Leakage


-40

-20

0

20

40

60

Process-induced Bow ( µµ µµm)

Bow X

Bow Y

0372 0372 0374 0897 1222 1360 2457 2457 2657 2657 2984 2984 3087 3087 3222 32221 32 5 6 8 10 12 14 164 7 9 11 13 15

Stress fingerprinting resultsFingerprinting: Measuring stress & deformation across multiple steps in line

Liner Ox

Gate Ox 1

Damage anneal

Poly Anneal

LSA 1

Process Flow SequenceWafer Start S/D Anneal

LSA 2

LSA 3

LSA 4

Gate Ox 2

Implant

LSA steps do not add

significant stress


Correlation of stress to leakage current

PMOS NMOS

• There is a significant correlation between wafer level stress and leakage

• Most of the leakage variation is due to within-wafer stress variations

• Low stress of LSA does not contribute significantly to stress correlated

leakage

All Points, All Wafers, All Steps

Stress variations

account for 41% of

leakage variance

Stress variations

account for 50% of

NMOS leakage variance

Log

Log


PMOS IOFF: Within Wafer Variation

• Data for each die location represents the average of all 24 wafers in lot

• Within wafer stress variations correspond to leakage current variations

Within-Wafer Variation of Stress

(Multiple Steps)

Within-Wafer Variation of

Leakage Current

Log

Log


Outline

•Introduction


•HK+MG




LSA Application To UTSOI

-300 -250 400 500 600 700100n

1µ

10µ

100n

1µ

10µ

~8%

Increase

~30% Increase

RTA only

RTA+LSA

I off [

A/µ

m]

Ieff

[A/µm]

UTSOI

IBM Alliance, VLSI-TSA 2006

LSA gives 30% enhancement in Ieff & 10% improvement in RO speed for UTSOI


Compatibility With Non-Planar Structures

High aspect ratio fins

Laser

• Shadowing effects?

• Thin Si fin is transparent to

CO2 wavelength, no

shadowing effects

• Scattering effects?

• Height is still << 10.6um, so

scattering is minimal for LSA

Total Integrated Scattering:

24

≈=

λ

πσ

i

s

RP

PTIS

σ is rms surface roughness

• Long wavelength reduces total amount of scattering

0

0.05

0.1

0.15

0.2

0.25

0.01 0.1 1 10 100

Scattering (%)

No

rmalized

Co

un

ts

10.6um

0.8um

>100X


Summary

• Market trends create stringent requirements for simultaneous

high performance and low leakage for advanced CMOS

• LSA tool architecture has inherent advantages for achieving

high anneal temperatures, which can be used to reduce leakage

• LSA is compatible with HK+MG because pattern suppression

extends to thin metal layers

• LSA has inherent advantages for low stress which make it

compatible with strain engineering techniques, and may reduce

leakage correlated with wafer-level stress

• LSA is compatible with transistor architectures that may be

used at 22nm

cmos leakage reduction using laser spike annealing · 3 avs west coast junction technology group...

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