cmos imaging technology for space science applications · gate. Φ . flush. v. ref. Φ. sel. Φ....

Pain,Cunningham,, Stirbl,Hancock, Wrigley, Ringold, et. al2002JPL Proprietary

CMOS Imaging Technology for CMOS Imaging Technology for Space Science Applications

Bedabrata Bedabrata Pain, Thomas Cunningham, Pain, Thomas Cunningham, Suresh Suresh SeshadriSeshadri, Robert , Robert StirblStirbl

Jet Propulsion LaboratoryCalifornia Institute of Technology

[email protected]

Space Science Applications

Innovative Designs for the Next Large Aperture Optical/UV TelescopeNHST Workshop, STScI, Baltimore

April 10-11, 2003


MONOLITHIC CMOS APS CAMERA-ON-A-CHIP

n-well

p-well

Vdd

RSTSFin

p- epi(lower doping)

n+ n+

GND

p-welln+p+

Depletion region

Undepleted region

PixelArray

AnalogOutputBuffer

Digital OutputBufferAnalog to Digital

Converter (ADC)

RowDriver

Column Signal Chain

Timing & Control

Processor

Inpu

t int

erfa

ce

cont

rolle

r

Low power, miniature, miniatureLow NoiseRandom Access capability Ease of operation and integration

Single-chip imager: “ digital camera-on-a-chip”

Standard single power supply

Best-suited for ultra-large format imagingIntegration with support circuitsNoise does not increase with data rate

More radiation tolerant: > 10 Mrad.(Si); 2x1012 protons/cm2

(p-channel CCD – 40x increase in CTI at 2x109

p/cm2)

Reliability and cost: leverage from multi-billion dollar VLSI industry

PIXEL CROSS-SECTION

Charge to voltage conversion in each pixelCharge to voltage conversion in each pixel


MINIATURIZATION & SMARTNESS w/APS

>3 W

~ 20 mW

First Wireless digital camera

DRV camera

Miniaturized Sun-sensor

Miniature camera head Miniature star-tracker

Field-deployable Bio-sensors

First Single-chip digital camera


WHAT MATTERS

@ > 1 MHz, Circuit techniques<1 eNoise

digitization; move support electronics close to detector> 1 MHzData rate

Higher operating temp; circuitNoneImage persistence

~ 100 krad, Reduce field inversion< 0.001 e/sDark rate

after radiation

Reduce device thickness, circuitsHighSEU

tolerance

CMOS should have advantage~ 1x1012

p/cm2Proton tolerance

ImplantsHighLinearity

Passivation implants, increase operating temp.< 0.001 e/sDark rate

Cross-section engineeringGeometric limitedMTF

Reverse-illumination>80%QE

Non-planar architecture1 billionFormat

n-well p-well

Vdd

RST

GND

SFin

p- epi

n+ n+ p+

p+ substrate

Improved linearity

Leakage and QE

QE, Cross-talk

Dark current

Dynamic Range

QE

Radiation hardness


STRATEGIC ALLIANCE with AGILENT

Align with VLSI technology developmentAlign with VLSI technology development• Build devices with tools and

techniques universally used• Make necessary changes to the CMOS

process for scientific imaging

• Largest CMOS Supplier• Dedicated fab. Facility • AMOS Family for Image

Sensor (0.35um, 0.25um)• Adding 3 implants for dark rate

reduction and improved radiation tolerance(layout + dose + energy)

• Provides access to a commercial foundry to make appropriate modifications

Agilent

Hynix

Micron

OmniVision

Sharp

Others

Source: Nikkei Electronics (11 March 2002)


HIGH PERFORMANCE MEGAPIXEL IMAGER

0

0.2

0.4

0.6

0.8

1

1.2

0 0.5 1 1.5 2pitch*fsig

MTF

500nm800nmgeometric

Excellent MTF

n-well p-well

Vdd

RST

GND

SFin

p- epi

n+ n+ p+

p+ substrate

Low-doped for high QE, low cross-talk

New Pixel cross-section for improved performance

0

10

20

30

40

50

60

2s CDS 4s gnd-CDS 4s int-CDS HTS Hard reset

Noi

se

Random (e)

FPN (e)

Ultra-low noise with CDS


NOISE REDUCTION

• CDS not very suited for multiplexed detectors (e.g CMOS, IR …) because of the flicker noise and system drifts

• Feedback used to suppress kTC• Minimal impact on fill-factor

Requires only one extra transistor per pixel

• Maintains high full-well (> 200 ke)• Fully compatible with 2-D visible/IR

imager implementation• Noise constant with readout bandwidth

Towards < 1 e- read noisekTC noise is no longer the

“fundamental limit”

Pixel

APS pixel

opampReference

shaper

Conceptual Diagram


Feedback Reset Pixel

-

+

Msf

Mrst

Mact

Msel

Mflush

Mdrop

Mload

Vcol

Vpd

Vfbk

Vload

Vdd-array

AVdd

ColumnAmplifier

Transmissiongate

Φflush

Vref

Φsel

Φfbk

PIXEL

Vout

0.01

0.1

1

1.E-01 1.E+01 1.E+03 1.E+05 1.E+07 1.E+09Gain (dB)

Noi

se (N

orm

. to

kTC

)

1050100100010501001000

Dotted line: Cin=100 fFSolid line: Cin=10fF

0

10

20

30

40

50

60

5 10 15 20

Conversion Gain (uV/e)

Noi

se (e

)

w/o feedback

with feedback

SIMULATED

MEASURED


REVERSE-ILLUMINATED APS

Improving Quantum Efficiency and MTF

Passivation implant

Si-epitaxial layer (fully depleted; 10 µm)

Implanted region (pixel circuitry)Implanted region (on-chip electronics)

Si-substrate (heavily doped)

FRONT SIDE

Additional implant

Thinned megapixel imager

Frame-thinning• Mechanical stability (no warping or

wrinkling)• Separate imager performance from

support electronics

Thinning carried out by S.Nikzad & T. Jones


OTHER TECHNOLOGY: NOVEL SOI IMAGER

•Pixel in handle-wafer, readout in SOI (isolates sensor from circuit)•Not only enables SOI imager, but vastly enhances performance•Planar architecture reduces dark rate and enables more radiationhardness•Reduced substrate noise due to decoupling via BOX: suitable for high-speed operation•Better spectral coverage through independent handle-wafer doping•Ideally suited to vertical integration

p-

FETs Column-bus

RST SELGnd

n++n p+

p-

p++

One pixel

With Mike Wood,With Mike Wood, SpawarSpawar, San Diego, San Diego


MEASURED QE

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

300 400 500 600 700 800 900 1000 1100Wavelength (nm)

QE

•Front-illuminated (>80% fill-factor)•25 µm pixel•No anti-reflection coating (goes through thin silicon and thin buried oxide)•Modeled by a 300 mm wafer doped at 1x1013/cm3; with 20 µm depletion width

JPL Proprietary


RADIATION HARDENING SOI

-13

-12

-11

-10

-09

-08

-07

-06

-05

-04

-03

-02

-1 -0.5 0 0.5 1 1.5 2VGATE (V)

PRERAD

EDGELESSDEVICE

1 Mrad

MULTI-EDGEDEVICE

MULTI-EDGE(40 mesas - 80 edges)

EDGELESS

FIELD

MESA

POLY

BTS

DRAIN

SOURCE

DRAIN

SOURCE

Log

I DR

AIN

(A)

SILICON SUBSTRATE

BURIED OXIDE

MESA ISLAND

P+ BODY TIE-TO-SOURCE (BTS)to control floating body

N+ SOURCE

POLY GATE

N+ DRAIN

BTS

No channel at mesa edge

• Easily hardened• Excellent immunity to

high energy events


RAD-HARD IMAGER RESULTS

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

400 500 600 700 800 900 1000 1100

Wavelength (nm)

Med

ian

Spe

ctra

l Res

pons

e (u

V/p

h)

Pre-Rad0.5 Mrad1Mrad1.5 Mrad

Response Unchanged after radiation

5.5 Mrad Total Dose Proton dose 63 MeV RT @ 2x1012 P/cm2

With BAE Systems, Manassas–Response unchanged with dose–Well-behaved dark-current behavior–Unbiased to 5.5 Mrad(Si)–In-situ to 1.5 Mrad(Si)–No bias effects–No adjustments over temp. or dose–Minimal dependence of responsivity on dose–Minimal change in dark current with Protons 0

1

2

3

4

5

6

7

8

9

10

0 250 500 750 1000 1250 1500

Total dose (krad)

Dark

Rat

e (n

A/cm

2)

UnbiasedBiased

~ 5 pA/cm2/krad


APS IN RADIATION ENVIRONMENTEc

Ev

Eact

e-

h+

Tunneling

Trap release

Eliminate Field-Enhanced Leakage

•• No Charge transferNo Charge transfer: CTE degradation eliminated

•• Thin OxideThin Oxide: oxide charge trapping and threshold shift minimized

•• Main ProblemMain Problem: Dark Current Rise under Radiation; Interface Traps in Electric Field

•• FieldField--InversionInversion: Device Isolation Dependent

•• Good SEU PerformanceGood SEU Performance: Thinner epi-layer; use SOI

•• High Proton Immunity:High Proton Immunity: less sensitive to bulk damage

•• Minimal modification of process is Minimal modification of process is required

1

10

100

1000

10000

100000

-4 -2 0 2 4 6 8Normalized dark rate

# of

pix

els

Rayleigh + Exponential

required


ULF IMAGER VIA VERTICAL INTEGRATION

Thru' SiInterconnect

PWB (only for datarouting)

Imager pixels

Chip metallization

Illumination

Back-ill. Imager chip

Wafer-to-waferbonding

chip dielectric

chip dielectric

companionchip

Illumination

• ULF imagers will require dead-space free mosaicing Vertical Integration• Reliability, cost, thermal management are major issues• CMOS more suited for ULF imaging

• noise does not scale up with data rate (< 2 e read noise at 10 MHz possible)• low-power suitable for efficient thermal management• small pixel size• Integration of support electronics is important

• Vertical Integration requires new technology and architecture• Block-parallel architecture• Wafer-to-wafer bonding

•Format: 1 billion pixels•Update rate: > 1 Hz•Noise: < 5 electrons


VERTICAL INTEGRATION APPROACH• Remain close to VLSI processing in

order to maximize reliability and reduce cost

• Wafer-to-wafer bonding through low-temperature oxide bonding

• Block-parallel architecture: Efficient data extraction + minimize interconnect density

• Power doesn’t scale with # of pixels (no standby power): gigapixel @ 200 mW

• No compromise of performance

Vertical Integration

Imager chip Companion chip

Top view

64x64

2Kx2K


High Speed Photon-Counting

Use photocathode + MCP coupled to event-driven focal-plane arrayIncrease global and local count rates (> 1 million counts per sec):Use specialized random-access capability:

•detect and generate address from the area of interest•fast readout of pixels that have been hit

A B C

Fiber taper

ToCentroider

MCP Intensifier

ADC

Event drivenAPSPhosphor

MCPs

PIXELARRAY

AnalogReadout

5

10

Analog Out5 differential

Analog samplingcapacitors

Analog cross-bar switchColumn scan logic

Column comparators

Priority Encoder

Disable latch-set

Digital cross-bar switch

Column address gen. logic

Column decoder

Row

comparators

Priority Encoder

Disable latch

Row

address gen. logic

Row

decoder

Row

rst + scan logic

FIFO

State Machine

PI: Randy Kimble, GSFC


Roadmap?

Component Tech.

2000 2005 2010.

QE>90

RN<1

DN<1

2Kx2K

D2Kx2K

LF Intg. Imagers

ULF Technology > 1Gig

cmos imaging technology for space science applications · gate. Φ . flush. v. ref. Φ. sel. Φ....

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