cmos devices and rf building blocks - 東京工業大学 … and circuits...2004.11.11 titech, a....

2004.11.11 Titech, A. Matsuzawa 1

CMOS Devices and RF Building Blocks

Akira Matsuzawa

Tokyo Institute of Technology

Design of CMOS RF Circuits


Contents

• Building blocks in RF systemand basic performances

• MOS Device characteristics in RF application• Basic RF CMOS circuit design

– Low noise amplifier– Mixer– Oscillator

• Future device trend• Summary


Current status of RF CMOS chip

• Current products– Bluetooth: 2.4GHz, CSR etc., major– Wireless LAN: 5GHz, Atheros etc., major– CDMA : 0.9GHz-1.9GHz, Qualcomm, becomes major– Zigbee: 2.4GHz, not yet, however must use CMOS– TAG: 2.4GHz, Hitachi etc., major

Major Cellular phone standard uses SiGe-BiCMOS technology

RF CMOS was an university research theme, however currently becomes a major technology in the world of wireless.


Why CMOS?

• Low cost– Must be the biggest motivation– CMOS is 30-40% lower than Bi-CMOS

• High level system integration– CMOS is one or two generation advanced– CMOS can realize the full system integration

• Stable supply and multi-foundries– Fabs for SiGe-BiCMOS are very limited.

Slow price decrease and limited product capability• Easy to use

– Universities and start-up companies can use CMOS with low usage fee, but SiGe is difficult to use such programs.


Building blocks in RF systemand basic performances


Basic RF circuit block

Receiver

Transmitter

ImpedanceMatching

1)LowNoiseAmp. 2) Mixer

3) Oscillator

PowerAmp.

Filter

RF systems are composed of limited circuits blocks.LNA, Mixer, and Oscillator will be discussed in my talk.


Basic functions of RF building blocks

Log (f) Log (f)

dB dB1) Amplifier3) Filter

Down conversion

Up conversion

2) Mixer+ Oscillator

Desired

Undesired

Amplifier, frequency converter (mixer +oscillator), and filerare basic function blocks in RF system.

Frequency conversion


RF Amplifier

• Gain: Amplify small signal or generate large signal.• Noise: Smaller noise and larger SNR.• Linearity: Smaller non-linearity.

Non-linearity generates undesired frequency components.

.....)()()()( +++= tvtvtvtv inininout3

32

21 ααα

( ) ( )( ) ( ) ( ) ( )( ) ( )( )tttttt 2121212

21 222 ωωωωωωωω ++−+++=+ coscoscoscoscoscos

( ) ( )( ) ( )( ) ( )( ) ....coscoscoscos +−+−=+ tttt 12213

21 2212

21 ωωωωωω


Input and output characteristics

Pout

Pin

OIP3

IIP3

IP3

1dBPout(1dB)

Fundamental IMD3

Slope=1Slope=3

SNR minSNR min

SFDRBDR

NoiseFloor

NoiseFloor

SFDR

MDSCP1dB

Distortion and noise are important factors in RF amplifier, as well as power and gain.


Dynamic range

BWNFdBmFloorNoise log10174 ++−=

( ) minSNRFloorNoiseIIPSFDR −−= 332

SFDR: Spurious free dynamic rangeThe input power range over which third order inter-modulation productsare below the minimum detectable signal level.

BDR: Blocking dynamic range

kT limitation Bandwidth

MDS: Minimum detectable signal level= Noise Floor +SNRmin

minSNRFloorNoisePBDR dB −−= 1


InO

ut

)()()()( txtxtxty 33

221 ααα ++≈

x(t)=Acosωt

( ) ( )

tAtAtAAA

ttAtAtA

tAtAtAty

ωαωαωααα

ωωαωαωα

ωαωαωα

34

224

32

334

212

33

22

33

1

22

33

22

1

333

2221

coscoscos

coscoscoscos

coscoscos)(

++⎟⎟⎠

⎞⎜⎜⎝

⎛++=

++++=

++=

Important

OutputInput

ω 2ω 3ωω

harmonicsFundamental

FundamentalIf a amplifier has a distortion…

y(t)=cosωtcos2ωtcos3ωt

Distortion

Undesired signals are generated by the amplifier’s distortion.


20logAin

20lo

gAou

t

1dB

A1-dB

3

11

12131

1450

1204320

αα

ααα

.

loglog

=∴

−=+

−

−

dB

dB

A

dBA 03

In a front end amp.

1-dB compression point

<α

A gain of amplifier will be saturated at 1 dB compression point due to the non-linearity.

)(,

)(

ppmm mVmVVRVP

mWdBmWdBm

62312

101020

2

=∴=

==− μ


In

Out

)()()()( txtxtxty 33

221 ααα ++≈

x(t)=A1cosω1t+A2cosω2t

In

322113

22211222111 )coscos()coscos()coscos()( tAtAtAtAtAtAty ωωαωωαωωα +++++=

[ ]

[ ]

[ ]ttAA

ttAAttAA

)2cos()2cos(4

3:2

)2cos()2cos(4

3:2

)cos()cos(:

12121

223

12

21212

213

21

212121221

ωωωωαωω

ωωωωαωω

ωωωωαωωω

−++±=

−++±=

−++±=

ω1ω2 ω1ω2

2ω1-ω2

2ω2-ω1

Out

IntermodulationThe distortion causes undesired signal components around the carrier signals.

Undesired signalsOriginal carriers


BPF(Band pass filter)

(BPF)

LNA

ω

ω

ω

2ω1-ω2

ω1 ω2

2ω2-ω1

Signals caused by the distortionfrequency

An amplifier generates undesired signals


)log( A120 α

⎟⎠⎞

⎜⎝⎛ 3

34320 Aαlog

inAlog20

outAlog20

Input signal

Out

put s

igna

l

Third intercept point (IP3)

Fundamentalsignal

Third distortionsignal

IIP3

OIP3

IP3

The intercept point, IP3 shows the non-linearity characteristics of amplifier.

3133

13 3

4 IIPOIPIIP ααα

== ,

The larger IP3 means the smaller distortion


MOS Device characteristicsin RF application


MOS transistor

Gate

Drain

Source

G D

S, B

rg

Cgs

Cgd

gmvg’

vg’ rds

Cds

MOS Transistor Equivalent Circuit

Body

Intrinsic gate voltage and gm are the most important factors in RF CMOS.


Cutoff frequency: fT

Cin gmViVi

in

mT C

gfπ2

=∴

Ii

Ii Io

)cos(

)sin(

tCiv

tii

in

ai

ai

ωω

ω

=

=

in

amimo C

tigvgiω

ω )cos(==

fT: Frequency at which the current gain is unity.

Input current

Gate voltageS

GD

Output current

Proportional to gmInversely proportional to Cin

For higher fT, increase gm and decrease Cin.


Amplifier gain

insg Cr

1=ω

s

T

rrG 0⋅≈

ωω

in

mT C

g=ω

Cingmvg

Vg

rsvs

ro

ig id Log (G)

Log (f)

G=gmr0

1

sT

ins

om

rr

Crrg 0

0 ωω ==

For the larger gain

Fundamentally larger gmr0 oeff

dsom r

VIrgG ⋅

⎟⎟⎠

⎞⎜⎜⎝

⎛≈≈

2

Larger Ids or ro

Larger Q

CQLQro0

0 ωω ==Q

Distortion and Cin increaseVeff is difficult to reduce

Higher fT and lower rs

For higher voltage gain, increase gm, fT, ro (Q), and decrease input and gate resistance


Vgs-Ids特性

W/L=20um/2um0.4um NMOS

( ) )()( dsdsgsds VVLWC

VVVLWC

Ieff

OX

T

OX λμ

λμ

+⎟⎠⎞

⎜⎝⎛=+−⎟

⎠⎞

⎜⎝⎛= 1

21

222

MOSの基本電圧・電流特性：２乗特性


Characteristics of gm (Basic)

⎟⎟⎠

⎞⎜⎜⎝

⎛=

⎟⎟⎠

⎞⎜⎜⎝

⎛=

2

1

2effds

m

eff

dsm VI

gVIg ,

dsox

eff IWL

CV ⋅⋅=

μ1

( )

dsm

effgs

m

gsds

ILWCg

VLWC

dVdI

g

VLWC

VVLWC

I

OX

OX

ds

eff

OX

T

OX

⎟⎠⎞

⎜⎝⎛=

⎟⎠⎞

⎜⎝⎛=≡

⎟⎠⎞

⎜⎝⎛=−⎟

⎠⎞

⎜⎝⎛=

μ

μ

μμ

2

2222

Square law region

Gm is proportional to Ids and inversely proportional to Veff.

Veff is proportional to square root of Ids and inversely proportional to square root of (W/L) ratio.

dsdseff JLWILV ⋅=∝

Veff is proportional to square root of drain current density.


サブスレッショルド領域

VgsがVTＨよりも低い電圧では拡散により電流が流れる

⎟⎟⎠

⎞⎜⎜⎝

⎛ +−=

⎭⎬⎫

⎩⎨⎧

⎟⎟⎠

⎞⎜⎜⎝

⎛ −−⎟⎟

⎠

⎞⎜⎜⎝

⎛=

T

dsTOTOXso

T

ds

T

gssods

nUVηVexpU

LWCμnI

UVexp

nUVexpII

22

1

qkTUT = 温度電圧：26mV (常温）

η DIBL (Drain Induced Barrier Lowering)係数

)CC(nox

d+= 1 Cd: 空乏層容量

Log(Ids)

VgsVTH0

弱反転領域強反転領域

ゲート電圧がしきい値電圧よりも低い電圧ではサブスレッショルド電流が流れる。電流はゲート電圧に対して指数関数的に流れる。

サブスレッショルドリーク電流

拡散電流ドリフト電流


速度飽和領域

N+ N+

垂直電界

水平電界

１） Vgが高くなるとチャネルの垂直電界が高くなり表面散乱が大きくなって

モビリティーが低下する。

2) 飽和領域では水平電界が強くなるとキャリア速度が飽和してモビリティーが劣化する、速度飽和によって電流は飽和する。

1)垂直電界効果 ( )THgseff VV −+

=θ

μμ1

0

2)水平電界効果 o

ss,sos

s

o

μvEEμv,

EEEμ)E(v 2

21

1==

+=

( )s

THgso

THgso

LvVVμ

VVLμv

21 −+

−=( )vVVWCvQI THgsox

ds 2−

=⋅=

垂直電界によるモビリティーの劣化効果を入れて

( )( ) LvVVVV

LWCI

s

o

Tgs

THgsoxods 212

2 μθξξ

μ+=

−+−

⎟⎠⎞

⎜⎝⎛≈ ,


ドレイン電圧 VD

ドレイン電

流I D

(VG-VT)2に比例して増加する

ドレイン電圧 VD

ドレイン電

流I D

ゲート電圧に対してほぼ等間隔

傾斜

)VV(WCvIMOSFET

)VV(CμLWI

MOSFET

THgsoxSds

THgsoxods

−=

−=

21

2

短チャネル

長チャネル

実際はこの中間を取り、以下の表現を用いる場合もある。

微細トランジスタの電圧・電流特性

( )αTgsoxds VVCμLWI −= 0

21

α: 1～2, 通常1.3程度桜井のα乗則T. Sakurai, et al., IEEE, JSC, Vol. 25, no.2, pp.584-594, 1990.

微細なトランジスタではゲート電圧に比例する電流になる。


Non-ideal effects to square low region

Tds

m

T

dsm

gssods

nUIg

nUIg

nUV

IIT

1==

⎟⎟⎠

⎞⎜⎜⎝

⎛≈ exp

Mobility degradation and velocity saturation

Low Veff Sub-threshold region

High Veff

LvV ceff

00

0

1μθθ

θμμ +≈

+≈ ,

( Weak inversion)

This effect becomes larger at large Veff and short channel length.

At larger Veff and lower Veff, two non-ideal effects are not negligible .


Distortion

⋅⋅⋅⋅+++= 33

221 effeffeffds VaVaVaI

3

133

3

3 34

61

aaIIP

dVIdaeff

ds =≡

Lower Veff gives higher gm, bur results in higher distortion.To obtain lower distortion ( higher IIP3), we must increase Veff.

Higher gm and lower distortion means higher Ids.


速度飽和効果と歪

Lv

VVV

LWKI

sat

effdseffds

2

11

11

0

2

μθ

λ

+=Θ

Θ+−=

( )( )

( )( )23

2

123

4

12

effeffeff

effeffeff

VVV

IIP

VVVIIP

Θ+Θ+Θ

=

Θ+Θ+=

・Veffが大きいほど歪が小さい・微細化により歪は小さくなる（速度飽和効果）


ドレイン抵抗

ドレイン抵抗はVdsがVeffよりも大きくなればリニア領域から飽和領域に入って一定値を取るもの

ではなく、ドレイン電圧により大きく変化する。Vdsが低い領域ではドレイン抵抗が小さく、低電圧で高利得の回路を設計する際注意を要する。


飽和領域のドレインコンダクタンス

xxdsds WkIg −= 1

0.4umCMOSの実測

gdsを下げる（rdsを上げる）ためにはゲート長Lを大きくする。Lminの場合はDIBL効果によりrdsが低いので注意が必要。

Lgds

1∝

飽和領域のドレインコンダクタンスgdsはチャネル長に反比例する。


ピーク遮断周波数

速度飽和領域でのgm

ピークの遮断周波数はチャネル長に反比例する（0.1umでは120GHz程度に達する）

チャネル長で決定

LWCg

Cgf

ox

m

gs

mT ππ 22

≈≈

satoxmsat vWCg =

Lvf sat

Tpeak π2=∴


GHz operation by CMOS

in

mT C

gfπ2

≡

Cutoff frequency of MOS becomes higher than that of Bipolar.Over several GHz operations have attained in CMOS technology

eff

satTpeak L

vfπ2

≈


Effect of parasitic capacitance to fT

)( pgdgs

mT CCC

gf++

≡π2

fT of actual circuit is reduced by the parasitic capacitance.There is an optimum gate width to obtain highest fT.

Cingmvi

ViCp

Cin=Cgs+Cgd

Region(1); Increased by increasing gmRegion(2); Decreased by increasing Cin


fT: MOS vs. Bipolar

⎟⎟⎠

⎞⎜⎜⎝

⎛≡

2eff

dsm V

IgT

cm U

Ig ≡

Teff nUV 2=min n: 1.4 BipCMOS gmgm41,

21

<mV

qkTUT 26≈≡

（Same operating current）

in

mT C

gfπ2

≡

BipCMOS CinCin41,

21

<

（Same fT）

Veff/2: 50-100mV(actual ckt.)

Even if fT of MOS is same as that of Bipolar, fT of MOS is easily lowered by parasitic capacitance.Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current.

MOS Bipolar

Small parasitic capacitance is a key for RF CMOS design.


VT mismatch

VT mismatch degrades accuracy; ADC, OP amp, and Mixer.Larger gate area is needed for small VT mismatch.Scaling and proper channel structure improves mismatch.


RF noise source in MOS transistor

N+ N+

Gate resistance noise

md kTBgi382 =

Induced Gate Noise

2. Channel noise

1. Gate resistance

Channel noise

3. Induced Gate Noise gg kTBgi 42 =do

gsg g

Cg

22

51 ω

=

Ig2 and id2 has a strong correlation

(C=0.4j)

dod gkTBior γ42 =,

gn kTBRe 42 =

gdo: zero-bias channel resistance in linear region

Conventional SPICE does not include this noise

mn g

kTBv3

82 =


1/f noise1/f noise of MOS is larger than that of bipolar.

22oxvf

vfnf TS

ff

LWS

V ∝Δ

= ,

For the lower 1/f noise, the larger gate area is needed.


Substrate effect

SDSDSPAD

Gate

SDSDSPAD

GateShield layer

RF power loss and noise generation

Substrate should be treated as resistive network.

This substrate resistance causes RF power loss and noise generation.

Shielding can reduce this effect.


Power loss in substrate

C

RpGp Cp

Equivalent

CR

CC

RG

pp

p

p

p

p

pp

1

1

1

1

1

2

2

2

=

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎠

⎞⎜⎜⎝

⎛

⋅=

ϖ

ωω

ωω

ωω

Very low resistance or high resistance realizes low power loss.

Higher C and moderate Rsubresults in higher power loss.


LC resonator

CQLQro

00

ωω ==Substrate

LC

r0

Q

LC1

0 =ω

LC resonator can be regarded as resistance at the resonance frequency.


インダクタ

2

1Q

S ∝φ

RF-CMOS LSI

QI 1∝

Noise:

Current

L

C

L

CVc

Vb

Vo Vo

RF-VCO

VCOの性能の大半はインダクタのQで決定される。したがってきわめて重要な素子であるが、同時に最も面積を占有する素子である。最近のRFLSIはインダクタをできるだけ用いないようにしている。


インダクタの形状とインダクタンス


インダクタのQ

３層メタル（厚さ 3um)基板抵抗 500Ω

低い周波数では配線抵抗が支配的高い周波数では寄生容量を通じて発生するロスが支配的

配線膜圧を厚くする

上層メタルを用いる高比抵抗基板を用いる

2004.11.11 Titech, A. Matsuzawa 43~ 0.35-μm CMOS /SOI Devices ~

高比抵抗基板の効果：インダクタのQの向上

高比抵抗基板では高周波信号の基板での損失が小さいためにインダクタのQが向上する。


パターンシールド

誘導電流による損失を防ぐためにインダクタと基板間にポリシリコンなどでパタンシールドを挿入することが行われている。誘起されるループ電流に対して直角にスリットを入れるか、トレンチの溝を切る


バラクタ

MOSバラクタは通常、蓄積型MOS容量が用いられる。Qが高く100程度のものが多い。


Basic RF CMOS circuit design

Low noise amplifier

Mixer

Oscillator


Lg

Ls

Cpi

Rsub

M1

M2

Z0 rg

Cgs rgs

• High gain• Impedance matching• Low noise• High IIP3

• Low noise

Conventional MOS LNA

Low noise amplifier design


Noise figure: General

sss jXRZ +=

( )nis

s

nv

s

nis

s

nv

rsn

ngsngrsn GRRR

RGR

RR

V

IRVVF ++≈++=

++= 11

2

2

22

,

,

ningnvng kTGIkTRV 44 22 == ,

NoiselessCircuit

Vs

Rs Vn,rs Vng

Ing

The lower Rnv and Gni realizes the better for lower noise figure.

ni

nv

ng

ngsopt

GR

IVR == ninvGRF 21+≈min

Noise voltage source

Noise current source

Described by equivalent resistance and conductance

231NL

WRr totsrg =

( )ds

eff

mNQSgs

gsgnv

IV

gr

rrR

1051

≈≈

+=

,

2

0

5 ⎟⎟⎠

⎞⎜⎜⎝

⎛=

T

mni

gGωω


Low NF design

( )

)(

.

0

20

51

1

4051

1

ωω

ωω

>>

++≈

+⎟⎠⎞

⎜⎝⎛+

++≈

Ts

mg

smTs

mg

rg

r

rgrg

rF

S

D

S

D

S

S

D

Divide the gate

231NL

WRr totsrg =

（いろいろ調べたが、まだ定説になっている理論式は無いと言ってよい。微妙に異なっている。）

Rsr: Sheet resistanceN：The # of division

Low noise figure

1) Lower the gate resistance

Dived the gate or lower the gate sheet resistance

2) Reduce substrate loss

Use shield technique to the input bonding PAD.

Use high resistive substrate, if possible.

3) Increase drain current

4) Increase rs, if possible.

Reduce parasitic capacitance


( )

( )

( )

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛−+=→

++=≡∴

−+=

=+−+

+

+

gsgs

gs

sin

gsgs

gs

sm

t

tin

sstmts

ttgs

sstmt

CLLj

CLg

Z

sCLLs

CLg

ivZ

sLvvgiv

visC

sLvvgi

m

ωω 1

1

1

)(

)(

Vin

Ls

vt

it vs

( )stm vvg −

Impedance matching

Lg

Cgs Ls

入力インピーダンスに合わせる

ゼロにする

入力インピーダンス整合はこのような回路により実現できる


Ids and Veff optimization

WIV ds

eff ∝

sdseffsmLNA

LNA rIVrgFIIPDR ≈∝

−∝

13

Veff

NF

Gain

3rd

distortion

dB

Adjust the Ids and Veff for optimization of gain, noise and distortion.

Lower Ids

effVIIP

Higher Ids

∝3

Dynamic range of LNA is proportional to Ids.

L

moi CgQQGainω

≈

動作電流の設定

Veff の設定

NF, IP3, Gain整合などのチェック

OK?YES

NO

大きいほど高性能

高：gm小、fT高、歪小低： gm小、fT低、歪大

Veff 高, W小Veff 小, W大


チャネル長の選定

LW

LLWVT ≡=∝Δ α

αQ

11

31.LS =

ds

OXVT

eff

T

ds

ds

nIC

LVV

II μσ 22

≈Δ

=Δ

Lro ≈

LLWVn

11≈∝

Log L 大きい小さい

Log

大きさ

VTばらつき

トランジスタの面積

電流源ばらつき

出力抵抗

1/fノイズ

ゲート容量2LLWCC oxgs ∝=

DCゲイン LrgG om ∝=

周波数特性 LGCLCCg

gdoxp

mT ++

∝ 2ω

Lにより性能が変わる。

さまざまな考慮で最適点を決めていく。


NF progress in MOS LNA

NF of MOS LNA is reaching 1dB.


Vout

VDD

LPF

Amp 1

Amp 2

DC Bias current

RF pathTwo stage amp. Reuse of Bias current

A.R.Shahani, ISSCC Dig. Tech. Papers, p.368 (1997)

HPF

Circuit example

同一電流で２段の増幅器になる。


Mixer

( )( )tAV LOsso ωωπ

±= cos2Vs

VLO

Vo( )tAV sss ωcos=

( )tAV LOLOLO ωcos=

If VLO>>4Veff (Full swing)

FIF FIF

Freq

dB

FIF

Freq

dB

FLO

Fdes

Fimage

RF spectrum IF spectrum

Mixer converts frequency, but image signal is converted to the same frequency.


Image-reject mixers

( )tLOωcos

LPF

+

LPF °− 45

Vin (t) Vout(t)

( )tLOωsin

°45

( ) ( )tAtAtV imimdesdesin ωω coscos)( +=

( ) ( )tIAAtAAtV IFRcimIFcdesout ωω coscos)( +=

Ac: Conversion gain, IR: Image rejection

IR=0 if I/Q phase difference is 90° and Channel conversion gains are equal.

Quadrature mixing realizes image-suppression.Gain and phase matching is needed.


Gain mismatch and phase error

φγγφγγ

coscos

2121

2

2

++−+

=desired

spur

PP γ

φ: Gain ratio

:Phase error

A. Rofougaran, et al., IEEE J.S.C. Vol.33, No.4, April 1998. PP. 515-534.


Passive FET mixer

Lo Lo

LoLo

Vin

Vin

Vo Vo

Low powerHigh linearityNo 1/F noise

No conversion gainNo isolation, Bi-directional

Passive FET mixer

MOS can realize passive mixer easily.

Ultimately low power, but take care of isolation.


Active mixers

Lo Lo

Vo Vo

Vin

RL

Single balanced mixer

Lo Lo

Vo

Vin

Lo

Vin

Vo

Double balanced mixer

M1

M2 M3

M1 M1’

M2 M3 M2’ M3’

Very small direct feed through and even order distortion

RL RL RL

Direct LO component


Active Mixer design

Lo Lo

Vo

Vin

Lo

Vin

Vo

M1 M1’

M2 M3 M2’ M3’

RL RL

RF amplifier

Switch

Load

Low noiseLow distortion

High gainSame as LNA

Noise: Thermal and 1/f

Gain and noise


Active mixer design

Lmmix RgG 12π

=

eff

ds

eff

mLm

onin

mLLmLO

LLon

VIIP

IV

kTg

kTRg

vSSBv

gkTRRgAIRkTRv

≈

≅≈

⎟⎠⎞

⎜⎝⎛

=

≈⎟⎟⎠

⎞⎜⎜⎝

⎛++=

3

2

1

22

1

22

12

12

22

8218

γπγπ

π

γγπγ

Mixer gain

Thermal noise

A larger dynamic range needs larger current

Ts TLO

1/F noise

1) Switch transistor (M2, M3)

gsCWLswn

swnLO

son

v

vTTv

112

4

∝≈

=

,

,,

Larger Ids is needed for higher dynamic rangeand shorter switching time for low 1/f noise.

2) Load transistors Directly produces

Phase modulation

Shorter switching time or larger Ts/TLo ratio

Load resistor

Input transistor

LO swing

Noise in switch


1/f noise

1/f noise of MOS is larger than that of bipolar.

22 , oxvfvf

nf TSff

LWSV ∝

Δ=

For the lower 1/f noise, the larger gate area is needed.


1/f noise generation

1/f noise can be expressed as small imbalance signal to the differential pair.

This voltage modulates the switching timing.

Filtered (Integrated) pulse train generates 1/f noise on the Load.

H. Darabi and A. Abidi; JSC, vol. 35, No. 1, pp.15-25, Jan. 2000

This effect can be expressed as a narrow current pulse train

1/f noise from mixer circuits causes serious problem in direct conversion and low IF conversion.


Principle of Oscillator

L C L C RL C R -R

Damped waveNon-damped wave Non-damped wave

CLQR =LCo

1=ω

mgR 2=−

Negative resistor sustains oscillation


CMOS LC Oscillator

M2 M3

L

C

L

C

Vb

Vc

Vo Vo

M1

M2 M3

I

+Vo -Vo

Rin

min gR 2

=−


Oscillator

πo

oscIrV 4

=

QCV

rVI odd

o

ddopt

ωππ==

2

CQLQro0

0ω

ω ==

L CQr0-1/gm -1/gm

1) Amplitude condition

Oscillationamplitude

Vdd

2) Oscillation condition

Headroomlimit

2Vdd

QCV

Ir

g effo

om

3232

2 ,,, ,

ω>>

L

C

There is an optimum Ids for low phase noise.

L

C

Vb

Vc

Vo Vo


ωc ω ωc ω

Ideal oscillator Actual oscillator

Phase noise in oscillator

( )1<<

−≈+

)(sin)(cos)(cos

tttAtAttA ccc

θωθωθω

Q

Phase noise causes broad noise spectrum around carrier frequency


Periodical phase noise

( ) ( )( )

( ) ( )[ ]ttAtA

ttAtAttAttAty

radtt

mcmcm

c

mmcc

mmcmmcn

mmmn

ωωωωφω

ωφωωωφωωφω

φωφφ

−−++=

⋅−≈⋅−⋅=

<<=

coscoscos

sinsincossinsinsinsincoscos)(

.sin)('

2

1

[ ])(cos)( ttAty nc φω +=

tA

ωc

ωc+ωm

ωc-ωm

Side band

Periodical phase modulation causes sidebands


Phase noise problem

Oscillator phase noise causes interference to wanted signal.This reduces SNR for received signals.


Phase noise of oscillator

2

0222

24 ⎟⎟

⎠

⎞⎜⎜⎝

⎛=⋅

Δ=

Δ m

onn

QkTrZ

fi

fv

ωω

( )

0

00

2ωωωωω

mm

LjZ ≈+

LrQ0

0

ω=

( )ωjZ

0

21ωQ

BW=

BW

ω

R

0.7R

L CQ

-1/gm -1/gmr0

( )m

m QrZωωωω

200

0 ≈+

{ }⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛⋅=

2

0

2210

msigm QP

kTLωωω log

0ωω <<m

Noise spectrum density

Phase noise

(Filter action)


Phase noise equation

{ }⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛⋅⋅=

2

0

2210

msigm QP

kTLωωω log

{ }⎥⎥⎦

⎤

⎢⎢⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛+

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅⋅=

m

m

msigm

f

QPFkTL

ω

ω

ωωω

3112

12102

0 /log

Larger signal powerHigher Q for lower phase noise

F: Noise factor

Modification

Noise floor Thermal noise filtered by LC tank

1/f noise effect

Leeson’s equation

D. B. Leeson, Proceedings of the IEEE, vol. 54, pp. 329-330, Feb. 1966.

Due to the filter action of LC tank.


Frequency characteristics of Phase noise in oscillator

0

2ω

LQBW =

3

2

0 122 msL P

FkTQ ωω

⎟⎟⎠

⎞⎜⎜⎝

⎛

2

2

0 122 msL P

FkTQ ωω

⎟⎟⎠

⎞⎜⎜⎝

⎛

sPFkT2

coω

-9dB/oct(Slope =-3)

-6dB/oct(Slope=-2)

m

Phas

e no

ise

spec

trum

ω

1/f noise Thermal

( )

Thermal

1/f noise and thermal noise is converted to 1/f3 and1/f2, respectively.

mm

aSω

ωθ =Δ

( )PsFkTS m

2=Δ ωθ

( )mmL

m SQ

S ωωωω θφ Δ⎟⎟

⎠

⎞⎜⎜⎝

⎛=

2

0

21)(


Up and down converted noise

)/( HzVVnoise

ωo 2ωo 3ωo

P (dBm)

ω

ω

Down-conv.Up-conv.

Noises around 2fo are down converted to fo.

Noise into tank


FoM and minimum phase noise

IVfLffF

ddmmoM )(

12

0⎟⎟⎠

⎞⎜⎜⎝

⎛=

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛⋅⋅=⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛⋅⋅=

o

om

o

RFm

om

rVFkT

ff

QPFkT

ff

QfL

2

1211

21

2

2

2

2

2)(

19882 mo

o

o grVIrF ⋅++= γ

πγ

Fm: Offset frequencyL(fm): Phase noise at offset freq.

F: Noise factor

indo

ddodd

o

ddopt LQ

VQ

CVrVI

ωπωππ

22===

2

1

2

93242

14 Q

VVkT

QF

eff

ddoM ∝

++=

,

γπγπ

FoM is basically proportional to Q2.

at Iopt

Tank loss Switch noise Current source


Optimization

Bias currentIopt

Phase noise Oscillationamplitude

2Vdd

Large VddLarge Veff1, but take care of Vo reductionLarge L1, W1 to reduce 1/f noiseProper W/L for M2, M3Higher QLarger QLind for Lower Iopt

2

1

212 ⎟⎟

⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅⋅⋅=

m

o

effdd

indo

ddm f

fVVQ

LV

kTfL,

min )( ωγ

Careful optimization reduces oscillator phase noise.

L

C

L

C

Vb

Vc

Vo Vo

M1: Veff1, L1, W1

M2 M3

Small W2, W3 for higher amplitude and low CpSufficient W2, W3 for acceptable gm


L

C

L

CVc

Vb

Vo VoL

C

L

C

Vb

Vc

Vo Vo

L

C

L

C

Vb

Vc

Vo Vo

Cx

LxCs

Hi-Z at 2fo

(a) (b)(c)

CMOS oscillator circuits

Basic Low power (gm is higher) Low noise by filtering

E. Hegazi, ISSCC 2001


Filtering of 2fo component in OSC.

Noise filtering of 2fo component reduces OSC phase noise to -10dB.

E. Hegazi, ISSCC 2001


Oscillator phase noise progress

Phase noise in CMOS oscillator becomes lower than that of bipolar.


Future device trend


現在のSoC用トランジスタ

現在のSoCの量産プロセスである0.13umルールのトランジスタ

原子レベルの制御が求められる。

松下電器


CMOSの微細化と高周波特性の向上

微細化とfTの上昇は今後も続くが、、、


微細化と動作電圧

微細化による動作電圧の低下は緩和されたものの今後のCMOSは1V以下の電圧で動作さなければならない。


微細化とノイズ

微細化とともに熱雑音係数は増大微細化とともに1/fノイズは減少するがHi-Kの導入は1/fノイズを増大させる。


1/fノイズとVTミスマッチトレンド

・1/fノイズの係数は比較的順調に減少と予測・VTミスマッチはあまり改善されないと予測

C. H. Diaz, et al., IEEE, Tran on ED, Vol. 50, pp.557-566、２００３


微細デバイスのドレイン抵抗

ds

effA

dsds I

VVg

r+

≈≡1

微細デバイスではポケット注入を用いていることによりチャネル長を伸ばしてもVAつ

まりはドレイン抵抗はあまり上がらない。つまり、微細プロセスではDC利得が極めてあげにくいことを意味する。

D, Buss, et al., IEEE, Tran on ED, Vol. 50, pp.546-556、２００３


インダクタンストレンド・配線層数の増加や最上層配線の厚膜化などによりインダクタンスのQは増加傾向

C. H. Diaz, et al., IEEE, Tran on ED, Vol. 50, pp.557-566、２００３

最近のインダクタは6um程度の厚さを用いて20以上のQを得ているものもある。


Cost up issue by analog parts

Cost of mixed A/D LSI will increase when using deep sub-micron device, due to the increase of cost of non-scalable analog parts.

Large analog may be unacceptable.Some analog circuits should be replaced by digital circuits


Technology edge RF CMOS LSI

M. Zargari (Atheros), et al., ISSCC 2004, pp.96 K. Muhammad (TI), et al., ISSCC2004, pp.268

Discrete-time Bluetooth0.13um, 1.5V, 2.4GHz

Wireless LAN, 802.11 a/b/g0.25um, 2.5V, 23mm2, 5GHz

Many RF CMOS LSIs have been developed for many standards


Feature of CMOS technology

• Pros– Can use switch and voltage controlled conductance– Smaller distortion– No carrier accumulation – Can use switched capacitor circuits– Can increase fT by scaling– Easy use of complementally circuits– Easy integration with digital circuits

• Cons– Low gm/Ids– Larger mismatch voltage and 1/f noise– Lower operating voltage with scaling– Difficult to enable impedance matching– Easily affected by substrate


Potential and limitation of RF CMOS

• Potential– RF CMOS are going to be major in wireless products.– SiGe Bi-CMOS technology will be used for extremely low noise and

low power RF products.– 60GHz or 100GHz CMOS circuits has already developed.

• Limitation– For low noise and low power characteristics in RF circuit, SiGe

bipolar technology must be better than CMOS. – High power PA will not be integrated on scaled CMOS chip, due to

low efficiency and needs low voltage operation.– Use of further advanced technology beyond 90nm would be limited.

This is because low analog operating voltage of less than 0.9V and chip and development cost increase.


Advantage of SiGe Bi-CMOS

Alcatel1) OkiProcess

Chip sizeﾞ

Id

Rx_Sens.

Tx_Power

Rx

Tx

Broadcom Conexant MitsubishiCMOS0.25um

40.1mm2

50mA

-80dBm

+2dBm

70mA

CMOS0.35um

18.0mm2

47mA

-77dBm

+2.5dBm

66mA

CMOS0.35um

46mA

-80dBm

+5dBm

47mA

SiGe-BiCMOS0.5um

12mA

-78dBm

+2dBm

16.4mA

Si-BiCMOS0.5um

34.4mA

44.0mA

-80dBm

0dBm

17.0mm2

Vdd 2.7-3.3V1.8-3.6V3V(?)2.7-3.3V2.5V

SiGe Bip has a great advantage in power consumption


CMOS vs. SiGe-BiCMOS

Wafer cost of SiGe BiCMOS is 30-40% higher than CMOS at the same generation,however almost same as one generation advanced CMOS.

SiGe-BiCMOSはコスト高と供給問題があったため一部のメーカーしか使用できなかったが、状況は改善し、0.13um程度の微細化も進んでいるようである。

今後、もっと使用されるものと思われる。


Principal design for RF CMOS

• Use small size devices and compensate the accuracy and 1/f noise degradation.– Small parasitic capacitance is imperative.

• Much smaller capacitance is needed to keep higher cutoff frequency under the lower gm condition

– Small size results in increase of mismatch voltage and 1/f noise• Should be addressed by analog or digital compensation,

not by increase of device size.

• Keep the voltage swing high as possible to realize higher SNR– The noise level is higher and gm is lower than those of bipolar.

• Use digital technology rather than analog technology– Performance increase and power and area decrease are promised

by scaling. Analog is not so.


Acknowledgment and references• Acknowledgment

I would like to thank Prof. Asad Abidi from UCLA and N. Itoh from Toshiba for their advices.

• References– Asad A. Abidi, “Power-Conscious design of Wireless circuits and systems,” pp.665-695,

“Trade-offs in Analog Circuit Design,” Kluwer Academic Publishers, 2002. (Edited by Chris Toumanzou, George Moschytz, and Barrie Gilbert)

– Thomas. H. Lee, “The design of CMOS RF ICs,” Cambridge University Press, Jan. 1998.– Bezad, Razavi, “RF micro-electronics,” Prentice Hall, Nov. 1999.– Domine Leenaerts, Johan van der Tang, and Ciero Vaucher, “Circuit Design for RF

Transceivers,” Kluwer Academic Publishers, 2001.– Charles Chien, “Digital Radio Systems on A chip,” Kluwer Academic Publishers, 2001.– E. Hegazi, et. Al., ”A Filtering Technique to Lower Oscillator Phase Noise,” ISSCC 2001,

23.4, Feb. 2001.– 伊藤信之, “RF CMOS回路設計技術” トリケップス 2002年– 松澤昭 “CMOSのRF応用” 応用物理, pp.318-322, Vol.71, No.3, 2002.– “Special Issue on Silicon-Based RF and Microwave Integrated Circuits”

IEEE Transaction on Microwave Theory and Techniques, Vol. 50, No. 1, Jan. 2002.

– “Special Issue on Device Integration Technology for Mixed-Signal SoC”IEEE Transaction on Electron Devices, Vol. 50, No. 3, March, 2003.

cmos devices and rf building blocks - 東京工業大学 … and circuits...2004.11.11 titech, a....

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