cmos device architecture evolution and metrology challenges … · cmos device architecture...

CONFIDENTIAL

CMOS DEVICE ARCHITECTURE EVOLUTION AND METROLOGY

CHALLENGES

NAOTO HORIGUCHI, IMEC

CONFIDENTIAL

OUTLINE

CMOS scaling trend and imec device roadmap

Device scaling and metrology challenges

FinFET

Horizontal nanowire FET

Vertical nanowire FET

TFET

2D material devices

Summary

2

CONFIDENTIAL

CMOS SCALING TRENDTRANSISTOR ARCHITECTURE UNDER PRESSURE

log

2(#

tran

sist

ors

/$)

20152013201120092007

14nm

20nm

28nm

40nm

65nm

90nm

2017 2019 2021 2023 20252005

10nm

7nm

5nm

7(?)-5nm: Finfet with

channel stress and/or

Nanowire introduction

3.5nm

2.5nm1.75nm

20nm: Planar device runs

out of steam - electrostatics

14nm: Si FinFET device

– improved

electrostatics, current

density, and mismatch

2.5nm: Fin/Nanowire

devices run out of steam

Happy scaling era

# transistors per area

doubles every two year

for same cost

DTCO

2.5nm & beyond

3D (Vertical) Logic

Hybrid stacking

Beyond CMOS

New compute paradigms

STCO

Less happy scaling era

Still doubles but device

scaling provides diminishing

returns

NO

WFocus of process technology innovation is

Scale device and wire Scale basic logic cells Scale (sub-)system functions

CONFIDENTIAL

IMEC HIGH PERFORMANCE MOBILE LOGIC ROADMAP

Early fdry

production

2014

N14 (industry ref.)

2016-2017

iN10

2018-2019

iN7

2020-2021

iN5

2022-2023

iN3

2023-...

Vdd (V) 0.8 0.8-0.7 0.7-0.6 0.7-0.5 0.6-0.5

Device FinFET FinFET FinFET or HGAA FinFET or HGAA HGAA

Channel nfet/pfet Si / Si Si / Si {SiGe} Si / SiGe Si/ SiGe (Higher mobility)

Gate Pitch (nm) 70-90, 193i 64, 193i 42, 193i 32, EUV TBD

Gate length (nm) 30 24 20 18-14 14-10

Contact metal W W W or Co Alternative metal Alternative metal

Metal Pitch (nm) 52-64, 193i 42, 193i 32, 193i, EUV cut/Via 24, EUV 18, EUV

Low k dielectric 2.55 2.55 2.55-2.4 2.7-2.4 2.7-2.1

Metallization TaN/Ta + Cu TaN/Co + Cu TaN/Ru + CuMn/Ru + Cu and/or

Co via prefillAlternative metals

Vertically integrated

device circuits

New functional scaling on top

of base CMOS:

Spintronics, 2D devices,

(Steep-Slope switches)

Horizontal nanowire

stacked devices (CFET)

Ch-IIIVCh-Ge

iNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around;

Finfet FinfetFinfet

HGAA

CONFIDENTIAL

ENHANCE PITCH-BASED SCALING WITH DTCOCONTACTED GATE PITCH SCALING

7nm10nm 5nm16/14nm

9-tracks

CGP = 78 SP

MP = 64 LELE

FP = 48 SADP

4-fin

7.5-tracks

CGP = 64 SADP/LELE

MP = 48 SADP/LELE

FP = 36 SAQP

3-fin

6-tracks

CGP = 52 SADP

MP = 40 SADP

FP = 30 SAQP

2-fin

6-tracks

CGP = 40 SADP

MP = 32 EUV SP

FP = 24 SAQP

2-fin or stacked-NW

x0.61

x0.67

x0.83

x0.51

x0.80

x0.54

x0.61

x0.84

x0.51

Pitch scaling

Pitch scaling

Pitch scaling

DTCO

DTCO

DTCO

1st gen scaling boosters:

o M1/CGP gear

o Single diffusion break

o Self aligned block

o In line merged via

o Open M1architecture

2nd gen scaling boosters:

o Self aligned gate contact

o Fully self aligned via

o Super Via

o Buried power rail

…

Fins

Fins

Gates

Fins

Fins

Gates

Gates

Fins

Fins

Fins

Fins

Gates

Contacted Gate Pitch (CGP) Scaling Gate length scaling

Fin # scaling Fin height increase or high mobility channel

CONFIDENTIAL

15 20 25 3010

Lg (nm)

60

70

80

90

100

110

120

Su

bth

resh

old

Sw

ing (

mV

/dec)

DEVICE ARCHITECTURE IMPACTS ELECTROSTATICS

FinFETs offered a Low-Voltage transistor option wrt bulk planar.

To maintain electrostatics, fin width scaling is necessary.

FinW=7-10nm

Tapered Fin

Lmin~ 28nm

Straight Fin

FinW=7-8nm

Lmin~ 22-24nm

Ultra-Thin Fin

FinW=5nm

Lmin~ 18nm

N22N14N10N7N5

28-32nm

Bulk Planar

(Vdd ~ 0.9-1.0V)

FinFETs

(Vdd ~ 0.7-0.8V)

6

CONFIDENTIAL

FIN SCALING

• Continuous fin pitch & cd scaling from SADP to SAQP

• Fin height increase for accelerate scaling and performance

High aspect ratio in fin and subsequent modules

30 n

m45 nm10 nm

5

25 nm

50 n

m

5 nm

CONFIDENTIAL

SCALED FINFET METROLOGY CHALLENGES

8

Fin

Fin

Fin

• Fin cd

• Fin height

• Fin profile

• Gate cd (@ fin sidewall)

• Gate height

• Gate profile

CD & overlay measurements in high AR 3D structures

Stress measurement in fin

Dopant diffusion & activation

in fin & SD

Defects

SiGeSi:P

Composition in thin

film & interface

CONFIDENTIAL


Early fdry

production

2014

N14 (industry ref.)

2016-2017

iN10

2018-2019

iN7

2020-2021

iN5

2022-2023

iN3

2023-...

Vdd (V) 0.8 0.8-0.7 0.7-0.6 0.7-0.5 0.6-0.5




Gate length (nm) 30 24 20 18-14 14-10



Low k dielectric 2.55 2.55 2.55-2.4 2.7-2.4 2.7-2.1




device circuits


of base CMOS:



Horizontal nanowire


Ch-IIIVCh-Ge


Finfet FinfetFinfet

HGAA

CONFIDENTIAL

15 20 25 3010

Lg (nm)

60

70

80

90

100

110

120

Su

bth

resh

old

Sw

ing (

mV

/dec)

DEVICE ARCHITECTURE IMPACTS ELECTROSTATICS

FinFETs offered a Low-Voltage transistor option wrt bulk planar.

To maintain electrostatics, simple FinFETs will hit limits

FinW=7-10nm

Tapered Fin

Lmin~ 28nm

Straight Fin

FinW=7-8nm

Lmin~ 22-24nm

Ultra-Thin Fin

FinW=5nm

Lmin~ 18nm

Nanowire =7nm

Gate-All-Around Nanowire

Lmin~ 15nm

N22N14N10N7N5

28-32nm

Bulk Planar

(Vdd ~ 0.9-1.0V)

FinFETs

(Vdd ~ 0.7-0.8V)

10

CONFIDENTIAL

CMOS LATERAL NANOWIRE DEMONSTRATION

LG = 30 nm

Pfet Nfet

NfetPfet

HfO2HfO2

TiAlTiN TaN

2 stacked Si lateral nanowires CMOS demonstration with RMG

CONFIDENTIAL

12

STACKED NANOWIRE FET FLOW

• Starting material: Si wafer

• Well implantations

• SiGe/Si epitaxy

• SADP fin patterning

• STI fill

• Dummy gate patterning

• Extension implantations

• Spacer

• Embedded S/D epitaxy

• ILD0 (incl. poly removal)

• Dummy oxide removal

• Sacrificial layer etch

• HK + WF metal

deposition

• Metal gate fill and CMP

• LI1 + LI2 + V0 + BEOL

SiGe/Si SL epi and STI formation

Stacked nanowire fabrication

by SiGe etch in narrow gate trenches

Modifications to the Si FinFET flow

(EV-FF):

40

Stacked nanowire FET process flow is similar as FinFET.

Critical metrologies: FF + nanowire specific metrologies

CONFIDENTIAL

NANOWIRE SPECIFIC METROLOGIES

Si/SiGe multi layer defects and Ge diffusion Stacked nanowire diameter and shape &

HK/WFM conformality

CONFIDENTIAL

SCALED HIGH MOBILITY CHANNEL (III-V) GATE-AROUND (GAA)

DEVICES ON SILICON

• Improving III-V GAA Passivation improves performance and scalability

• 300mm-compatible process developed & record performance for InGaAs achieved

Record InGaAs channel

performances for Vdd=0.5V

Lg ~ 36nm-46nm (NEW)

Wfin ~ 16nm (NEW)

Gmsat > 2000 mS/mm

SS ~ 90-100mV/dec

CONFIDENTIAL

DEFECT ENGINEERING FOR III-V ON SILICON

C. Merckling & IIIV Epi Team

• Unique defect trapping Innovation allows for InGaAs to be

integrated in tight geometry in proximity to Si & other materials

Defect characterization is key for high mobility channel integration in FF and NW.

CONFIDENTIAL


Early fdry

production

2014

N14 (industry ref.)

2016-2017

iN10

2018-2019

iN7

2020-2021

iN5

2022-2023

iN3

2023-...

Vdd (V) 0.8 0.8-0.7 0.7-0.6 0.7-0.5 0.6-0.5




Gate length (nm) 30 24 20 18-14 14-10



Low k dielectric 2.55 2.55 2.55-2.4 2.7-2.4 2.7-2.1




device circuits


of base CMOS:



Horizontal nanowire


Ch-IIIVCh-Ge


Finfet FinfetFinfet

HGAA

CONFIDENTIAL

FinFETGAA

No Room for

Lateral

Contacted Pitch

Vertical

• Eventually disruptive architectures like Vertical NWs can extend density scaling

2010753

10

40

60

90

Physi

cal D

imen

sio

n (

nm

)

CMOS Technology Node (nm)

• Continual gate pitch (density) scaling will be limited by space for Contact & Gate

Solution necessary for Lgate scaling and contact area scaling

LIMITS TO DENSITY/LGATE SCALING

CONFIDENTIAL18

VERTICAL FET PROCESS FLOW

• Nanowire diameter, shape, & profile control

and their metrologies are important in vertical

nanowire FET, which is similar as horizontal

nanowire.

• Vertical nanowire FET specific process control &

metrology: vertical alignment between gate-SD

CONFIDENTIAL


Early fdry

production

2014

N14 (industry ref.)

2016-2017

iN10

2018-2019

iN7

2020-2021

iN5

2022-2023

iN3

2023-...

Vdd (V) 0.8 0.8-0.7 0.7-0.6 0.7-0.5 0.6-0.5




Gate length (nm) 30 24 20 18-14 14-10



Low k dielectric 2.55 2.55 2.55-2.4 2.7-2.4 2.7-2.1




device circuits


of base CMOS:



Horizontal nanowire


Ch-IIIVCh-Ge


Finfet FinfetFinfet

HGAA

CONFIDENTIAL

MOVING TO TUNNEL FET

20

LOW VOLTAGE APPLICATIONS

CONFIDENTIAL

TFET INTEGRATION

21

Planar InGaAs TFET Vertical InGaAs TFETVertical heterojunction

TFET

Vd=0.05V

0.5V

80

70

60

50

40

30

SS

(m

V/d

ec)

10-6

10-5

10-4

10-3

10-2

Id (uA/um)

EOT=0.8 nm(c)

SS down to 54mV/dec

by EOT scaling

SS down to 75mV/dec

• Vertical TFET has same challenges as vertical

nanowire FET (NW diameter, shape, profile)

• Heterostructure defect control/metrology

is TFET specific challenge.

CONFIDENTIAL

TFET SWING & LEAKAGE DETRACTORS

drain

gate

source

gate

p i n

Ambipolar

Leakage: Low Eg

limites Vgd

Dit: Interference & Fermi pinning

due to interface defect states

SRH: Thermal Gen. &

Recomb.

kT

E

CJ

g

SRH2exp1

TAT: Trap-Assisted-Tunneling

Phonon-Assisted Tunneling

kT

EE

CJT

g

trap2exp2

Lateral (Point) Vs. Vertical (Line)

Tunneling & resultant DOS

F

ECJ

g

BTBT

2/3

exp

TFET performance dominated by heterostructure and defects.

Metrology of bulk/interface defects in heterostructure is important.

CONFIDENTIAL

ELECTRICAL EVALUATION OF DEFECTS

23

DLTS Noise

Defect impact evaluated electrically by DTLS and Noise measurement.

CONFIDENTIAL

Van

der

Waals

20Å

2-D CrystalsLow or free of dangling bonds

Wide band gap High DOS &

reasonable

mobility for ultra-thin

channels

Low-defectivity

molecular doping

Natural Nanosheets

2-D TRANSITION METAL DICHALCOGENIDES(TMD) CRYSTALS (MX2)

VdW heterostructures (No

lattice mismatch issues?)

H. Wang et al, Nanoscale, 2014, 6, 12250

• Interesting properties for ultra-thin body devices

• Especially the Metal-Se2 or Metal-S2: High Band gap &

reasonably high mobility

B. Radisavljevic et al., Nature Nanotechnology

MoS2

CONFIDENTIAL

WHY 2D MATERIALS?

Characteristic length of short channel FETs:

𝜆 =𝜖𝑐ℎ𝜖𝑜𝑥

𝑡𝑐ℎ. 𝑡𝑜𝑥

MOSFET

Reduced short channel effects in planar devices

TFET

Choice of bandgaps and band alignment

No dangling bonds at interfaces

VS

VD

0 V

2D’

2D

VG

High-k

ԦI

25

CONFIDENTIAL

2D MATERIAL SYNTHESIS AND METROLOGYCMOS and TFET require both n-type and p-type semiconductors

MX2μ (cm2/Vs)

MoS2 340-410

MoSe2 240

WS2 1,103

WSe2 705

SnS2 306

HfS2 1,833

HfSe2 3,579

W. Zhang et al, Nano

Research 2014, 7, 1731

Theoretical limit (RT) MoS2 SnS

WS2 WSe2

-30 -15 0 15 30 45 60 75

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

Id(A

/mm

)

Vg (V)

CVD up to 200mm

CVD up to 200mm

-10 -5 0 5 10

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

Dra

in C

urr

ent,

Id (

A)

Control Gate Voltage, VCG

(V)

Id PG floating

Id Vpg=10

Id Vpg=-12

Ig_CG

CVD 300mm MBE up to 200mm

2D material synthesis and bulk/interface metrology are key.

CONFIDENTIAL

SUMMARY

CMOS scaling was/is/will be continued by

CD and pitch scaling,

Device architecture evolution from 2D to 3D,

and New materials.

Metrologies required to characterize parameters, which impact device performance &

yield.

Smaller CD and pitch,

High aspect ratio 3D structures

and New materials.

27

CONFIDENTIAL

cmos device architecture evolution and metrology challenges … · cmos device architecture...

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