clifford e. cummings heath chambers - sunburst designsnug 2019 page 7 rev 1.0 finite state machine...

World Class SystemVerilog & UVM Training

FiniteStateMachine(FSM)Design&SynthesisusingSystemVerilog-PartI

CliffordE.Cummings HeathChambers

SunburstDesign,Inc. HMCDesignVerification,Inc.

Provo,UT,USA Albuquerque,NM,USA

www.sunburst‐design.com

ABSTRACTThere are at least seven different Finite StateMachine (FSM) design techniques that arecommonlytaught,onewithcombinatorialoutputsandsixwithregisteredoutputs.Thispaperwill describe four of the FSM design techniques: (1) 1‐Always Block Stylewith registeredoutputs,(2)2‐AlwaysBlockStylewithcombinatorialoutputs,(3)3‐AlwaysBlockStylewithregisteredoutputs,and(4)4‐AlwaysBlockStylewithregisteredoutputsThispaperestablishesmeasurementtechniquestodeterminegoodcodingstylesandalsoshowssynthesisresultsforASICdesigns.MultiplebenchmarkFSMdesignsareusedtomeasurecodingstyleandsynthesisefficiency.TheotherthreeFSMdesignstyleswillbedescribedinfollow‐onpapers.

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FiniteStateMachine(FSM)Design&SynthesisusingSystemVerilog‐PartI

TableofContentsFiniteStateMachine(FSM)Design&SynthesisusingSystemVerilog‐PartI.................................................1

1.Introduction.............................................................................................................................................................................6

2.Importantdesigngoals........................................................................................................................................................7

2.1Morecode=morebugs.........................................................................................................................................7

3.FSMCodingStyleMetrics...................................................................................................................................................8

4.Statemachinetypes..............................................................................................................................................................8

4.1Moore‐vs‐Mealy......................................................................................................................................................8

4.2Binary‐vs‐OneHotencoding..............................................................................................................................9

5.ASIC‐vs‐FPGASynthesis....................................................................................................................................................9

6.SystemVerilogFSMcodingstyles................................................................................................................................10

6.1OneAlwaysBlockFSMcodingstyle‐registeredoutputs...................................................................10

6.2TwoAlwaysBlockFSMcodingstyle‐combinatorialoutputs..........................................................10

6.3ThreeAlwaysBlockFSMcodingstyle‐registeredoutputs...............................................................11

6.4FourAlwaysBlockFSMcodingstyle‐registeredoutputs.................................................................12

7.SystemVerilogFSMCodingTips&Tricks................................................................................................................13

7.1Logicdatatype.......................................................................................................................................................13

7.2Assignmentsusing'0/'1/'x‐vs‐1'b0/1'b1/1'bx............................................................................13

7.3FSMmoduleheader&portlist.......................................................................................................................15

7.4Enumeratedstatetypes.....................................................................................................................................15

7.5FMSRTLcodeshoulduseSystemVerilogalways_ffandalways_combprocedures................17

7.6FSMStateRegister................................................................................................................................................17

7.7Defaultnext='x‐vs‐defaultnext=state.......................................................................................................18

7.8Nextstatenamingconvention.........................................................................................................................19

7.9Nextassignmentsplacedinacolumn..........................................................................................................20

7.10Loopbacknextstateassignments...............................................................................................................21

7.11Defaultoutputassignments...........................................................................................................................21

7.12NonblockingAssignmentraceconditions?.............................................................................................22

8.BenchmarkFSMdesigns..................................................................................................................................................23

8.1FSM1with4states,2outputsand2inputs..............................................................................................25

8.2FSM7with10states,1outputand2inputs..............................................................................................27

8.3FSM8with10states,3outputsand2inputs............................................................................................33

8.4Prep4FSMdesignwith16states,8‐bitoutputand8‐bitinput.......................................................35

9.Comparisons&Summary................................................................................................................................................38

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10.Acknowledgements.........................................................................................................................................................39

11.References...........................................................................................................................................................................39

12.Author&ContactInformation....................................................................................................................................41

ToolsandOSversions..............................................................................................................................42

FSMbenchmarksourcecode................................................................................................................43

FSM1‐fsm1_pkgsforabstractandbinaryencodedenums......................................43

FSM1‐1alwaysblockRTL‐NOTRecommended‐RegisteredOutputs.............44

FSM1‐2alwaysblockRTL‐Recommended‐CombinatorialOutputs................45

FSM1‐3alwaysblockRTL‐NOTRecommended‐RegisteredOutputs..............46

FSM1‐4alwaysblockRTL‐Recommended‐RegisteredOutputs.......................47

FSM7‐fsm7_pkgsforabstractandbinaryencodedenums......................................48

FSM7‐1alwaysblockRTL‐NOTRecommended‐RegisteredOutputs.............49

FSM7‐2alwaysblockRTL‐Recommended‐CombinatorialOutputs................51

FSM7‐3alwaysblock‐Recommended‐RegisteredOutputs.................................52

FSM7‐4alwaysblockRTL‐Recommended‐RegisteredOutputs....................53

FSM8‐fsm8_pkgsforabstractandbinaryencodedenums...................................55

FSM8‐1alwaysblockRTL‐NOTRecommended‐RegisteredOutputs..........56

FSM8‐2alwaysblockRTL‐Recommended‐CombinatorialOutputs.............59

FSM8‐3alwaysblock‐Recommended‐RegisteredOutputs..............................61

FSM8‐4alwaysblockRTL‐Recommended‐RegisteredOutputs....................63

PREP4‐prep4_pkgsforabstractandbinaryencodedenums..............................65

PREP4‐1alwaysblockRTL‐NOTRecommended‐RegisteredOutputs........66

PREP4‐2alwaysblockRTL‐Recommended‐CombinatorialOutputs...........70

PREP4‐3alwaysblock‐Recommended‐RegisteredOutputs............................73

PREP4‐4alwaysblockRTL‐Recommended‐RegisteredOutputs..................75

TableofFiguresFigure1‐Moore&MealyStateMachineblockdiagram...........................................................................................8

Figure2‐Binary‐vs‐OneHotstatediagrams................................................................................................................9

Figure3‐Blockdiagramfor1‐alwaysblockcodingstyle.....................................................................................10




Figure7‐FSM1statediagram‐usedforexamplecode.........................................................................................13

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Figure8‐DesignVisionerrormessagesfrombadusageofalways_ffbegin‐endstatements...............18

Figure9‐FSMloopbackstateassignmentstyles......................................................................................................21

Figure10‐FSM1statediagram........................................................................................................................................25

Figure11‐fsm1‐Codingstyleseffortcomparison.................................................................................................25

Figure12‐fsm1‐Linesofcode........................................................................................................................................26

Figure13‐fsm1‐Codinggoalssummary....................................................................................................................27





Figure18‐FSM7statediagram‐whyisthe1‐alwaysblockstylesoverbose?..........................................30





Figure23‐Prep4statediagram.......................................................................................................................................35

Figure24‐prep4‐Codingstyleseffortcomparison...............................................................................................36

Figure25‐prep4‐Linesofcode......................................................................................................................................37

Figure26‐prep4‐Codinggoalssummary..................................................................................................................37

TableofExamplesExample1‐FSM1moduleheaderandportlistexample......................................................................................15

Example2‐FSM1:fsm1_pkg_a.svwithabstractenumeratedstate_etypedef.............................................16

Example3‐FSM1:fs1_pkg_b.svencodedstate_etypedefw/logicdatatypeandbit‐range..................16

Example4‐FSM1:importingfsm1_pkg::*;(abstractorbinary)withstate/nextdeclaration..............16

Example5‐FSMstateregisterdeclaration.................................................................................................................17

Example6‐Badusageofalways_ffbegin‐endstatements...................................................................................18

Example7‐Defaultnext='xcombinatorialalways_combprocedureforFSMdesigns............................19

Example8‐always_combnextassignmentsinaneatcolumn‐Recommended........................................20

Example9‐always_combnextassignmentsfollowingcontourofthecode‐NOTRecommended...20

Example10‐FSMregisteredoutputassignmentsusinganalways_ffprocedure......................................22

Example11‐fsm7_1‐1‐alwaysblockstyleoutputassignmentsforeachtransitionarc.......................32

Example12‐File:fsm1_pkg_a.sv‐fsm1_pkgenumeratedtypedef..................................................................43

Example13‐File:fsm1_pkg_b.sv‐fsm1_pkgenumeratedtypedef..................................................................43

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Example14‐fsm1_1x‐1‐alwaysblockwithregisteredoutputs.......................................................................44

Example15‐fsm1_2x‐2‐alwaysblockwithcombinatorialoutputs...............................................................45

Example16‐fsm1_3x‐3‐alwaysblockstylewithregisteredoutputs............................................................46





Example21‐fsm7_2x‐2‐alwaysblockstylewithcombinatorialoutputs....................................................51






Example27‐fsm8_2x‐2‐alwaysblockstylewithcombinatorialoutputs....................................................60



Example30‐File:prep4_pkg_a.sv‐prep4_pkgenumeratedtypedef..............................................................65

Example31‐File:prep4_pkg_b.sv‐prep4_pkgenumeratedtypedef..............................................................65

Example32‐prep4_1x‐1‐alwaysblockstylewithregisteredoutputs.........................................................69

Example33‐prep4_2x‐2‐alwaysblockstylewithcombinatorialoutputs..................................................72



TableofTablesTable1‐Averagetimeverificationengineersspendinvarioustasks................................................................7

Table2‐fsm1‐Synthesisefficiencycomparisontable..........................................................................................26



Table5‐prep4‐Synthesisefficiencycomparisontable........................................................................................36

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1.IntroductionWhat could possibly be new about Finite State Machine (FSM) design? Hasn't this topic beencompletelycoveredbyexistingpublications?

SunburstDesignhasbeenteachingsixdifferentFSMcodingstyles,plusa fewminorvariants, formorethantwodecadesandthelastpaperthatCliffdidonthistopicwaspresentedin2003.Cliff&HeathhavemademanynewobservationsandrefinementstotheFSMcodingtechniquesandwehaveobservedsynthesisimprovementsusingFSMcodingstyles.Also,FSMsynthesiscanhaveinterestingdifferenceswhen synthesizing for ASICs and FPGAs. This paper shares fundamental FSM codingstylesalongwithnewerFSMdesigntechniquesthatwehaverefinedinthe15yearssinceCliff'slastFSMconferencepaper.

FSMdesignisactuallyaverylargetopic.ThesevenmajorFSMcodingstylesincludeoneFSMcodingstyle with combinatorial outputs and six FSM coding styleswith registered outputs. Registeringmoduleoutputsistypicallyrecommendedbysynthesistoolvendorsasithelpsmeettiminggoalsmoreeasilywithoutusingmultipledifferentinputandoutputtimingdesignconstraints.Registeredoutputsarealsoglitch‐free.ThereisnothinginherentlywrongwithFSMcombinatorialoutputswhenglitchingoutputsareusedinternallytoanASICorFPGAdesignandsettlebeforethenextactiveclockedgetomeetregistersetuptimes,whichcanbeprovenwithStaticTimingAnalysis(STA)tools,sowedoshowonereasonableFSMcodingstylewithcombinatorialoutputs.

Heath and Cliff generally recommend doing FSM design with registered outputs and there aremultipleFSMcodingstylesthatachievethatgoal.

Thesevendifferentcodingstylesthatwecommonlyteachare:

2‐alwaysblockcodingstylewithcombinatorialoutputs. 1‐alwaysblockcodingstylewithregisteredoutputs. 3‐alwaysblockcodingstylewithregisteredoutputs. 4‐alwaysblockcodingstylewithregisteredoutputs(newstylenotpreviouslyshown). IndexedOneHotcodingstylewithregisteredoutputs. ParameterOneHotcodingstylewithregisteredoutputs. Outputencodedcodingstylewithregisteredoutputs.

This topic is largeenough that it isour intent tobreakdocumentationon these styles into threepaperswiththisbeingthefirst.Thispaperwillcoverthefirstfourcodingstyleslistedabovewiththeremainingthreecodingstylesandsub‐variationstobecoveredinsubsequentpapers.

In theprocessofwriting thispaper,wediscovered that the1‐alwaysblockcodingstyle typicallyinfersadesignthatissomewhatsmallerandfasterthanourpreferred3‐alwaysblockcodingstyle.Wefoundthatcreatinga4‐alwaysblockFSMdesigncouldachievethesamesynthesisresultsasthe1‐alwaysblockstylewhilestillbeingamuchmoreconcisecodingstylethanthe1‐alwaysblockstyle.Thereasonsfortheseclaimsandthe4‐alwaysblockcodingstyleareincludedinthispaper.

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2.ImportantdesigngoalsHarryFosterofMentor,ASiemensBusiness,hasconductedindustrytrendstudiesusingtheWilsonResearch Group,whichwe believe are the best andmost reliable studies in our industry. ThesestudieshaveshowndesignandverificationtrendsforASIC&FPGAdesignsincetheyear2010.Intheyear 2010, Cliff Cummings and Harry Foster conducted Assertion Based Verification seminarsworldwide and in those seminars, Harry consistently claimed that the activity that was mostresponsibleforputtingaprojectbehindschedulewasdebugtime.

Table1-Averagetimeverificationengineersspendinvarioustasks

TheWilsonResearchGroupStudiesfrom2010[6],2012[7],2014[8][9],2016[10][11]and2018[12]allshowedthatdebugtimeconsistentlyconsumedthemostverificationengineeringtime.Since2014asshowninTable1,debugginghastakenonaverage~95%moreeffortthananyotherverificationtask.

Itisclearfromthesestudiesthatanycodinghabitthathelpstominimizedebugtimeisanimportanthabittodevelop.TheRTLcodingguidelinessharedinthispaperhelptoreducedebugtime.

2.1Morecode=morebugs

Ithasoftenbeensaidthatmorelinesofcodeequalsmorebugs.Aquickonlinesearchcouldnotfinddefinitivesourcesforthisclaimbutinallofthesourcesreferenced,nonemadethecounterclaimandmanysourcesgavereasonedargumentswhytheclaimthatmore_lines=more_bugsmakessense[19][20][21][22][23][24][25][26].

Forthesereasons,webelievethatconcisecodingstylesthatfollowdefensivecodingguidelinestoeitheravoidbugsortoenableearlydetectionareofgreatestvalueinRTLdesigningeneralandFSMdesigninparticular.Throughoutthispaperwewillemphasizewherewehaveusedconcisecodingstylesandstylesthathelptoeasilyidentifybugs.

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3.FSMCodingStyleMetricsInordertojudgewhatmakesagoodcodingstyle,weselectedthefollowinggoalsthatcanbeusedtojudgethevariouscodingstyles:

1. TheFSMcodingstyleshouldbeeasilymodifiabletochangestateencodingsandFSMstyles.2. Thecodingstyleshouldbeconcise.3. Thecodingstyleshouldbeeasytocodeandunderstand.4. Thecodingstyleshouldhelpfacilitatedebugging5. Thecodingstyleshouldyieldefficientsynthesisresults6. ThecodingstyleshouldbeeasytochangeduetoFSMmodificationsincludingmodifyingthe

numberofinputsandoutputs.

Thesemetricswillbeevaluatedforeachcodingstyleandtabulatedattheendofthispaper.

4.StatemachinetypesTherearetwoprinciplestatemachineclassificationsthatapplytoallstatemachinedesigns.

4.1Moore-vs-Mealy

AMoorestatemachineisclassifiedasanFSMwheretheoutputsareonlyafunctionofthepresentstate,whileMealystatemachineshaveoneormoreoutputsthatareafunctionofthepresentstateandoneormoreFSMinputs.

Figure1-Moore&MealyStateMachineblockdiagram

Moorestatemachinesarefavoredinindustrybecausetheoutputshaveafullcycletosettlethroughthecombinatoriallogicandarethereforeeasiertomeetrequiredcycletimes.Mealyoutputsallowaninputtoappearafterthecyclehasstarted,andtheinputmuststilltraversethecombinatoriallogicandmeetsetuptimefortheMealyoutput.Ifthedesignabsolutelyrequiresaninputtomakeiton‐chipaftertheactiveclockedge,passthroughlogicandappearontheoutputallwithinonecycle,thosearethedesignsthattypicallyuseaMealyoutput.

Usingaplayonwords,itissaidthat,"MooreisLess"meaningthatMoorestatemachinesareonlydependentonthecurrentstatewhileMealyStateMachinesaredependentonthecurrentstateandoneormoreinputs.

Ingeneral,weavoidMealyFSMdesignsunlessabsolutelynecessary.

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4.2Binary-vs-OneHotencoding

ThesecondmajorclassificationiswhetherthestateencodingoftheFSMdesignsarebinary(alsoreferredtoashighlyencoded)oriftheyareOneHot.

Therearemultiplebinaryencodedstylesbutwhattheyhaveincommonisthattheytypicallyusefewerflip‐flopstocreateuniquebinaryencodingsforeachstateintheFSMdesignthanOneHotFSMdesigns.

OneHotencodingusesoneflip‐flopforeachstateinthestatemachineandwhenthestatemachineisinthatstate,thatflip‐flopis"hot"orequalto"1"whiletherestofthestatesareequalto"0."Sincetransitioningfromonestatetoanotheronlyrequiresthattheprevioushotflip‐flopbesetto0andthenewhotflip‐flopbesetto1,thecombinatoriallogictotransitionbetweenstatesistypicallyverysimple.AswillbeexplainedinSection5.OneHotFSMdesignsaretypicallyinferredautomaticallybyFPGAsynthesistools.

Figure2-Binary-vs-OneHotstatediagrams

5.ASIC-vs-FPGASynthesisTherearetwoimportantdifferencesbetweenASIC&FPGAdesign.

ForASICs,thegeneralruleisthat"siliconisfreeandflip‐flopscost."Addinganothernandgatetoacombinatorialpathtypicallydoesnotaddmuchdelaytothepath,buteveryflip‐flopaddsblocksofclockedlogic,whichdoconsumespace.

ForFPGAs,thegeneralruleisthat"flip‐flopsarefreeandcombinatoriallogiccosts."FPGAstypicallyhavemoreflip‐flopsthanareneededformostdesignssousingtheextraflip‐flopsdoesnotaddmoresilicontothedesign,whilethespeedofanFPGAislargelydeterminedbythesizeofthecombinatoriallogic.IfthecombinatoriallogicfitsintooneLookUpTable(LUT)thelogicisfast.IfthecombinatoriallogicrequirestwoLUTstoimplementthecombinatorialfunction,thenthereisonelookupdelay,oneormoretracedelays,andasecondlookupdelay,whichtypicallycausesthecombinatoriallogicdelaytobemorethantwiceaslongasaone‐LUTcombinatorialimplementation.

SinceOneHotFSMdesignstypicallyrequiresmallercombinatoriallogic(asdiscussedinSection4.2), FPGA synthesis tools synthesize OneHot State Machines for smaller FSM designs by default,regardlessofthestateencodingincludedintheRTLcode.Forthisreason,FPGAsynthesistoolsaresometimesmoreforgivingwhenitcomestooptimizingsynthesiscodingstyles.AslongastheFPGAsynthesistoolrecognizesthattheRTLcodewillinferanFSM,thesynthesistoolcreatesaverygoodOneHotFSMdesignandlargelyignoresthecodingstyleusedbytheRTLdesigner.

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FPGA synthesis tools frequently have a special setting (typically a GUI switch) to turn off theautomaticcreationofOneHotFSMdesigns.OneHotFPGAdesignswillbedescribedinthePartIIFSMpaper.

6.SystemVerilogFSMcodingstylesThefourFSMcodingstylesdiscussedinthispaperarethe1‐alwaysblockwithregisteredoutputs,2‐alwaysblockwithcombinatorialoutputs,3‐alwaysblockwithregisteredoutputsand4‐alwaysblockwith registered outputs. OneHot and Output Encoded FSM coding styles will be discussed insubsequentpublications.

6.1OneAlwaysBlockFSMcodingstyle-registeredoutputs

The1‐alwaysblockFSMcoding style canbeviewedasa singlealways_ff procedure (shown inFigure3)thathandlesthestateregister,thenextstateassignmentsandtheoutputsthatbelongtothenextstate foreachtransitionarc.Thetrickused in thiscodingstyle is torecognize that theoutputassignmentsareforthestateyouaregoingtonextandnotforthecurrentstatebeingtestedinthecasestatement.The1‐alwaysblockcodingstylerequiresdesignerstosettheoutputsforeachtransition arc to thatstate andnot just once for thatstate. This iswhy this coding style is soverbose.Onthepositiveside,thesynthesisresultsaretypicallybetterthanthe2‐alwaysblockand3‐alwaysblockcodingstylessincethenextstateandnext‐outputsarebeinggeneratedinparallelinthesinglealways_ffprocedure.Thefixforthe3‐alwaysblocksynthesisinefficiencyistosplitthefinalalways_ffintoseparatealways_combfornext‐outputsandtoregisterthoseoutputsinafinalalways_ffprocedure,thuscreatingthe4‐alwaysblockcodingstyleasshowninsection6.4.

Figure3-Blockdiagramfor1-alwaysblockcodingstyle

6.2TwoAlwaysBlockFSMcodingstyle-combinatorialoutputs

The2‐alwaysblockFSMcodingstylecanbeviewedasanalways_ffstateregister(just3linesof

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code) followed by an always_comb procedure to represent the combined next state logic andcombinatorial output logic. Optionally, the outputs can be separated from the always_combprocedure and placed into a separate always_comb procedure or into one or more continuousassignmentstatements.


6.3ThreeAlwaysBlockFSMcodingstyle-registeredoutputs

The3‐alwaysblockFSMcodingstylecanbeviewedasanalways_ffstateregister(just3linesofcode)followedbyanalways_combproceduretorepresentthenextstatecombinatoriallogicandanalways_ffproceduretocalculateandregisterthenextoutputs.


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Thetrickusedinthiscodingstyleistorecognizethattheoutputassignmentsarethe"next"outputassignmentsandnottheoutputassignmentsforthecurrentstate,sothefinalalways_ffprocedurewilluseacasestatementtotestthenextstate,notthecurrentstate.Sincetheoutputsarecalculatedfromthenextstatelogic,thiscanaddextralogicwhensynthesizedasthenextstatewasalreadycalculated from input conditions. Thismeans that there is one block of combinatorial logic thatcalculatesthenextstateandthatfeedsasecondblockofcombinatoriallogictocalculatethenextoutputs,whichcancreatelargerandslowercombinatoriallogic.Inthe1‐alwaysblockcodingstyle,theinputsandstatevariablesareusedtocalculateboththenextstateandnextoutputsinparallel,whichcanreducethesizeanddelaythroughthecombinatorialnextoutputlogic.Thisinefficiencywillbeaddressedinthe4‐alwaysblockcodingstyledescribedinthenextsection.

6.4FourAlwaysBlockFSMcodingstyle-registeredoutputs

Whilewritingthispaper,wediscoveredthatthe1‐alwaysblockcodingstylerequiredmuchmorecodebuttypicallygavebettersynthesisresultsthanthe3‐alwaysblockcodingstyle.Thiswasabitofasurpriseuntilwerealizedthatthenext‐outputcombinatoriallogicofthe3‐alwaysblockcodingstyleisfedbyanotherblockofcombinatoriallogicthatwasusedtocalculatethenextstate.The1‐always block coding style generated the next state and next‐outputs in parallel, in the samecombinatorialblockoflogic.

Wefoundthatcreatinga4‐alwaysblockcodingstylewherethecombinatorialnextoutvaluesarecreatedfromanalways_combprocedurethatsimultaneouslyexaminestheregisteredstateoutputsalongwiththeFSMinputs,wouldgenerallygivethesameoptimizedsynthesisresultsasthe1‐alwaysblockcodingstylewithfarfewerlinesofcode.Thefirstalways_ffandalways_combproceduresareidenticaltothe3‐alwaysblockcodingstyle.Thethirdalways_ffprocedurefromthe3‐alwaysblockcodingstyleissplitintoanalways_combproceduretocalculatethenext‐outputlogicandanalways_ffproceduretoregisterthenext‐outputs.Theseoptimizationsimprovedsynthesisresultstomatchtheresultsobservedwiththe1‐alwaysblockstyle.


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7.SystemVerilogFSMCodingTips&TricksAsoftheyear2019andafter15yearsofSystemVerilogFSMcoding,wehavecompiledsomeofourfavorite FSM coding tips and tricks. You do not have to follow any of these tips and tricks toimplementaworkingandsynthesis‐efficientFSMdesign,butwehavefoundthemtobeusefulandadvantagesofusingeachtrickwillbeexplained.Usersareencouragedtoimplementtheirfavoritetricksfromthislistandfeelfreetosharebackwithussomeofyourfavoritetricks.

Manyofthesetricksfallintothecategoryof"lessisbetter."Wefinditeasiertovisualizeadesignthatisconciseandwheremoreofthedesigncanbeviewedwithoutadditionalscrollingonacomputerscreenorflippingofprintedpages.Forus,awellformattedandconcisedesignearnsextrapoints.

Tohelpexplainthetips&tricks,wewillusethefollowingverysimpleMoorestatemachinewithfourstates,twoinputsandtwooutputs.

Figure7-FSM1statediagram-usedforexamplecode

7.1Logicdatatype

ForSystemVerilogRTLcoding,designersshouldfollowthisguideline:

Declarealldatatypestobeoftypelogicunlesstherearemultipledriversonthesignal,thenusethewiredatatype.

The threemost common sources for validmulti‐driver‐signal designs are bus crossbars, OneHotmultiplexers and bidirectional buses, all of which are becoming increasingly scarce in modernhardwaredesign.Anylogicthatincludesthree‐statelogicisstronglydiscouragedincontemporaryASICdesignsandalmostnon‐existentinmodernFPGAdesigns.

Thestrongadvantageofthelogicdatatypeisthatifadesignerevermistakenlymakesmultipleassignmentstothesamesignal, thesimulationcompilerwillcatchandreport theerrorbeforeanengineereversimulatesorsynthesizesthedesign.Catchingtheerrorbeforesimulationsavesdebugtime.

Checklistitem:EngineersshouldgenerallydeclareallFSMportsandallFSMinternalsignalstobeoftypelogic.

7.2Assignmentsusing'0/'1/'x-vs-1'b0/1'b1/1'bx

SystemVerilogintroducedaveryconvenientshorthandtoassignall0's,all1'sorallX'stoascalarsignaloravectorbus.Thenotationistoassign'0 (allzeros),'1(allones)and'x(allX's).Although

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thisisasmallenhancement,itisusefulformultiplereasons.

First,assigning'0insteadof1'b0ismoreconcise,albeitbyonlytwocharacterssothisisnotthecompellingreasontousethisstyle.

A better reason is that the notation 1'b0 is somewhat confusing and when the code is quicklyscanneditiseasytomistakethisassignmentfora"1"whiletheshorter'0conveysnosuchconfusion.

Sowhynotjustuse0or1tomakeanassignment?Assigning0or1 isacceptableandcommoninVerilogdesignsandtheytypicallyworkjustfine,butassigning0isreallyassigning32‐bitsof0whileassigning1 is really assigning31‐bits of0with LSB equal to1 andVerilog quietly truncates theleading31bitswhenthisisassignedtoa1‐bitvariable.Thisisfineunlessthecodeisrunthroughalintingtool,whichfrequentlyreportsawarningthat32bitsarebeingassignedtoa1‐bitvariable.Theassignmentworksfinebutthewarningisbothannoyinganddistractingsoengineersoftenaddwaiverstotheirlintingtoolstoignorethiswarning.

Coding'0/'1/'xassignsasmany0's,1'sorX'sasarerequiredtofill theleft‐hand‐side(LHS)variable or wire that is being assigned, so there is never any linting tool warning related tomismatchedsizeswhenmakingthesenewSystemVerilogassignments.

AlsowhenassigningX'susingtheolderVerilogstyle,onemustindicatehowmanyX‐bitsarerequiredfortheassignmentwhile'xwillfilltheassignedvariablewithasmanyX'sasareneeded.Thisavoidsbugsthatmightbeintroducedwhenwidthsarechangedlaterinthedesign.

Weuse'0/'1/'xforallofourFSMdesigns,andforthatmatter,forallofourSystemVerilogdesignsthatdonotrequireanon‐repeatedfillpattern.Formoreunusualassignmentpatterns,westillusethe older Verilog style to indicate the bit‐pattern and howmany bits are required, for example8'b0110_1100or8'h6C.

Checklistitem:Whereeverpossible,usetheSystemVerilog'0/'1/'xtomakeassignments.

7.2.1Cautionusing'0/'1/'x

Althoughwerecommendusingthesenewassignmentstyles, thereare twopointsofcautionthatengineersshouldunderstand.

First,assigning'1willassignall1'sandnotall0'sfollowedbyasingle1.Ifyouassigndata[7:0]='1thendatawillbeequalto8'hFF,not8'h01.'1doesindeedassignall1's.

Second,when'0/'1/'xareplacedinsideofconcatenation,theyareonly1‐bitassignmentsandtheydonotfilltheremainingbitswiththepattern.Ifyouassigndata[7:0]={'1, 4'hA}theresultwillbethatdataisequalto8'h1AandNOT8'hFA.Thereasonthatthe'1doesnotfilltheleadingbitsisbecausewhatifmultiple'1/'0assignmentsareincludedinthesameconcatenation?Whereisthefilloperationsupposedtooccur?Considerthefollowingexamples:

data[15:0] = {'1, 4'hA, '0}; // Which bits should be leading 1's and which bits should be trailing 0's? data[15:0] = {'0, '1, '0}; // Which bits should be leading 1's, middle 0's and trailing 1's?

Thereweretoomanyopportunitiesforconfusionbyadding'0/'1/'x/'ztoconcatenation,sothe SystemVerilog Standards Group decided that when this shorthand notation was used inconcatenationthatthenotationwouldonlyexpandtoasinglebiteach.Intheaboveexamples,thevaluesexpandasshownbelow.

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data[15:0] = {'1, 4'hA, '0}; // is equal to 16'b0000_0000_0011_0100 or 16'h0034 data[15:0] = {'0, '1, '0}; // is equal to 16'b0000_0000_0000_0010 or 16'h0002

7.3FSMmoduleheader&portlist

TheFSMmoduleheaderandportlistshouldbecodedusingtheVerilog‐2001conciseportliststyle.AllportsshouldbedeclaredtobeoftypelogicforthereasonsdiscussedinSection7.1Weordertheportlistasoutputsfollowedbyinputsfollowedbycontrolinputs.Theoutputs‐inputsorderisnotrequiredbyVerilogorSystemVerilogandmanyengineersprefertolistinputsfollowedbyoutputs.SinceVeriloggateprimitivescanonlybeinstantiatedusingpositionalportsandsincetheorderisalwaysoutputsfollowedbyinputsfollowedbycontrolinputs,wefollowthatsameconventionwithourownmodules.Wehavealsobeentoldbyengineeringcolleaguesthatmostmodulechangesarerelatedtoaddingormodifyingtheinputsandthatitiseasiertomodifytheendofthelistasopposedtothefrontorcenterofthelist.

ThemoduleheaderandportlistfortheFSM1designisshowninExample1.

module fsm1_3 ( output logic rd, ds, input logic go, ws, clk, rst_n);

Example1-FSM1moduleheaderandportlistexample

Manyengineerslisteachportonaseparatelineandthereisnothingspecificallywrongwiththatpractice,butweprefertogroupmultiplesignalsintoeachoutputandinputdeclarationasshowninExample1,toreducethenumberoflinesofcodeintheFSMdesignandtoallowmoreoftheFSMdesigntobevisibleperpagewhenexaminingthecode.

Checklistitem:UsetheVerilog‐2001conciseportdeclarationstyleanddeclareallportstobeoftypelogic.Extrapointsforlistingoutputsfollowedbyinputsfollowedbycontrolinputs.Extrapointsforgroupingmultiplesignalsintoeachoutputandinputportlistdeclaration.

7.4Enumeratedstatetypes

EnumeratedtypesareusedtomakethestateandnextstatedeclarationsandthentheenumeratedstatenamesareusedthroughouttheFSMdesign.

Whileworking on this paper,we discovered that thereweremultiple advantages to putting theenumerateddeclarationsintoapackageastypedef[s]andthenimportingthepackageintotheFSMdesign.

Weusedthenamingconventionof<fsm-name>_pkgandweactuallymaintainedtwodifferentFSMpackages,onewithabstractenumerateddeclarationtypedefwithfilename<fsm-name>_pkg_a.sv(_a for abstract) and onewith binary encoded enumerated declarationtypedef with filename<fsm-name>_pkg_b.sv(_bforbinary).

UsingtheFSMenumtypedefpackagesofferedthefollowingadvantages:

(1) EachFSMcodingstylewould import thesameFSMpackagesandensure thatall theFSMstylesusedtheexactsameFSMtypedef[s].Feweropportunitiestomakemistakes.

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(2) By maintaining pkg_a and pkg_b files, we could easily switch from abstract to binaryencodedenumtypedef[s]withoutmaintainingtwocopiesofeachFSMfile.

(3) Simulation of either abstract or binary‐encoded enum[s] was as easy as selecting andcompiling the appropriatepackagebefore compiling the other simulation files since eachpackagehadthesameidenticalpackagename.Thisgaveusmucheasiercodemaintenance.

(4) Similarly,synthesisofeitherabstractorbinary‐encodedenum[s]wasaseasyascompilingtheappropriatepackagebeforecompilingtheothersynthesisfilessinceeachpackagehadthesameidenticalpackagename.Again,mucheasiercodemaintenance.

(5) Ifwewantedtotrydifferentenumeratedassignments,weonlyhadtochangethepkg_bfileandallstyleswouldusetheexactsamenewencodings.WedidnothavetotouchtheFSMfilesthemselves.

(6) Thetestbenchcouldeasilyusethesamestate_etypedeftoimplementreferencemodelstotrackexpectedFSMstates,ifdesired.

(7) Thetestbenchcouldeasilyusebind‐filesforassertionsorcovergroupsbyusingthetypedeftoinputthestateandnextvariablesfromtheFSMdesign.

Afterweimplementedtheseparatepackagefiles,wewereabletocutthenumberofFSMbenchmarkfilesinhalfandensuredamoreerror‐freecodingstyle.

The enumerated declarations for thestate_etypedef can either bemade using abstract stateencodingsasshownin

Example2,orcanbemadeusingthelogicdatatype,specifyingthenumberofstatebitsasarange,andincludeuser‐definedencodingsforeachstateasshowninExample3.

package fsm1_pkg; typedef enum {IDLE, READ, DLY, DONE, XXX } state_e; endpackage

Example2-FSM1:fsm1_pkg_a.svwithabstractenumeratedstate_etypedef

package fsm1_pkg; typedef enum logic [1:0] {IDLE = 2'b00, READ = 2'b01, DLY = 2'b11, DONE = 2'b10, XXX = 'x } state_e; endpackage

Example3-FSM1:fs1_pkg_b.svencodedstate_etypedefw/logicdatatypeandbit-range

import fsm1_pkg::*; state_e state, next;

Example4-FSM1:importingfsm1_pkg::*;(abstractorbinary)withstate/nextdeclaration

ItistypicalforRTLcoderstostartwiththeabstractstateandnextdeclarationsandtolateraddstateencodingsifdesired.SincethestatenamesareusedthroughouttheFSMRTLcode,addingstate

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encodingslaterdoesnotrequireanyadditionalRTLmodificationstotheFSMdesign.

Theenumeratedstatenamesalsoshowupautomaticallyinawaveformdisplaytohelptrackstatetransitions and to help debug the state machine. It is often useful to show two copies of theenumeratednamesinthewaveformdisplay,thefirstshowingthestatenames(whichisthedefaultmodeforallwaveformviewers)andthesecondcopywiththeradixchangedtobebinary,decimalorhex to see the state encodings (often useful for debugging). There is nothing in the IEEESystemVerilogStandard[15]thatrequiresawaveformviewertoshowthestatenamesbydefault,butallwaveformviewersthatwehaveusedfromallofthemajorEDAvendorsshowthestatenamesbydefault.

ItisagoodpracticetoincludeanextraXXorXXXstateinthelistofdeclaredstatenamesasshowninbothExample2andExample3.ThisextraXXXstatewillbeusedtocodethealways_combprocedureandthispracticecanhelpquicklydebuganFSMdesign,plusifonechoosestoincludestateencodings,theXXXstatewillbesettoallX's,whicharetreatedas"don'tcares"bythesynthesistooltohelpoptimizethesynthesizeddesign.

Checklistitem:Declarethestateandnextvariablesusingenumeratedtypes.AddanXXorXXXstatetohelpdebugthedesignandtohelpoptimizethesynthesizedresult.

7.5FMSRTLcodeshoulduseSystemVerilogalways_ffandalways_combprocedures

The RTL code for the FSM design should usealways_ff andalways_comb procedures to inferclockedandcombinatoriallogic.DonotusetheolderVerilogalwaysprocedures.Thealways_ffandalways_combproceduresshowdesignerintentandincludebuilt‐incheckingforbadRTLcodingstylesasdescribedinthepaper"SystemVerilogLogicSpecificProcessesforSynthesis‐BenefitsandProperUsage[3]."

Checklistitem:Usealways_ffandalways_combprocedurestoinferclockedandcombinatoriallogic.DonotusetheolderVerilogalwaysprocedures.

7.6FSMStateRegister

Thestateregistershouldbeanalways_ffprocedureandshouldbe3linesofcode,not5linesandnot6lines.ThisstateregisterisplacedatthetopoftheFSMdesign,immediatelyfollowingtheFSMdeclarations,andrequiresnocommenttonotetheobviousstateregistercode.Sincethestateregistercodeisatthetopofthemodule,thereisnoneedtosearchtheremainderoftheFSMdesigntoseethatthestateregistercodewasaddedandimplementedproperly.

Withaposedge clkandalow‐trueasynchronousreset,ourstateregistersarealmostalwaysexactlythefollowingthreelinesofcode:

always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= IDLE; else state <= next;

Example5-FSMstateregisterdeclaration

Thereisnoneedtoputtheif‐statementandthestateassignmentonseparatelinesandthereisnoneedtoputbegin‐endonthealways_ffprocedure.Also,weplacetheresetstateassignmentandnextstateassignmentintoanice,neatcolumnforeasyscanningandreading.

Notethataddingbegin‐endtothealways_ffprocedureisnotonlyunnecessary,butintroducesthe opportunity to add code before the first if (!rst_n) statement, which violates coding

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requirementsforsomesynthesistoolsincludingDesignCompiler.Inshort,thealways_ffbegin‐endallowsanRTLdesignertocodeandsimulatesomethingthatmightnotbesynthesizableandassuch,weconsiderthistobeapoorcodingpractice.

ConsiderthelegalRTLcodeinExample6.

always_ff @(posedge clk, negedge rst_n) begin testbad <= go; if (!rst_n) state <= IDLE; else state <= next; end

Example6-Badusageofalways_ffbegin-endstatements

ThisexamplecodeislegalSystemVerilogcodeandwillsimulatewithouterror,butoncethisdesignisreadintotheDesignVisionGUI,thefollowingerrormessagesarereportedinapop‐upwindow:

1: Error: <filename><line number>: The statements in this 'always' block are outside the scope of the synthesis policy. Only an 'if' statement is allowed at the top level in this always block. (ELAB-302) 2: Error: Cant' read 'sverilog' file <filename> (UID-59)

Figure8-DesignVisionerrormessagesfrombadusageofalways_ffbegin-endstatements

Inshort,thebegin‐endisunnecessary,needlesslyverboseandintroducestheopportunitytoaddbadcodethatmightnotbediscovereduntilthedesignisreadforsynthesis.

Checklistitem:Declarethestateregisterusingjust3linesofcodeandplaceitatthetopofthedesignaftertheenumeratedtypedeclaration.

7.7Defaultnext='x-vs-defaultnext=state

There are two commonways to code the always_comb procedure for an FSM design. The twomethods are to either make a pre‐default‐X next assignment or use a pre‐default next=stateassignment[16]withimpliedloopbackassignments.Whilerunningsynthesisbenchmarksonbothstyles,andtooursurprise,wediscoveredthatthenext='xpre‐default‐Xassignmentconsistentlygavebettersynthesisresultsoverthepre‐defaultnext=stateassignmentstyle.Thereasonseemstobethatthepre‐default‐Xtendstofilloutasynthesis‐equivalentoftheKarnaughMap(K‐Map)withX's,especiallywhentherearefewerthan2nstatesintheFSMdesign.Evenwhenaddingcase‐default‐Xassignmentstobothstyles,thepre‐default‐Xassignmentstyleconsistentlygavebettersynthesisresults.

always_comb begin next = XXX; // Pre-default-X assignment case (state) IDLE : if (go) next = READ; else next = IDLE; //@ loopback READ : next = DLY; DLY : if (!ws) next = DONE; else next = READ;

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DONE : next = IDLE; default: next = XXX; // case-default-X assignment endcase end

Example7-Defaultnext='xcombinatorialalways_combprocedureforFSMdesigns

AnyonewhohasdoneextensiveRTLcodingandsimulationrecognizesthat,whenitcomestoRTLdebugging,catastrophicRTLcodingfailuresaretheeasiesttofind,identifyandfix.Conversely,subtleRTLcodingerrorscanoftenbeverytimeconsumingtofindandfrequentlyrequiretheRTLcodertoaddnumerousdebugprintingmessagestofinallydiscoverthesubtleprobleminthecode.MakingX‐assignmentscanhelpcausecatastrophicsimulationfailureswhenthereisanRTLdesignproblem,whileimpliedloopbackerrorscanoftenallowanFSMdesigntoappeartobeworkingformultipleclockcyclesbeforethesimulationreportsanFSMsimulationerror.

Sohowdoesthisworkandwhatproceduredowerecommend?

Westronglyencourageengineerstomakethepre‐defaultnext='xassignmentintheFSMdesign.Thepre‐defaultX‐assignmentshavetwoRTLsimulationdebugadvantagesandoneRTLsynthesisadvantage.

The RTL simulation advantage is that assigning X's frequently causes the simulation to failcatastrophicallyifthereisamissingnextassignment.Atthepointwherethereisamissingnextassignment, we say that the waveform display "starts to bleed red!" Wherever the next stateassignmentismissing,thewaveformdisplaywillshowthatnextisallX'sandthatistypicallytheexactpointwherethenext‐assignmentismissing.Thisisacatastrophicsimulationerrorthatquicklyidentifiesthemissingassignmentand,fromourexperience,isfixedveryquickly.

ThesecondRTLsimulationadvantageisthatmakingapre‐default‐XassignmentrequirestheRTLcodertocodeanequationforeachtransitionarcfromeachstate.AftercompletingtheFSMdesign,adesignercandouble‐checkthecodebycountingthenumberoftransitionequationsforeachstateintheRTLcodeandmatchthattothenumberoftransitionarcsinthestatediagram.Thereisaone‐to‐one correspondence between the number of transition equations and transition arcs. Using thenext=statedefaultassignmentallowsdesignerstoremoveloopbacktransitionassignmentsfromtheRTLcodewhereverthereisafeedbacklooponthatstatesotherewillbefewerRTLequationsthantransitionarcsinthestatediagram.

TheRTLsynthesisadvantageisthatmakingX‐assignmentsislikeputtingX'sintoaK‐MapforunusedstatesandalldigitaldesignengineersrecognizethataddingX'stoaK‐Mapallowsengineersortoolstomakelargergroupings,enablingsmallersums‐of‐products,whichcaninfersmallercombinatoriallogic(atleastintheory).

Makinganext=statepre‐defaultassignmentonlyhasoneminoradvantageoverthenext='xpre‐defaultassignment.AnystatewithaloopbacktransitioncanbeomittedfromtheRTLcodesincethatstatewill not take another transition branch andwill remain in the same state; thus potentiallyremovingafewlinesofcode.

SincedebugtimeisaprimaryconcerninRTLdesign,werecommendusingthepre‐defaultnext='xassignmentstyle.

Checklistitem:Usethepre‐defaultnext='xassignmentatthetopofthealways_combprocedure.

7.8Nextstatenamingconvention

Weprefertousetheidentifiersstateandnext,notstateandnextstate.Thereisnothingwrong

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withusingnextstateexceptthatitisaneedlesslylongidentifierthatlengthensthecodeonallofthenextassignmentsinthecombinatorialalways_combprocedure.

WeknowthatnextisakeywordinVHDLsothosewithaVHDLbackgroundtendtogravitatetowardsusing thenextstate identifier, butnext is not a keyword in SystemVerilog and SystemVerilogcoderscanmaketheirdesignsmoreconcisebyusingthenextidentifierinsteadofusingnextstate.Aspreviouslymentioned,wepreferconcisecode.

Checklistitem:ExtrapointsforusingnextinsteadofusingnextstateintheFSMdesign,butbothworkfine.

7.9Nextassignmentsplacedinacolumn

SincereadabilityandtheabilitytoquicklyidentifyRTLcodingerrorsareveryimportant,wealsoplace all of thealways_combnext assignmentsneatly in a columnpositioned towards the rightmarginoftheRTLcodeasshowninExample8.Wefinditeasiertoscanthenextassignmentswhentheyare inaneatcolumnasopposedtonextassignmentsthat followthecontourof thecodeasshowninExample9.Thisstylealsohas theadvantagethat ifanengineerevermistakenlyusesamixtureofblockingandnonblockingassignmentsinthenextassignments,isitvisuallyveryobviousintheslightlymisalignedcolumnofnextassignments.

always_comb begin next = XXX; case (state) IDLE : if (go) next = READ; else next = IDLE; //@ loopback READ : next = DLY; DLY : if (!ws) next = DONE; else next = READ; DONE : next = IDLE; default: next = XXX; endcase end

Example8-always_combnextassignmentsinaneatcolumn-Recommended


Example9-always_combnextassignmentsfollowingcontourofthecode-NOTRecommended

Ofcoursethesimulationandsynthesisofbothoftheaboveexampleswillbeidentical.Thecolumnalignmentisusedtoquicklyunderstandanddebugthealways_combnextassignments.

Checklistitem:ExtrapointsforplacingthenextassignmentsinaneatcolumnintheFSMRTLcode.

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7.10Loopbacknextstateassignments

Anystateinthestatediagramwithaloopbackstatemustbecodedintothealways_combportionofthedesign.Therearetwowaystohandletheloopbackassignmentsdependingonhowthedefaultnextassignmentwasimplemented.

Ifthepre‐defaultnext='xwasused(whichiswhatwerecommend),theloopbackassignmentmustbecoded,butwerecommendthattheloopbackbeimplementedastheelse‐clauseofanif-else-ifstatement.Wefurtherrecommendthatacommentbeaddedtotheloopbackelse‐assignmentoftheform//@ loopback.Thereasonforthiscomment‐stylewillbeexplainedshortly.


always_comb begin next = state; case (state) IDLE : if (go) next = READ; READ : next = DLY; DLY : if (!ws) next = DONE; else next = READ; DONE : next = IDLE; default: next = XXX; endcase end

Figure9-FSMloopbackstateassignmentstyles

Ifthepre‐defaultnext=stateisused,theloopbackassignmentcanbeomittedfromtheif-else-ifstatementsincethenextstateisalreadyassignedtostayinthecurrentstate.

Thereasonforusingthe//@ loopback commentandplacingthe loopback intothe finalelse ‐clauseisthatitmakesitveryeasytoconvertfromthenext='xpre‐defaulttothenext=statepre‐defaultstyleofalways_combprocedure(althoughwedonotrecommendthelatter).TheRTLcodersimplyreplacesnext='xwithnext=stateandthendeletesalllinesthathavethe//@ loopbackcomment.

7.11Defaultoutputassignments

WhencodingtheoutputsinanFPGAdesign,wehaveobservedthatsomeengineersmakealloftheoutput assignments for each state of the case statement. We discourage this practice for thefollowingreasons:

It iseasytomissanoutputassignmentforoneofthestates,whichmeansthatthemissedoutput

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mustnotchangeforthatstateandthatwillinferalatchwhensynthesized.

ListingalloftheoutputsforeachstatecausestheFSMRTLdesigncodetogrowinsizeveryquickly.

Listingalloftheoutputsforeachstatemakesitconfusingforanengineertodeterminewhichoutputshave changed in which states. Engineers often try to examine the output assignments for theprecedingandnextstatesinanattempttotrytofigureoutwhathaschangedinthisstate.

Abettercodingpracticeistoplacedefaultoutputassignmentsbeforetheoutput‐assignmentcasestatementandthentoupdatetheappropriateoutputsforeachstatewheretheoutputschangeasshowninExample10.

always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin rd <= '0; ds <= '0; end else begin rd <= '0; ds <= '0; case (next) IDLE : ; READ : rd <= '1; DLY : rd <= '1; DONE : ds <= '1; default: {rd,ds} <= 'x; endcase end endmodule

Example10-FSMregisteredoutputassignmentsusinganalways_ffprocedure

Thiscodingstyleofferstwosignificantadvantagesovermakingalloutputassignmentsforeachstate.

First,thecodebecomesmoreconcise.Secondanengineercanplainlyseewhichoutputschangeforeachstate,thusmakingthecodemorereadable,easiertounderstandandeasiertodebug.

Thisstylerequireslesscode(oneofourgoals)andmakesthedesigneasiertodebug(alsooneofourgoals).

Checklistitem:Placepre‐defaultoutputassignmentsbeforetheoutput‐assignmentcasestatementandthenupdatetheappropriateoutputsforeachstatewheretheoutputschange.

7.12NonblockingAssignmentraceconditions?

ThecodeshowninExample10showsdefaultoutputassignmentsusingnonblockingassignmentsfollowedbymorenonblockingassignmentstothesameoutputsinthecasestatement.WeareoftenaskedifthisisaraceconditioninVerilogandSystemVerilog?Theanswerisnoandthecodingstyleshownisbothproperandrecommended.

The question arises due to an error in the 1995Verilog Standard[13]. Section 5.4.1 of the 1995VerilogStandardcorrectlystatesthattwononblockingassignmentstothesamevariablearequeuedintheorderthattheyareexecutedsuchthatthelastassignmentwins(inmoreofficialverbiage).Inthe same 1995 Verilog Standard, Section 9.2.2 includes an example with a mistake where twoassignments are sequentially executed and the description states that the "final value … isindeterminate."Thatdescriptionwaswrong.

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The2001VerilogStandard[14]fixedtheexampleinsection9.2.2tohaveparallelexecutionofthetwoassignments,whichindeedisaracecondition;thus,Section5.4.1clearlygovernsthebehavioroftwosequentiallyexecutednonblockingassignmentsandlastassignmentwins.

ThereisnoraceconditioninExample10.

8.BenchmarkFSMdesignsThispaper examines coding efforts andDesignCompiler synthesis results for fourdifferentFSMbenchmark designs: FSM1, FSM7, FSM8 and Prep4. Each design includes a state diagram and adescriptionoftheRTLcodeusingthefourdifferentFSMcodingstyles,1‐alwaysblockwithregisteredoutputs,2‐alwaysblockwithcombinatorialoutputs,3‐alwaysblockwithregisteredoutputsand4‐alwaysblockwithregisteredoutputs.ThefullRTLcodeforeachexampleisincludedinAppendix2.

Forbenchmarkpurposes,wehavenotedthenumberoflinesofcoderequiredtocompleteeachofthe four coding styles that incorporated the pre‐default‐X assignments and included all of theloopbackassignments.Webelievethepre‐default‐XwithexplicitloopbackcodetobeindicativeofthecodingeffortforeachFSMdesign.WealsoassignedourevaluationforeachoftheoriginalcodinggoalsforeachstyleasdescribedinSection3.WehaveincludedcodingobservationsforthedesignsineachofthefourFSMsections.

Thesynthesisresultsweretestedusingthe1‐alwaysblock,2‐alwaysblock,3‐alwaysblockand4‐alwaysblockcodingstyles.Eachofthesefourcodingstyleswasalsotestedwithslightvariations,specifically,eachwastestedwithoutusingcase-default‐Xassignments(Nocase‐default‐X),withcase-default‐X assignments (case‐default X) and then used case‐default‐Xwith pre‐default‐X(required "Explicit loopback" assignments) and with next=state (used "Implicit loopback"assignments).

To see if there have been improvements between a 2015 version and a 2018 version of DesignCompiler(DC),the"NoDefaultX"and"DefaultX"variationsweresynthesizedusingbothversions(explicitDCversionsarenotedin0),butwhenwesawabsolutelynodifferenceinsynthesizedresults,wequit using the2015version and synthesized all of the coding variations onlyusing the2018versionofDC.

SynthesiscompilationwasdoneusingtwoavailableASIClibraries,theLSI10Klibrary,whichhasbeenincludedinalloftheDCreleases,butwhichisalsoaratheroldlibrarywithlimitedmoderncapabilities.WealsousedanSAED32 (SynopsysArmeniaEducationalDepartment32nm) librarythatisincludedwithaSynopsysBitCoinonlineexample.

Default synthesiswasdonewithout any clocking goals andusing abstract enumerated types (noassignedstateencodings).Thenacreate_clock clk-period 0wasexecutedaftercompilingthedesign and before doingreport_area andreport_timing to show the default delay (negativeslack) through each design. Note that abstract enumerated types are assigned integer values bySystemVerilogstartingwiththefirststatelistedequaltozeroandeachsuccessivestateincrementingby1.Thesein‐orderbinarycountsaretypicallynotveryefficientwhensynthesized.

Basedonthedefaultdelays,acreate_clockcommandwasissuedwitharealisticclockperiodplusallinputsweregiven80%oftheclockstylewhilealloutputsweregiven20%oftheclockcycle.

Thesecond iterationofeachdesignusedsemi‐intelligentbinaryencodedvaluesassignedtoeachstateandsomeeffortwasmadetochooseencodingsthatwouldgiveGray‐liketransitionsasmuchaspossible.Thenthedesignswereagainsynthesized,firstwithnoclockgoalandthenwithclockinputandoutputdesignconstraints.

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Noneofthedesignsuptothispointusedcase‐defaultvaluessettoallX's(case-default‐X).InthetablesforeachFSMdesign,thesearereferredtoasthe"Nocase‐default‐X"values.

SinceaddingdefaultX'stoacasestatementissimilaraddingX'stoaK‐Map,defaultX‐valueswereassignedtonextstatesandoutputsinthecasestatementsandtheprevioussynthesisexerciseswererepeated.Thesearereferredtoasthe"DefaultX"valuesinthetables.

Thenextsynthesisiterationwastochangethenext = 'xassignmentstonext = stateandtoremovealloftheloopbackcodefromthecasestatements.Thetheorybeingtestedisthatsynthesismightimproveifthestatedoesnottransitionandiftheextracodeisremovedfromeachdesign.Thenthesynthesisrunswereexecutedagain.Thesearereferredtoasthe"DefaultX‐NoLoopback"valuesinthetables.

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8.1FSM1with4states,2outputsand2inputs

TheFSM1design,showninFigure10,hasanasynchronouslow‐truerst_n,twoinputsgoandws(waitstate),andtwooutputsrd(read)andds(donestrobe).

Figure10-FSM1statediagram

ThereisoneloopbackstateintheFSM1designandthatisintheIDLEstate.

ThecodingeffortforsmallFSMdesignsusingthedifferentstylesdoesnotdiffersignificantly,butitwilldifferdramaticallyasthenumberofstatesandoutputsincreases.

Figure11-fsm1-Codingstyleseffortcomparison

Figure11showstherelativecodingdifferencebetweenthefourcodingstyles.Thefullfsm1RTLcodeforallfourcodingstylesusedinFigure11areshowninAppendix2.2‐Appendix2.5.Thefsm1_pkgfileswithbothabstractandbinaryencodedtypedef[s]thatwereusedbyallofthefsm1designsareshowninAppendix2.1.

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Table2-fsm1-Synthesisefficiencycomparisontable

Whenthefsm1designwassynthesized,therewerealmostnodifferenceswhenstateencodingsandpre‐default‐Xvalueswereadded.Alsotherewasnonoticeabledifferencewhentheloopbackcodewasdeleted.Inthisdesign,the1‐alwaysblockcodingstylehadslightlybettersynthesisresultsthanthe3‐alwaysblockstyle,andthe4‐alwaysblockstylesynthesisresultsmatchedthe1‐alwaysblocksynthesisresults.SincethisFSMdesignhasfourstatesandsincetwobitswereusedtocreateallpossibleuniqueencodingsforeachstate,itisnotsurprisingthataddingdefault‐Xassignmentsdidnotnoticeablyimprovethesynthesisresults.Weexpectpre‐default‐Xassignmentswillprovemoreusefulwhenthenumberofstatesisnotapowerof2.

Figure12-fsm1-Linesofcode

Design Compiler O‐2018.06‐SP4 LSI 10K Library ‐ lsk_10k

RTL RTL RTL

Enums LOC* Area Slack Area Slack LOC* Area Slack Area Slack LOC* Area Slack Area Slack

fsm1_1 Abstract 39 52 ‐5.57 52 0.04 44 50 ‐5.19 49 0.04 42 50 ‐5.36 51 0.04

fsm1_2 Abstract 34 32 ‐4.89 38 (1.68) 39 31 ‐4.94 35 (1.37) 38 28 ‐5.18 35 (1.37)

fsm1_3 Abstract 38 49 ‐6.37 49 0.03 41 49 ‐6.37 49 0.03 40 49 ‐6.37 57 0.04

fsm1_4 Abstract 48 52 ‐5.57 52 0.04 50 52 ‐5.57 52 0.04 49 53 ‐5.10 52 0.04

fsm1_1 Encoded 39 44 ‐4.08 44 0.04 44 44 ‐4.08 44 0.04 42 44 ‐4.08 44 0.04

fsm1_2 Encoded 34 26 ‐4.09 28 (1.16) 39 26 ‐4.09 28 (1.16) 38 26 ‐4.09 27 (1.16)

fsm1_3 Encoded 38 44 ‐5.06 45 0.04 41 44 ‐5.06 45 0.04 40 44 ‐5.06 45 0.04

fsm1_4 Encoded 48 44 ‐4.08 44 0.04 50 44 ‐4.08 44 0.04 49 44 ‐4.08 44 0.04

LOC* ‐ Lines Of Code (not including imported enums)

RTL RTL RTL

Abstract LOC* Area Slack Area Slack LOC* Area Slack Area Slack LOC* Area Slack Area Slack

fsm1_1 Abstract 39 51 ‐0.42 54 0.00 44 51 ‐0.40 52 0.00 42 52 ‐0.39 54 0.00

fsm1_2 Abstract 34 34 ‐0.38 54 (0.12) 39 34 ‐0.40 42 (0.09) 38 32 ‐0.40 43 (0.09)

fsm1_3 Abstract 38 48 ‐0.50 49 0.00 41 48 ‐0.50 49 0.00 40 48 ‐0.50 48 0.00

fsm1_4 Abstract 48 51 ‐0.42 54 0.00 50 51 ‐0.42 54 0.00 49 50 ‐0.40 52 0.00

fsm1_1 Encoded 39 42 ‐0.38 44 0.00 44 42 ‐0.38 44 0.00 42 42 ‐0.37 44 0.00

fsm1_2 Encoded 34 26 ‐0.35 31 (0.06) 39 26 ‐0.35 31 (0.06) 38 26 ‐0.35 29 (0.06)

fsm1_3 Encoded 38 42 ‐0.41 45 0.00 41 42 ‐0.41 45 0.00 40 42 ‐0.41 45 0.00

fsm1_4 Encoded 48 42 ‐0.37 44 0.00 50 42 ‐0.37 44 0.00 49 42 ‐0.38 44 0.00

No case‐default‐X / Explicit loopback case‐default‐X / Explicit loopback case‐default‐X / Implicit loopback

Design Compiler O‐2018.06‐SP4

No Clock Goal Clock Goal 7.5

No Clock Goal Clock Goal 0.65

case‐default‐X / Implicit loopback

SAED Library ‐ saed32rvt_ss0p95v125c.db

No Clock Goal Clock Goal 7.5 No Clock Goal Clock Goal 7.5

No Clock Goal Clock Goal 0.65 No Clock Goal Clock Goal 0.65

No case‐default‐X / Explicit loopback case‐default‐X / Explicit loopback

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Figure13-fsm1-Codinggoalssummary

ItisapparentfromFigure12thatthecodingstylesareratherequal.

8.2FSM7with10states,1outputand2inputs

TheFSM7designhasanasynchronouslow‐truerst_n,twoinputsgoandjmp(jump),andjustoneoutputy1.

Thereareloopbackstatesinthefsm7diagraminstatesS0andS3.

ThecodingeffortforthisFSMdesignusingthedifferentstylesdoesstarttoshowthatthe1‐alwaysblockcodingeffortisstartingtogetverbose.ThisdesignissomewhatcontrivedbecausemostFSMdesignswith10stateswouldhavemultipleoutputsandmultipletransitionarcs,sowedonotyetseethefullimpactofthe1‐alwaysblockcodingstyle.


Ascanbeseenfromthefsm7design,the1‐alwaysblockcodingstylerequired46%morecodethantheequivalent3‐alwaysblockcodingstyle.

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Whenthefsm7designwassynthesized,therewassomeareaandperformanceadvantageusingthe1‐always block coding style over the 3‐always block coding style as shown in Table 3. This ispresumably due to the fact that the registered outputs for the 3‐always block coding style arecalculated from thenext state values as opposed to using the same inputs tests to calculate theclockedoutputs for the1‐alwaysblockstyle.Noteworthy is the fact that the4‐alwaysblockstylesynthesisresultswereactuallyslightlybetterthanthe3‐alwaysblocksynthesisresults.Thefullfsm7RTLcodeforthecodingstylesusedinFigure15areshowninAppendix2.7‐Appendix2.10.Thefsm7_pkgfileswithbothabstractandbinaryencodedtypedef[s]thatwereusedbyallofthefsm7designsareshowninAppendix2.6.

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RTL RTL RTL


fsm7_1 Abstract 69 100 ‐7.60 153 0.00 73 94 ‐7.48 105 0.11 70 89 ‐7.42 97 0.06

fsm7_2 Abstract 41 76 ‐8.10 118 (1.48) 45 78 ‐6.87 112 (1.15) 43 78 ‐8.90 95 (1.15)

fsm7_3 Abstract 46 93 ‐8.92 164 (0.91) 47 89 ‐8.14 145 0.01 45 87 ‐7.82 127 0.02

fsm7_4 Abstract 57 95 ‐8.38 139 0.07 59 91 ‐7.79 118 0.03 57 87 ‐7.96 88 0.12

fsm7_1 Encoded 69 78 ‐6.54 89 0.11 73 73 ‐6.15 77 0.24 70 79 ‐7.37 93 0.07

fsm7_2 Encoded 41 61 ‐5.79 83 (1.44) 45 61 ‐6.50 68 (1.15) 43 66 ‐7.68 78 (1.29)

fsm7_3 Encoded 46 73 ‐5.20 71 0.24 47 73 ‐5.20 71 0.24 45 77 ‐7.30 93 0.06

fsm7_4 Encoded 57 77 ‐5.32 78 0.19 59 73 ‐5.20 71 0.24 57 82 ‐7.69 84 0.14


RTL RTL RTL


fsm7_1 Abstract 69 122 ‐0.77 126 0.00 73 101 ‐0.63 107 0.00 70 96 ‐0.68 102 0.00

fsm7_2 Abstract 41 80 ‐0.68 108 (0.11) 45 87 ‐0.61 109 (0.07) 43 82 ‐0.71 95 (0.07)

fsm7_3 Abstract 46 100 ‐0.73 113 0.00 47 95 ‐0.65 101 (0.01) 45 92 ‐0.62 122 0.00

fsm7_4 Abstract 57 105 ‐0.70 125 0.00 59 103 ‐0.65 107 0.00 57 96 ‐0.68 107 0.00

fsm7_1 Encoded 69 89 ‐0.60 96 0.00 73 80 ‐0.48 85 0.00 70 86 ‐0.62 87 0.00

fsm7_2 Encoded 41 65 ‐0.49 86 (0.08) 45 70 ‐0.57 70 (0.07) 43 74 ‐0.73 91 (0.07)

fsm7_3 Encoded 46 80 ‐0.47 79 0.00 47 80 ‐0.47 79 0.00 45 90 ‐0.57 89 0.00

fsm7_4 Encoded 57 86 ‐0.44 84 0.00 59 80 ‐0.47 79 0.00 57 90 ‐0.74 90 0.00






Clock Goal 0.65

No Clock Goal Clock Goal 8.5No Clock Goal Clock Goal 8.5 No Clock Goal Clock Goal 8.5


No Clock Goal Clock Goal 0.65 No Clock Goal Clock Goal 0.65 No Clock Goal

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ItisapparentfromFigure16thatthe1‐alwaysblockcodingstyleissignificantlymoreverbosethanthe3‐alwaysblockcodingstyleandthatthe1‐alwaysblockcodeisgettinghardertofollowallofthenext‐outputassignments.

Wehaveagainnotedthatthe1‐alwaysblockcodingstylemightnotbesoeasytochangeduetoFSMchanges.

8.2.1Whyis1alwaysblockmoreverbosethan3alwaysblock?

Whenwe originally examined different FSM coding stylesmore than 15 years ago,weweresurprisedtoobservethatlarger1‐alwaysblockFSMRTLcodedexamplesweresignificantlymoreverbose than 3‐always block coded examples. Based on the names of the styles, this seemedcounterintuitive.Afterall,whichsoundsbigger?1‐alwaysblockor3‐alwaysblocks?

Uponcloserexaminationwenotedthatthe2‐alwaysblockand3‐alwaysblockRTLcodingstylesassigntheoutputsonceperstate,whilethe1‐alwaysblockstyleassignedtheoutputsoncepertransitionarctoeachstate.

Figure18-FSM7statediagram-whyisthe1-alwaysblockstylesoverbose?

IntheFSM7design,asshowninFigure18,theworstcasestateisS3.EverystateinthisFSMdesignthattransitionstostateS3mustsetstate <= S3andalsochangetheoutputassignmentbysettingy1 <= '1.Thesetwoassignmentsmustbeencapsulatedwithinbegin‐endstatements.ThismeansthateachtransitionarctostateS3mustincludethesefourlinesofcode.Thiscontributestotherapidcode‐explosionthatissocommonwhenusingthe1‐alwaysblockcodingstyle.

IntheRTLcodeshowninExample11,itcanbeseenthattherearefourlinesofcodeforeachstateinthecasestatementthatarenearlyidentical.ForeachtransitiontostateS3,theassignmenty1 <= '1isrequiredandthestate <= S3assignmentisalsorequired.Thesetwoassignmentsmustalsobesurroundedbybegin‐end.Thesefourlinesofcode,addedtoeachcaseitem,quicklyaddmanylinesofcodetothecasestatement.

always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin state <= S0; y1 <= '0; end else begin

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state <= XX; y1 <= '0; case (state) S0 : if (go && jmp) begin y1 <= '1; state <= S3; end else if (go && !jmp) state <= S1; else state <= S0; //@ looopback S1 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S2; S2 : begin y1 <= '1; state <= S3; end S3 : if (!jmp) state <= S4; else begin y1 <= '1; state <= S3; //@ loopback end S4 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S5; S5 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S6; S6 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S7; S7 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S8; S8 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S9; S9 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S0; default: begin y1 <= 'x; state <= XX; end endcase

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end endmodule

Example11-fsm7_1-1-alwaysblockstyleoutputassignmentsforeachtransitionarc

Thedifferencebecomesmorepronouncedwhentherearemorestates,multipleoutputassignmentsandmoretransitionarcsasshownintheFSM8designofSection8.3.

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8.3FSM8with10states,3outputsand2inputs

TheFSM8designhasanasynchronouslow‐truerst_n,fourinputsgo,sk1,sk0andjmp(jump),andthreeoutputsy3,y2andy1.


Ascanbeseenfromthefsm8design,the1‐alwaysblockcodingstylerequired84%morecodethantheequivalent3‐alwaysblockcodingstyle.


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Surprisingly, when the fsm8 design was synthesized, there was some area and performanceadvantageusingthe3‐alwaysblockcodingstyleoverthe1‐alwaysblockand4‐alwaysblockcodingstylesasshowninTable4.ThisobservationsuggeststhatfirstcodingFSMdesignsusingtheconciseand efficient 3‐always block style and then copying the code to incorporate the 4‐always blockmodificationsisagoodstrategy.Thecopied4‐alwaysblockstyletypicallywillhavebettersynthesisresultsthanthe3‐alwaysblockstyle,butnotalways.

Thefullfsm8RTLcodeforthecodingstylesusedinFigure20areshowninAppendix2.11‐Appendix2.11.Thefsm8_pkgfileswithbothabstractandbinaryencodedtypedef[s]thatwereusedbyallofthefsm8designsareshowninAppendix2.11.


RTL RTL RTL


fsm8_1 Abstract 136 147 ‐10.66 220 0.03 142 163 ‐8.63 207 0.00 138 149 ‐8.37 179 0.15

fsm8_2 Abstract 70 105 ‐10.57 190 (2.99) 76 100 ‐7.88 150 (1.95) 73 98 ‐8.62 141 (1.87)

fsm8_3 Abstract 72 140 ‐14.81 284 (0.72) 73 133 ‐11.50 229 (1.38) 70 139 ‐12.62 246 (1.39)

fsm8_4 Abstract 98 155 ‐10.11 261 (0.03) 100 157 ‐9.02 190 0.02 97 162 ‐10.45 210 0.01

fsm8_1 Encoded 136 140 ‐11.38 213 (0.09) 142 164 ‐7.85 195 0.02 138 175 ‐8.73 198 0.03

fsm8_2 Encoded 70 94 ‐7.95 154 (2.70) 76 85 ‐7.19 130 (2.16) 73 95 ‐9.57 141 (1.69)

fsm8_3 Encoded 72 128 ‐11.55 224 0.01 73 128 ‐11.55 224 0.01 70 146 ‐11.90 270 (0.95)

fsm8_4 Encoded 98 143 ‐8.64 180 0.01 100 164 ‐7.85 195 0.02 97 174 ‐8.02 220 0.00


RTL RTL RTL


fsm8_1 Abstract 136 170 ‐0.84 185 0.00 142 180 ‐0.75 195 0.00 138 177 ‐0.90 186 0.00

fsm8_2 Abstract 70 119 ‐0.80 166 (0.17) 76 120 ‐0.74 142 (0.12) 73 124 ‐0.66 148 (0.09)

fsm8_3 Abstract 72 154 ‐1.15 210 (0.05) 73 150 ‐1.07 173 (0.01) 70 152 ‐1.19 177 0.00

fsm8_4 Abstract 98 178 ‐0.84 199 0.00 100 177 ‐0.84 187 0.00 97 185 ‐0.82 181 0.00

fsm8_1 Encoded 136 160 ‐0.86 177 0.00 142 193 ‐0.69 197 0.00 138 212 ‐0.71 211 0.00

fsm8_2 Encoded 70 116 ‐0.72 145 (0.16) 76 97 ‐0.53 150 (0.15) 73 116 ‐0.85 141 (0.11)

fsm8_3 Encoded 72 140 ‐0.93 176 0.00 73 140 ‐0.93 176 0.00 70 171 ‐0.97 243 (0.01)

fsm8_4 Encoded 98 164 ‐0.74 172 0.00 100 193 ‐0.69 197 0.00 97 220 ‐0.69 222 0.00






No Clock Goal Clock Goal 9.0No Clock Goal Clock Goal 9.0 No Clock Goal Clock Goal 9.0


No Clock Goal Clock Goal 0.8 No Clock Goal Clock Goal 0.8 No Clock Goal Clock Goal 0.8

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WeseeinFigure21andFigure22thatthe1‐alwaysblockcodingstyleissignificantlymoreverbosethan the 3‐always block coding style and that the 1‐always block code is getting even harder tounderstandallof thenext‐outputassignments,whileagainnoting that the1‐alwaysblockand4‐alwaysblockcodingstyleswerenotnecessarilymoreefficientwhensynthesized.

Wehavealsonotedthatthe1‐alwaysblockcodingstylemightnotbeveryeasytochangeduetoFSMchanges.

8.4Prep4FSMdesignwith16states,8-bitoutputand8-bitinput

ThePrep4designhasanasynchronouslow‐truerst_n,one8‐bitinputi,andone8‐bitoutputo.

Figure23-Prep4statediagram

AscanbeseeninFigure24fortheprep4design,the1‐alwaysblockcodingstylerequiredmorethantwiceasmuchcode(114%morecode)thantheequivalent3‐alwaysblockcodingstyle.

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Figure24-prep4-Codingstyleseffortcomparison

Table5-prep4-Synthesisefficiencycomparisontable

Itshouldbenotedthattheoutputsinthisprep4designareshowninvectorformforeachstate,sotheeasiestwaytocodetheoutputsinthisFSMdesignwastoassigntheoutputvectorforeachstateandnotmakedefault‐Xoutputassignments.Sincetheoutputsarecalculatedfromeachnextstate,theareaincreasedsignificantlywhensynthesized.Thefullprep4RTLcodeforthecodingstylesusedinFigure24areshowninAppendix2.17‐Appendix2.20.Theprep4_pkgfileswithbothabstractandbinaryencodedtypedef[s]thatwereusedbyalloftheprep4designsareshowninAppendix2.16.

RTL RTL RTL


prep4_1 Abstract 188 304 ‐10.96 421 0.00 192 303 ‐11.17 353 0.04 182 334 ‐11.03 451 0.00

prep4_2 Abstract 115 201 ‐9.44 345 (4.65) 119 199 ‐9.06 312 (4.91) 110 222 ‐13.57 360 (2.54)

prep4_3 Abstract 90 285 ‐16.32 476 (1.58) 92 281 ‐14.27 511 (0.62) 83 297 ‐16.30 497 (2.09)

prep4_4 Abstract 126 328 ‐12.09 453 (0.34) 128 304 ‐11.49 419 0.02 118 340 ‐12.64 487 0.00

prep4_1 Encoded 188 297 ‐10.69 363 0.01 192 297 ‐12.32 353 0.00 182 355 ‐14.89 423 0.02

prep4_2 Encoded 115 198 ‐9.01 357 (4.84) 119 202 ‐10.11 310 (5.08) 110 222 ‐13.22 360 (3.10)

prep4_3 Encoded 90 278 ‐15.89 491 (1.61) 92 291 ‐15.37 580 (1.14) 83 293 ‐17.42 491 (2.68)

prep4_4 Encoded 126 302 ‐11.61 346 0.04 128 297 ‐11.11 361 0.01 118 350 ‐11.62 458 0.01


RTL RTL RTL


prep4_1 Abstract 188 369 ‐0.85 373 0.00 192 398 ‐0.78 395 0.00 182 441 ‐0.90 494 (0.01)

prep4_2 Abstract 115 276 ‐0.66 345 (0.34) 119 275 ‐0.69 327 (0.29) 110 314 ‐0.95 355 (0.20)

prep4_3 Abstract 90 354 ‐1.19 448 (0.09) 92 367 ‐1.21 408 (0.08) 83 377 ‐1.40 526 (0.11)

prep4_4 Abstract 126 409 ‐0.79 400 0.00 128 399 ‐0.81 401 0.00 118 438 ‐1.02 478 (0.08)

prep4_1 Encoded 188 383 ‐0.73 386 0.00 192 379 ‐0.87 368 0.00 182 456 ‐0.92 488 0.00

prep4_2 Encoded 115 267 ‐0.65 376 (0.33) 119 272 ‐0.69 339 (0.32) 110 315 ‐0.83 368 (0.26)

prep4_3 Encoded 90 358 ‐1.14 469 (0.14) 92 355 ‐1.19 426 (0.05) 83 368 ‐1.34 529 (0.09)

prep4_4 Encoded 126 383 ‐0.86 371 (0.01) 128 379 ‐0.87 399 0.00 118 463 ‐0.98 493 (0.01)


Clock Goal 0.8





No Clock Goal Clock Goal 11Clock Goal 11No Clock Goal Clock Goal 11 No Clock Goal


No Clock Goal Clock Goal 0.8 No Clock Goal No Clock Goal Clock Goal 0.8

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Figure25-prep4-Linesofcode

Figure26-prep4-Codinggoalssummary

AsseeninFigure25,the1‐alwaysblockcodingstyleismorethantwiceasverboseasthe3‐alwaysblockcodingstyleandthe1‐alwaysblockcodeisgettingmuchhardertofollowwhenexaminingthenext‐outputassignments.

WehaveagainnotedinFigure26thatthe1‐alwaysblockcodingstyleisnotsoeasytochangeduetoFSMchanges.

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9.Comparisons&SummarySystemVerilogcodingstyleshelpfacilitatepropersimulationandunderstandingoftheFSMcodingstyles.Belowisalistofitemsthatwereidentifiedaschecklistitemsinthispaper.AftercodingyourFSMdesign,werecommendcompareyourcodeagainsttheitemsinthischecklist.

Checklistitem:EngineersshouldgenerallydeclareallFSMportsandallFSMinternalsignalstobeoftypelogic.

Checklistitem:Whereeverpossible,usetheSystemVerilog'0/'1/'xtomakeassignments.

Checklistitem:Declareallportstobeoftypelogic.Extrapointsforlistingoutputsfollowedbyinputsfollowedbycontrolinputs.Extrapointsforgroupingmultiplesignalsintoeachoutputandinputportlistdeclaration.

Checklistitem:Declarethestateandnextvariablesusingenumeratedtypes.AddanXXorXXXstatetohelpdebugthedesignandtohelpoptimizethesynthesizedresult.

Checklistitem:Usealways_ffandalways_combprocedurestoinferclockedandcombinatoriallogic.DonotusetheolderVerilogalwaysprocedures.

Checklistitem:Declarethestateregisterusingjust3linesofcodeandplaceitatthetopofthedesignaftertheenumeratedtypedeclaration.

Checklist item: Use a default next='x or next=state default assignment at the top of thealways_combprocedure.Startbyfirstusingthenext='xstyletohelpdebugtheFSMdesign.

Checklistitem:ExtrapointsforusingnextinsteadofusingnextstateintheFSMdesign,butbothworkfine.

Checklistitem:ExtrapointsforplacingthenextassignmentsinaneatcolumnintheFSMRTLcode.

Checklistitem:Placedefaultoutputassignmentsbeforetheoutput‐assignmentcasestatementandthentoupdatetheappropriateoutputsforeachstatewheretheoutputschange.

When comparing the coding effort for the four coding styles (1‐always block, 2‐always block, 3‐alwaysblockand4‐alwaysblock)the1‐alwaysblockcodingstyleisveryverboseandincreasesinsizequicklywithmorestatesandoutputs.Forthelargerprep4design,thecodingeffortwasmorethantwiceashardascodingthe3‐alwaysblockstyle.

Itwasalso interestingtonotethatthe3‐alwaysblockstyle frequentlyrequiredlesscodingeffortthanthe2‐alwaysblockstylewithcombinatorialoutputs.

The1‐alwaysblockand4‐alwaysblockcodingstylestypicallygaveslightlybettersynthesisareaandtimingperformanceoverthe3‐alwaysblockstyle,butwerecommendusingtheefficient3‐alwaysblockstyleandthenconvertingittoa4‐alwaysblockstyleifslightlybettersynthesisperformanceisneeded.

Inlaterpublications,wewillcomparethesestylestoOneHotandoutputencodedFSMcodingstylestoseeiftheimprovedareaandtimingtrendcontinues.

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10.AcknowledgementsWearegratefultogoodfriendandcolleaguePaulZimmer,creatoroftheFizZimFSMdiagramandcodegenerationtool[16],forhisreviewandvaluablesuggestionstohelpimprovethispaper.

Wealsothankourgoodfriendandcolleague,SteveGolson,forhisrecommendationstousenewertechnologylibrariesandtouseinputandoutputdesignconstraintswithourFSMdesigns.

WE also thank Jing Zhan, Robert Lombardi and Benny Widen for their valuable feedback andsuggestionsregardingthepaperandpresentation.

WethankWillCummingsofSynopsysforhishelpwithusingtheSynplifyProandSynplifyPremierFPGAsynthesistools.

11.References[1] ArmeniaEducationalPrograms‐SAED:SynopsysArmeniaEducationalDepartment

https://www.synopsys.com/company/contact‐synopsys/office‐locations/armenia/armenia‐educational‐program.html

[2] CliffordE.Cummings,"SynthesizableFiniteStateMachineDesignTechniquesUsingtheNewSystemVerilog3.0Enhancements,"SNUGhttp://www.sunburst‐design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf

[3] CliffordE.Cummings,“SystemVerilogAssertions‐Bindfiles&BestKnownPracticesforSimpleSVAUsage,”SNUG2016(SiliconValley).http://www.sunburst‐design.com/papers/CummingsSNUG2016SV_SVA_Best_Practices.pdf

[4] CliffordE.Cummings,"SystemVerilogLogicSpecificProcessesforSynthesis‐BenefitsandProperUsage,"SNUGhttp://www.sunburst‐design.com/papers/CummingsSNUG2016SV_SVLogicProcs.pdf

[5] DejanMarković,"LogicSynthesis‐Lecture11,"EEM216ALectureSlides,Fall2012http://icslwebs.ee.ucla.edu/dejan/researchwiki/images/0/0c/F2012‐Lec‐11_Logic‐Synthesis.pdf

[6] HarryFoster,"Part5:The2010WilsonResearchGroupFunctionalVerificationStudy,"(SeeFigure2‐32%Debug)https://blogs.mentor.com/verificationhorizons/blog/2011/04/04/part‐5‐the‐2010‐wilson‐research‐group‐functional‐verification‐study/





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[12] HarryFoster,"Part4:The2018WilsonResearchGroupFunctionalVerificationStudy,"(SeeFigure4‐2‐42%Debug)https://blogs.mentor.com/verificationhorizons/blog/2019/01/02/part‐4‐the‐2018‐wilson‐research‐group‐functional‐verification‐study/

[13] IEEEStandardHardwareDescriptionLanguageBasedontheVerilogHardwareDescriptionLanguage,IEEEComputerSociety,IEEE,NewYork,NY,IEEEStd1364‐1995

[14] IEEEStandardVerilogHardwareDescriptionLanguage,IEEEComputerSociety,IEEE,NewYork,NY,IEEEStd1364‐2001

[15] "IEEEStandardForSystemVerilog‐UnifiedHardwareDesign,SpecificationandVerificationLanguage,"IEEEComputerSocietyandtheIEEEStandardsAssociationCorporateAdvisoryGroup,IEEE,NewYork,NY,IEEEStd1800™‐2017

[16] PaulZimmer,MichaelZimmer,BrianZimmer,"FizZim‐anopen‐sourceFSMdesignenvironment,"http://www.fizzim.com/mydownloads/fizzim_tutorial_20160423.pdf

[17] SAEDTechnologyLibraries‐SolvNet,"BitcoinLowPowerCaseStudy,"(downloadTechnologyLibraries)https://solvnet.synopsys.com/retrieve/2630223.html

[18] SteveGolson,"StateMachineDesignTechniquesforVerilogandVHDL,"SynopsysJournalofHigh‐LevelDesign,September1994,pp.1‐48.

Lines of Code Web References:

[19] AmyBowersox,"Howtrueisthefollowing:"Everylineofcodeisabug"?,"https://www.quora.com/How‐true‐is‐the‐following‐Every‐line‐of‐code‐is‐a‐bug

[20] ChadPerrin,"Thedangerofcomplexity:Morecode,morebugs,"https://www.techrepublic.com/blog/it‐security/the‐danger‐of‐complexity‐more‐code‐more‐bugs/

[21] CharlesBrianQuinn,"LessCodeisBetter,"https://www.bignerdranch.com/blog/less‐code‐is‐better/

[22] CliffordE.Cummings,"TheSunburstDesign‐"Where'sWaldo"PrincipleofVerilogCoding,"http://www.sunburst‐design.com/papers/Wheres_Waldo_Coding.pdf

[23] JackGanssle,"KeepItSmall,"http://www.ganssle.com/articles/keepsmall.htm

[24] Quora,"Isthereacorrelationbetweenthenumberoflinesofcodeandthenumberofbugsinsoftware?,"https://www.quora.com/Is‐there‐a‐correlation‐between‐the‐number‐of‐lines‐of‐code‐and‐the‐number‐of‐bugs‐in‐software

[25] SoftwareEngineering,"Morecode=morebugs,"https://softwareengineering.stackexchange.com/questions/41949/more‐code‐more‐bugs

[26] SteveBaker,"Whatistheaverageratioofbugstoalineofcode?,"https://www.quora.com/What‐is‐the‐average‐ratio‐of‐bugs‐to‐a‐line‐of‐code

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12.Author&ContactInformationCliffCummings,PresidentofSunburstDesign,Inc.,isanindependentEDAconsultantandtrainerwith38yearsofASIC,FPGAandsystemdesignexperienceand28yearsofSystemVerilog,synthesisandmethodologytrainingexperience.

Mr.Cummingshaspresentedmorethan100SystemVerilogseminarsandtrainingclassesinthepast17yearsandwasthefeaturedspeakerattheworld‐wideSystemVerilogNOW!seminars.

Mr. Cummings participated on every IEEE & Accellera SystemVerilog, SystemVerilog Synthesis,SystemVerilog committee from 1994‐2012, and has presented more than 50 papers onSystemVerilog&SystemVerilogrelateddesign,synthesisandverificationtechniques.

Mr. Cummings holds a BSEE from Brigham Young University and an MSEE from Oregon StateUniversity.

Sunburst Design, Inc. offers World Class Verilog & SystemVerilog training courses. For moreinformation,visitthewww.sunburst‐design.comwebsite.

Emailaddress:cliffc@sunburst‐design.com

HeathChambersisPresidentofHMCDesignVerification,Inc.,acompanythatspecializesindesignandverificationconsultingandhigh tech training.Mr.Chambers isa consultantwith23yearsofVerilogExperience16yearsofSystemVerilogexperience,19yearsofconsultingandverificationleadexperienceformultipleprojectsandhasbeenaninstructorforSunburstDesignsincetheyear2000.Heathhas18yearsofSystemVerilog,Verilog,synthesisandUVMVerificationmethodologytrainingexperience for Sunburst Design, Inc., and was previously a contract Specman Basic Traininginstructor for Verisity. Heath has ASIC and system verification, firmware, and self‐test designexperience and is capable of answering the very technical questions asked by experiencedverificationengineers.

Mr. Chambers,was amemberof the IEEE1364Verilog and IEEE1800SystemVerilog StandardsGroups from 2000 to 2012, and has helped to develop and improve Sunburst Design Verilog,SystemVerilog,UVMandsynthesistrainingcourses.

Mr.ChambersspecializesinverificationofASICsandsystemsusingtop‐downdesignmethodologiesand is proficient in SystemVerilog,Verilog,UVM, 'e', C, andPerl.Mr. Chambers specializes in theQuesta,Cadence,Synopsyssimulationtools.

Before becoming an independent Consultant, Mr. Chambers worked for Hewlett‐Packard doingverificationofmulti‐milliongateASICsandsystemscontainingmultiplechips.Mr.Chamberswastheleadverificationengineerforthelasttwoprojectsheworkedonbeforeleavingthecompany.

Mr.ChambersholdsaBSCSfromNewMexicoInstituteofMiningandTechnology.

Emailaddress:[email protected]

LastUpdated:February2019

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ToolsandOSversionsTheabilityofVerilogandSystemVerilogtoolsusedtosimulateFSMdesignstypicallydoesnotchangewith simulation tool versions. Simulation of FSM designs is a well‐established task that has notchangedintheforeseeablepast.

Ontheotherhand,synthesisresultscontinuetoevolvewithdifferenttoolversionsandhaschangedsignificantlyovertheyears.

TheexamplesinthispaperwererunusingthefollowingLinuxandSynopsystoolversions:

64‐bitLinuxlaptop:CentOSrelease6.5

VCSversionN‐2017.12‐SP1_Full64

Runningvcsanddveeachrequiredthecommandlineswitch‐full64

Withoutthe‐full64commandlineswitch,vcscompilationwouldfailwiththemessage:error while loading shared libraries: libelf.so.1: cannot open shared object file: No such file or directory.

DesignCompilerversionsO‐2018.06‐SP4andK‐2015.06‐SP4

SynplifyPremierversionO‐2018.09‐SP1

SynthesisLibraries:

LSI10K‐oldsynthesislibrarythatshipswithDesignCompiler

SAED32

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FSMbenchmarksourcecodeThesourcecodefortheFSM1,FSM7,FSM8andPrep4sourcefilesareincludedinthisappendix.

FSM1-fsm1_pkgsforabstractandbinaryencodedenums

The[a]bstractenumerated typespackage file isnamedfsm1_pkg_a.svbut thepackagename isfsm1_pkg.

package fsm1_pkg; typedef enum {IDLE, READ, DLY, DONE, XXX } state_e; endpackage

Example12-File:fsm1_pkg_a.sv-fsm1_pkgenumeratedtypedef

The [b]inary encoded enumerated types package file is namedfsm1_pkg_b.sv but the packagenameisstillfsm1_pkg.

package fsm1_pkg; typedef enum logic [1:0] {IDLE = 2'b00, READ = 2'b01, DLY = 2'b11, DONE = 2'b10, XXX = 'x } state_e; endpackage

Example13-File:fsm1_pkg_b.sv-fsm1_pkgenumeratedtypedef

Thesepackagesincludeatypedefforthestate_etypethatisusedbyallofthefsm1designs.

Usingthesamepackagenamemakesitpossibletoreadtheseparatepackagefilesfirstinasimulationandfirstinsynthesiscompilationtoselectivelychooseabstractorbinaryencodedenumeratedtypeswithouttouchingthefsm1files.

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FSM1-1alwaysblockRTL-NOTRecommended-RegisteredOutputs

module fsm1_1x ( output logic rd, ds, input logic go, ws, clk, rst_n); import fsm1_pkg::*; state_e state; always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin state <= IDLE; rd <= '0; ds <= '0; end else begin state <= XXX; //@ LB rd <= '0; ds <= '0; case (state) IDLE : if (go) begin rd <= '1; state <= READ; end else state <= IDLE; //@ LB READ : begin rd <= '1; state <= DLY; end DLY : if (!ws) begin ds <= '1; state <= DONE; end else begin rd <= '1; state <= READ; end DONE : state <= IDLE; default: begin ds <= 'x; rd <= 'x; state <= XXX; end endcase end endmodule

Example14-fsm1_1x-1-alwaysblockwithregisteredoutputs

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FSM1-2alwaysblockRTL-Recommended-CombinatorialOutputs

module fsm1_2x ( output logic rd, ds, input logic go, ws, clk, rst_n); import fsm1_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= IDLE; else state <= next; always_comb begin next = XXX; //@LB next = state; rd = '0; ds = '0; case (state) IDLE : if (go) next = READ; else next = IDLE; //@ LB READ : begin rd = '1; next = DLY; end DLY : begin rd = '1; if (!ws) next = DONE; else next = READ; end DONE : begin ds = '1; next = IDLE; end default: begin ds = 'x; rd = 'x; next = XXX; end endcase end endmodule

Example15-fsm1_2x-2-alwaysblockwithcombinatorialoutputs

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module fsm1_3x ( output logic rd, ds, input logic go, ws, clk, rst_n); import fsm1_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= IDLE; else state <= next; always_comb begin next = XXX; //@LB next = state; case (state) IDLE : if (go) next = READ; else next = IDLE; //@ LB READ : next = DLY; DLY : if (!ws) next = DONE; else next = READ; DONE : next = IDLE; default: next = XXX; endcase end always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin rd <= '0; ds <= '0; end else begin rd <= '0; ds <= '0; case (next) IDLE : ; READ : rd <= '1; DLY : rd <= '1; DONE : ds <= '1; default: {rd,ds} <= 'x; endcase end endmodule

Example16-fsm1_3x-3-alwaysblockstylewithregisteredoutputs

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FSM1-4alwaysblockRTL-Recommended-RegisteredOutputs

module fsm1_4x ( output logic rd, ds, input logic go, ws, clk, rst_n); logic n_rd, n_ds; // next combinatorial outputs import fsm1_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= IDLE; else state <= next; always_comb begin next = XXX; //@LB next = state; case (state) IDLE : if (go) next = READ; else next = IDLE; //@ LB READ : next = DLY; DLY : if (!ws) next = DONE; else next = READ; DONE : next = IDLE; default: next = XXX; endcase end always_comb begin n_rd = '0; n_ds = '0; case (state) IDLE : if ( go) n_rd = '1; // READ else ; // IDLE READ : n_rd = '1; // DLY DLY : if ( ws) n_rd = '1; // READ else n_ds = '1; // DONE DONE : ; // IDLE default: {n_rd,n_ds} = 'x; endcase end always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin rd <= '0; ds <= '0; end else begin rd <= n_rd; ds <= n_ds; end endmodule


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package fsm7_pkg; typedef enum {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, XX } state_e; endpackage



package fsm7_pkg; typedef enum logic [3:0] {S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0011, S3 = 4'b0010, S4 = 4'b0110, S5 = 4'b0111, S6 = 4'b0101, S7 = 4'b0100, S8 = 4'b1100, S9 = 4'b1000, XX = 'x } state_e; endpackage




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module fsm7_1x ( output logic y1, input logic jmp, go, clk, rst_n); import fsm7_pkg::*; state_e state; always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin state <= S0; y1 <= '0; end else begin state <= XX; //@ LB y1 <= '0; case (state) S0 : if (go && jmp) begin y1 <= '1; state <= S3; end else if (go && !jmp) state <= S1; else state <= S0; //@ LB S1 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S2; S2 : begin y1 <= '1; state <= S3; end S3 : if (!jmp) state <= S4; else begin y1 <= '1; state <= S3; //@ LB end S4 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S5; S5 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S6; S6 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S7; S7 : if (jmp) begin y1 <= '1; state <= S3; end

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else state <= S8; S8 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S9; S9 : if (jmp) begin y1 <= '1; state <= S3; end else state <= S0; default: begin y1 <= 'x; state <= XX; end endcase end endmodule


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module fsm7_2x ( output logic y1, input logic jmp, go, clk, rst_n); import fsm7_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; y1 = '0; case (state) S0 : if (go && jmp) next = S3; else if (go && !jmp) next = S1; else next = S0; //@ LB S1 : if (jmp) next = S3; else next = S2; S2 : next = S3; S3 : begin y1 = '1; if (!jmp) next = S4; else next = S3; //@ LB end S4 : if (jmp) next = S3; else next = S5; S5 : if (jmp) next = S3; else next = S6; S6 : if (jmp) next = S3; else next = S7; S7 : if (jmp) next = S3; else next = S8; S8 : if (jmp) next = S3; else next = S9; S9 : if (jmp) next = S3; else next = S0; default: begin y1 = 'x; next = XX; end endcase end endmodule

Example21-fsm7_2x-2-alwaysblockstylewithcombinatorialoutputs

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FSM7-3alwaysblock-Recommended-RegisteredOutputs

module fsm7_3x ( output logic y1, input logic jmp, go, clk, rst_n); import fsm7_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; case (state) S0 : if (go && jmp) next = S3; else if (go && !jmp) next = S1; else next = S0; //@ LB S1 : if (jmp) next = S3; else next = S2; S2 : next = S3; S3 : if (!jmp) next = S4; else next = S3; //@ LB S4 : if (jmp) next = S3; else next = S5; S5 : if (jmp) next = S3; else next = S6; S6 : if (jmp) next = S3; else next = S7; S7 : if (jmp) next = S3; else next = S8; S8 : if (jmp) next = S3; else next = S9; S9 : if (jmp) next = S3; else next = S0; default: next = XX; endcase end always_ff @(posedge clk, negedge rst_n) if (!rst_n) y1 <= '0; else begin y1 <= '0; case (next) S3 : y1 <= '1; endcase end endmodule


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module fsm7_4x ( output logic y1, input logic jmp, go, clk, rst_n); logic n_y1; // next combinatorial outputs import fsm7_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; case (state) S0 : if (go && jmp) next = S3; else if (go && !jmp) next = S1; else next = S0; //@ LB S1 : if (jmp) next = S3; else next = S2; S2 : next = S3; S3 : if (!jmp) next = S4; else next = S3; //@ LB S4 : if (jmp) next = S3; else next = S5; S5 : if (jmp) next = S3; else next = S6; S6 : if (jmp) next = S3; else next = S7; S7 : if (jmp) next = S3; else next = S8; S8 : if (jmp) next = S3; else next = S9; S9 : if (jmp) next = S3; else next = S0; default: next = XX; endcase end always_comb begin n_y1 = '0; case (state) S0 : if (go && jmp) n_y1 = '1; // S3 else ; // S0, S1 S2 : n_y1 = '1; // S3 S3 : if (!jmp) ; // S4 else n_y1 = '1; // S3 S1, S4, S5, S6, S7, S8, S9: if (jmp) n_y1 = '1; // S3 else ; // S2, S5, S6, S7, S8, S9, S0 default: n_y1 = 'x; endcase end

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always_ff @(posedge clk, negedge rst_n) if (!rst_n) y1 <= '0; else y1 <= n_y1; endmodule


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package fsm8_pkg; typedef enum {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, XX } state_e; endpackage



package fsm8_pkg; typedef enum logic [3:0] {S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0011, S3 = 4'b0010, S4 = 4'b0110, S5 = 4'b0111, S6 = 4'b0101, S7 = 4'b0100, S8 = 4'b1100, S9 = 4'b1000, XX = 'x } state_e; endpackage




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module fsm8_1x ( output logic y1, y2, y3, input logic jmp, go, sk0, sk1, clk, rst_n); import fsm8_pkg::*; state_e state; always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin y1 <= '0; y2 <= '0; y3 <= '0; state <= S0; end else begin y1 <= '0; y2 <= '0; y3 <= '0; state <= XX; //@ LB case (state) S0: if ( go && jmp) begin y1 <= '1; y2 <= '1; state <= S3; end else if ( go && !jmp) begin y2 <= '1; state <= S1; end else state <= S0; //@ LB S1 : if (jmp) begin y1 <= '1; y2 <= '1; state <= S3; end else state <= S2; S2 : if (jmp) begin y1 <= '1; y2 <= '1; state <= S3; end else begin y1 <= '1; y2 <= '1; y3 <= '1; state <= S9; end S3: if (!jmp) state <= S4; else begin y1 <= '1; y2 <= '1; state <= S3; //@ LB end S4 : if (jmp) begin y1 <= '1;

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y2 <= '1; state <= S3; end else if (sk0 && !jmp) begin y1 <= '1; y2 <= '1; y3 <= '1; state <= S6; end else state <= S5; S5 : if (jmp) begin y1 <= '1; y2 <= '1; state <= S3; end else if (!sk1 && !sk0 && !jmp) begin y1 <= '1; y2 <= '1; y3 <= '1; state <= S6; end else if (!sk1 && sk0 && !jmp) begin y3 <= '1; state <= S7; end else if (sk1 && !sk0 && !jmp) begin y2 <= '1; y3 <= '1; state <= S8; end else begin y1 <= '1; y2 <= '1; y3 <= '1; state <= S9; end S6 : if (jmp) begin y1 <= '1; y2 <= '1; state <= S3; end else if (go && !jmp) begin y3 <= '1; state <= S7; end else begin y1 <= '1; y2 <= '1; y3 <= '1; state <= S6; //@ LB end S7 : if (jmp) begin y1 <= '1; y2 <= '1; state <= S3; end else begin y2 <= '1;

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y3 <= '1; state <= S8; end S8 : if (jmp) begin y1 <= '1; y2 <= '1; state <= S3; end else begin y1 <= '1; y2 <= '1; y3 <= '1; state <= S9; end S9 : if (jmp) begin y1 <= '1; y2 <= '1; state <= S3; end else state <= S0; default: begin y1 <= 'x; y2 <= 'x; y3 <= 'x; state <= XX; end endcase end endmodule


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module fsm8_2x ( output logic y1, y2, y3, input logic jmp, go, sk0, sk1, clk, rst_n); import fsm8_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; y1 = '0; y2 = '0; y3 = '0; case (state) S0: if ( go && jmp) next = S3; else if ( go && !jmp) next = S1; else next = S0; //@ LB S1 : begin y2 = '1; if (jmp) next = S3; else next = S2; end S2 : if (jmp) next = S3; else next = S9; S3 : begin y1 = '1; y2 = '1; if (!jmp) next = S4; else next = S3; //@ LB end S4 : if (jmp) next = S3; else if (sk0 && !jmp) next = S6; else next = S5; S5 : if (jmp) next = S3; else if (!sk1 && !sk0 && !jmp) next = S6; else if (!sk1 && sk0 && !jmp) next = S7; else if ( sk1 && !sk0 && !jmp) next = S8; else next = S9; S6 : begin y1 = '1; y2 = '1; y3 = '1; if (jmp) next = S3; else if (go && !jmp) next = S7; else next = S6; //@ LB end S7 : begin y3 = '1; if (jmp) next = S3; else next = S8; end S8 : begin

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y2 = '1; y3 = '1; if (jmp) next = S3; else next = S9; end S9 : begin y1 = '1; y2 = '1; y3 = '1; if (jmp) next = S3; else next = S0; end default: begin y1 = 'x; y2 = 'x; y3 = 'x; next = XX; end endcase end endmodule

Example27-fsm8_2x-2-alwaysblockstylewithcombinatorialoutputs

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FSM8-3alwaysblock-Recommended-RegisteredOutputs

module fsm8_3x ( output logic y1, y2, y3, input logic jmp, go, sk0, sk1, clk, rst_n); import fsm8_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; case (state) S0: if ( go && jmp) next = S3; else if ( go && !jmp) next = S1; else next = S0; //@ LB S1 : if ( jmp) next = S3; else next = S2; S2 : if ( jmp) next = S3; else next = S9; S3 : if (!jmp) next = S4; else next = S3; //@ LB S4 : if (jmp) next = S3; else if (sk0 && !jmp) next = S6; else next = S5; S5 : if (jmp) next = S3; else if (!sk1 && !sk0 && !jmp) next = S6; else if (!sk1 && sk0 && !jmp) next = S7; else if ( sk1 && !sk0 && !jmp) next = S8; else next = S9; S6 : if (jmp) next = S3; else if (go && !jmp) next = S7; else next = S6; //@ LB S7 : if ( jmp) next = S3; else next = S8; S8 : if ( jmp) next = S3; else next = S9; S9 : if ( jmp) next = S3; else next = S0; default: next = XX; endcase end always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin y1 <= '0; y2 <= '0; y3 <= '0; end else begin y1 <= '0; y2 <= '0; y3 <= '0; case (next)

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S7 : y3 <= '1; S1 : y2 <= '1; S3 : begin y1 <= '1; y2 <= '1; end S8 : begin y2 <= '1; y3 <= '1; end S6, S9 : begin y1 <= '1; y2 <= '1; y3 <= '1; end endcase end endmodule


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module fsm8_4x ( output logic y1, y2, y3, input logic jmp, go, sk0, sk1, clk, rst_n); logic a1, a2, a3; // next combinatorial outputs import fsm8_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; case (state) S0: if ( go && jmp) next = S3; else if ( go && !jmp) next = S1; else next = S0; //@ LB S1 : if ( jmp) next = S3; else next = S2; S2 : if ( jmp) next = S3; else next = S9; S3 : if (!jmp) next = S4; else next = S3; //@ LB S4 : if (jmp) next = S3; else if (sk0 && !jmp) next = S6; else next = S5; S5 : if (jmp) next = S3; else if (!sk1 && !sk0 && !jmp) next = S6; else if (!sk1 && sk0 && !jmp) next = S7; else if ( sk1 && !sk0 && !jmp) next = S8; else next = S9; S6 : if (jmp) next = S3; else if (go && !jmp) next = S7; else next = S6; //@ LB S7 : if ( jmp) next = S3; else next = S8; S8 : if ( jmp) next = S3; else next = S9; S9 : if ( jmp) next = S3; else next = S0; default: next = XX; endcase end always_comb begin {a3,a2,a1} = '0; case (state) S0 : if (go && jmp) { a2,a1} = '1; // S3 else if (go && !jmp) { a2 } = '1; // S1 else ; // S0 S1 : if (jmp) { a2,a1} = '1; // S3 else ; // S2

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S2 : if (jmp) { a2,a1} = '1; // S3 else {a3,a2,a1} = '1; // S9 S3 : if (!jmp) ; // S4 else { a2,a1} = '1; // S3 S4 : if ( jmp) { a2,a1} = '1; // S3 else if (sk0 && !jmp) {a3,a2,a1} = '1; // S6 else ; // S5 S5 : if ( jmp) { a2,a1} = '1; // S3 else if (!sk1 && !sk0 && !jmp) {a3,a2,a1} = '1; // S6 else if (!sk1 && sk0 && !jmp) {a3 } = '1; // S7 else if ( sk1 && !sk0 && !jmp) {a3,a2 } = '1; // S8 else {a3,a2,a1} = '1; // S9 S6 : if (jmp) { a2,a1} = '1; // S3 else if (go && !jmp) {a3 } = '1; // S7 else {a3,a2,a1} = '1; // S6 S7 : if ( jmp) { a2,a1} = '1; // S3 else {a3,a2 } = '1; // S8 S8 : if ( jmp) { a2,a1} = '1; // S3 else {a3,a2,a1} = '1; // S9 S9 : if ( jmp) { a2,a1} = '1; // S3 else ; // S0 default: {a3,a2,a1} = 'x; endcase end always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin y1 <= '0; y2 <= '0; y3 <= '0; end else begin y1 <= a1; y2 <= a2; y3 <= a3; end endmodule


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PREP4-prep4_pkgsforabstractandbinaryencodedenums

The[a]bstractenumeratedtypespackagefileisnamedprep4_pkg_a.svbutthepackagenameisprep4_pkg.

package prep4_pkg; typedef enum {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, XX } state_e; endpackage

Example30-File:prep4_pkg_a.sv-prep4_pkgenumeratedtypedef

The[b]inaryencodedenumerated typespackage file isnamedprep4_pkg_b.svbut thepackagenameisstillprep4_pkg.

package prep4_pkg; typedef enum logic [3:0] {S0 = 4'b0000, S1 = 4'b0100, S2 = 4'b0101, S3 = 4'b0001, S4 = 4'b1011, S5 = 4'b1001, S6 = 4'b0010, S7 = 4'b0011, S8 = 4'b0110, S9 = 4'b1111, S10 = 4'b1101, S11 = 4'b0111, S12 = 4'b1010, S13 = 4'b1000, S14 = 4'b1110, S15 = 4'b1100, XX = 'x } state_e; endpackage

Example31-File:prep4_pkg_b.sv-prep4_pkgenumeratedtypedef

Thesepackagesincludeatypedefforthestate_etypethatisusedbyalloftheprep4designs.

Usingthesamepackagenamemakesitpossibletoreadtheseparatepackagefilesfirstinasimulation

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andfirstinsynthesiscompilationtoselectivelychooseabstractorbinaryencodedenumeratedtypeswithouttouchingtheprep4files.

PREP4-1alwaysblockRTL-NOTRecommended-RegisteredOutputs

module prep4_1x ( output logic [7:0] out, input logic [7:0] in, input logic clk, rst_n); import prep4_pkg::*; state_e state; always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin state <= S0; out <= 8'h00; end else begin state <= XX; //@ LB out <= 'x; case (state) S0 : if (in) begin if (in < 4) begin out <= 8'h06; state <= S1; end else if (in < 32) begin out <= 8'h18; state <= S2; end else if (in < 64) begin out <= 8'h60; state <= S3; end else begin out <= 8'h80; state <= S4; end end else begin out <= 8'h00; state <= S0; //@ LB end S1 : if (in[0] & in[1]) begin out <= 8'h00; state <= S0; end else begin out <= 8'h60; state <= S3; end S2 : begin out <= 8'h60; state <= S3; end S3 : begin

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out <= 8'hF0; state <= S5; end S4 : if (in[0] | in[2] | in[4]) begin out <= 8'hF0; state <= S5; end else begin out <= 8'h1F; state <= S6; end S5 : if (in[0]) begin out <= 8'h3F; state <= S7; end else begin out <= 8'hF0; state <= S5; //@ LB end S6 : if ( in[6] & in[7]) begin out <= 8'h06; state <= S1; end else if (!in[6] & in[7]) begin out <= 8'hFF; state <= S9; end else if ( in[6] & !in[7]) begin out <= 8'h7F; state <= S8; end else begin out <= 8'h1F; state <= S6; //@ LB end S7 : if ( in[6] & in[7]) begin out <= 8'h80; state <= S4; end else if (!in[6] & !in[7]) begin out <= 8'h60; state <= S3; end else begin out <= 8'h3F; state <= S7; //@ LB end S8 : if (in[4] ^ in[5]) begin out <= 8'hFF; state <= S11; end else if (in[7]) begin out <= 8'h06; state <= S1; end else begin out <= 8'h7F; state <= S8; //@ LB

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end S9 : if (in[0]) begin out <= 8'hFF; state <= S11; end else begin out <= 8'hFF; state <= S9; //@ LB end S10: begin out <= 8'h06; state <= S1; end S11: if (in == 64) begin out <= 8'h7F; state <= S15; end else begin out <= 8'h7F; state <= S8; end S12: if (in == 255) begin out <= 8'h00; state <= S0; end else begin out <= 8'hFD; state <= S12; //@ LB end S13: if (in[1] ^ in[3] ^ in[5]) begin out <= 8'hFD; state <= S12; end else begin out <= 8'hDF; state <= S14; end S14: if (in) begin if (in < 64) begin out <= 8'hFD; state <= S12; end else begin out <= 8'hFF; state <= S10; end end else begin out <= 8'hDF; state <= S14; //@ LB end S15: if (in[7]) begin case (in[1:0]) 2'b00: begin out <= 8'hDF; state <= S14; end 2'b01: begin

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out <= 8'hFF; state <= S10; end 2'b10: begin out <= 8'hF7; state <= S13; end 2'b11: begin out <= 8'h00; state <= S0; end endcase end else begin out <= 8'h7F; state <= S15; //@ LB end default: begin out <= 'x; state <= XX; end endcase end endmodule

Example32-prep4_1x-1-alwaysblockstylewithregisteredoutputs

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PREP4-2alwaysblockRTL-Recommended-CombinatorialOutputs

module prep4_2x ( output logic [7:0] out, input logic [7:0] in, input logic clk, rst_n); import prep4_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; out = 'x; case (state) S0 : begin out = 8'h00; if (in) begin if (in < 4) next = S1; else if (in < 32) next = S2; else if (in < 64) next = S3; else next = S4; end else next = S0; //@ LB end S1 : begin out = 8'h06; if (in[0] && in[1]) next = S0; else next = S3; end S2 : begin out = 8'h18; next = S3; end S3 : begin out = 8'h60; next = S5; end S4 : begin out = 8'h80; if (in[0] || in[2] || in[4]) next = S5; else next = S6; end S5 : begin out = 8'hF0; if (in[0]) next = S7; else next = S5; //@ LB end S6: begin out = 8'h1F; if ( in[6] & in[7]) next = S1; else if (!in[6] & in[7]) next = S9; else if ( in[6] & !in[7]) next = S8; else next = S6; //@ LB

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end S7 : begin out = 8'h3F; if ( in[6] & in[7]) next = S4; else if (!in[6] & !in[7]) next = S3; else next = S7; //@ LB end S8 : begin out = 8'h7F; if (in[4] ^ in[5]) next = S11; else if (in[7]) next = S1; else next = S8; //@ LB end S9 : begin out = 8'hFF; if (in[0]) next = S11; else next = S9; //@ LB end S10: begin out = 8'hFF; next = S1; end S11: begin out = 8'hFF; if (in == 64) next = S15; else next = S8; end S12: begin out = 8'hFD; if (in == 255) next = S0; else next = S12; //@ LB end S13: begin out = 8'hF7; if (in[5] ^ in[3] ^ in[1]) next = S12; else next = S14; end S14: begin out = 8'hDF; if (in) begin if (in < 64) next = S12; else next = S10; end else next = S14; //@ LB end S15: begin out = 8'h7F; if (in[7]) begin case (in[1:0]) 2'b00: next = S14; 2'b01: next = S10; 2'b10: next = S13; 2'b11: next = S0; endcase end else next = S15; //@ LB end default : begin

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out = 'x; next = XX; end endcase end endmodule

Example33-prep4_2x-2-alwaysblockstylewithcombinatorialoutputs

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PREP4-3alwaysblock-Recommended-RegisteredOutputs

module prep4_3x ( output logic [7:0] out, input logic [7:0] in, input logic clk, rst_n); import prep4_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; case (state) S0 : if (in) begin if (in < 4) next = S1; else if (in < 32) next = S2; else if (in < 64) next = S3; else next = S4; end else next = S0; //@ LB S1 : if (in[0] && in[1]) next = S0; else next = S3; S2 : next = S3; S3 : next = S5; S4 : if (in[0] || in[2] || in[4]) next = S5; else next = S6; S5 : if (in[0]) next = S7; else next = S5; //@ LB S6: if ( in[6] & in[7]) next = S1; else if (!in[6] & in[7]) next = S9; else if ( in[6] & !in[7]) next = S8; else next = S6; //@ LB S7 : if ( in[6] & in[7]) next = S4; else if (!in[6] & !in[7]) next = S3; else next = S7; //@ LB S8 : if (in[4] ^ in[5]) next = S11; else if (in[7]) next = S1; else next = S8; //@ LB S9 : if (in[0]) next = S11; else next = S9; //@ LB S10: next = S1; S11: if (in == 64) next = S15; else next = S8; S12: if (in == 255) next = S0; else next = S12; //@ LB S13: if (in[5] ^ in[3] ^ in[1]) next = S12; else next = S14; S14: if (in) begin if (in < 64) next = S12; else next = S10; end else next = S14; //@ LB S15: if (in[7]) begin

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case (in[1:0]) 2'b00: next = S14; 2'b01: next = S10; 2'b10: next = S13; 2'b11: next = S0; endcase end else next = S15; //@ LB default : next = XX; endcase end always_ff @(posedge clk, negedge rst_n) if (!rst_n) out <= 8'h00; else begin out <= 'x; case (next) S0: out <= 8'h00; S1: out <= 8'h06; S2: out <= 8'h18; S3: out <= 8'h60; S4: out <= 8'h80; S5: out <= 8'hF0; S6: out <= 8'h1F; S7: out <= 8'h3F; S8: out <= 8'h7F; S9: out <= 8'hFF; S10: out <= 8'hFF; S11: out <= 8'hFF; S12: out <= 8'hFD; S13: out <= 8'hF7; S14: out <= 8'hDF; S15: out <= 8'h7F; default: out <= 'x; endcase end endmodule


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PREP4-4alwaysblockRTL-Recommended-RegisteredOutputs

module prep4_4x ( output logic [7:0] out, input logic [7:0] in, input logic clk, rst_n); logic [7:0] n_out; // next combinatorial outputs import prep4_pkg::*; state_e state, next; always_ff @(posedge clk, negedge rst_n) if (!rst_n) state <= S0; else state <= next; always_comb begin next = XX; //@LB next = state; case (state) S0 : if (in) begin if (in < 4) next = S1; else if (in < 32) next = S2; else if (in < 64) next = S3; else next = S4; end else next = S0; //@ LB S1 : if (in[0] && in[1]) next = S0; else next = S3; S2 : next = S3; S3 : next = S5; S4 : if (in[0] || in[2] || in[4]) next = S5; else next = S6; S5 : if (in[0]) next = S7; else next = S5; //@ LB S6: if ( in[6] & in[7]) next = S1; else if (!in[6] & in[7]) next = S9; else if ( in[6] & !in[7]) next = S8; else next = S6; //@ LB S7 : if ( in[6] & in[7]) next = S4; else if (!in[6] & !in[7]) next = S3; else next = S7; //@ LB S8 : if (in[4] ^ in[5]) next = S11; else if (in[7]) next = S1; else next = S8; //@ LB S9 : if (in[0]) next = S11; else next = S9; //@ LB S10: next = S1; S11: if (in == 64) next = S15; else next = S8; S12: if (in == 255) next = S0; else next = S12; //@ LB S13: if (in[5] ^ in[3] ^ in[1]) next = S12; else next = S14; S14: if (in) begin if (in < 64) next = S12; else next = S10; end

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else next = S14; //@ LB S15: if (in[7]) begin case (in[1:0]) 2'b00: next = S14; 2'b01: next = S10; 2'b10: next = S13; 2'b11: next = S0; endcase end else next = S15; //@ LB default : next = XX; endcase end always_comb begin n_out = 8'h00; case (state) S0 : if (in) begin if (in < 4) n_out = 8'h06; // S1 else if (in < 32) n_out = 8'h18; // S2 else if (in < 64) n_out = 8'h60; // S3 else n_out = 8'h80; // S4 end else n_out = 8'h00; //@ LB S1 : if (in[0] && in[1]) n_out = 8'h00; // S0 else n_out = 8'h60; // S3 S2 : n_out = 8'h60; // S3 S3 : n_out = 8'hF0; // S5 S4 : if (in[0] || in[2] || in[4]) n_out = 8'hF0; // S5 else n_out = 8'h1F; // S6 S5 : if (in[0]) n_out = 8'h3F; // S7 else n_out = 8'hF0; // S5 S6: if ( in[6] & in[7]) n_out = 8'h06; // S1 else if (!in[6] & in[7]) n_out = 8'hFF; // S9 else if ( in[6] & !in[7]) n_out = 8'h7F; // S8 else n_out = 8'h1F; // S6 S7 : if ( in[6] & in[7]) n_out = 8'h80; // S4 else if (!in[6] & !in[7]) n_out = 8'h60; // S3 else n_out = 8'h3F; // S7 S8 : if (in[4] ^ in[5]) n_out = 8'hFF; // S11 else if (in[7]) n_out = 8'h06; // S1 else n_out = 8'h7F; // S8 S9 : if (in[0]) n_out = 8'hFF; // S11 else n_out = 8'hFF; // S9 S10: n_out = 8'h06; // S1 S11: if (in == 64) n_out = 8'h7F; // S15 else n_out = 8'h7F; // S8 S12: if (in == 255) n_out = 8'h00; // S0 else n_out = 8'hFD; // S12 S13: if (in[5] ^ in[3] ^ in[1]) n_out = 8'hFD; // S12 else n_out = 8'hDF; // S14 S14: if (in) begin if (in < 64) n_out = 8'hFD; // S12 else n_out = 8'hFF; // S10 end else n_out = 8'hDF; // S14 S15: if (in[7]) begin case (in[1:0])

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2'b00: n_out = 8'hDF; // S14 2'b01: n_out = 8'hFF; // S10 2'b10: n_out = 8'hF7; // S13 2'b11: n_out = 8'h00; // S0 endcase end else n_out = 8'h7F; // S15 default : n_out = 'x; endcase end always_ff @(posedge clk, negedge rst_n) if (!rst_n) out <= 8'h00; else out <= n_out; endmodule


clifford e. cummings heath chambers - sunburst designsnug 2019 page 7 rev 1.0 finite state machine...

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