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ClickCAM Using Click for Exploring Power Saving Schemes in Router Architectures Jonathan Ellithorpe, Laura Keys CS 252, Spring 2009

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ClickCAM

Using Click for Exploring Power Saving Schemes in Router Architectures

Jonathan Ellithorpe, Laura Keys

CS 252, Spring 2009

Motivation

Energy Concerns $$ environmental

Networking Impact operation costs hardware layout

Where TCAM / SRAM fit in

Router – Hardware Model

CPU TCAMMain

Memory

NIC

NICNIC

NIC

SRAM Buffers

SRAM Buffers

SRAM Buffers

SRAM Buffers

Power Hungry!

TCAMs (Ternary Content Addressable Memory)

Pros/Cons

Uses

Four stages precharge select lines match lines priority encoder

TCAM Configurations

Pros / cons of smaller TCAMs

Alternate Configurations

Attempts to decrease power consumption sub-tables paging schemes + entry compression splitting TCAM into banks

Our Approach

Reduce power consumption with small performance degradation

Metrics Throughput (as a percentage of packets presented) Average Power

Success attained by decreasing power by 2x the reduction in performance

Power-saving Schemes: Sleepy Banks

If few number of unique entries accessed in a TCAM bank, turn off lesser used banks to save on static and leakage power

Pros if traffic comes in bursts with large lapses, save on

power

Cons if traffic constantly hits in all banks, we either don't

put any to sleep or else we frequently access DRAM

Sleepy Banks

Bank 0

Bank 1

Bank n

TCAM SDRAM

TCAM IMAGE

zZ

Z

Mapper

Incoming DST IP

Power-saving Schemes: Tuple Cache

Use a smaller TCAM as a cache for low-power SDRAM

Pros small TCAM is lower power and faster than larger

one if we have small set of frequently accessed

destinations, we could potentially save a lot of power

Cons potential to pull from DRAM frequently if unique

destination set is not small enough

Tuple Cache

TCAM

SDRAM

TCAM ENTRIESIncoming

DST IP Miss!

Hit!Load

Experiments

Click timing notion

UCSB's TCAM power model

randomly generated workload represent different types of traffic

Flow-Based Workload Generator

Simulation Methodology

Task Queue

Clock

TCAM

SDRAM

HW Element N

Functional Model

Timing Model

HW Model

Model Model

Communication Queueing

Results

Average Power

Throughput

(7.0W, 1.0)

(1.5W, 0.35)

Baseline

(2.5W, 0.36)

16 Banks, Sleepy

4 Banks, Sleepy3W

6W

9W

1.000.750.500.25

(6.6W, 0.64)(6.4W, 0.46)

1 Banks, Sleepy

End Zone

64 Banks, Sleepy

95% mark

Conclusions

Hard to do power modeling in network hardware.

Proprietary black boxes

Tradeoff between power and performance is tricky! End zone hard to reach.

Banking can help, but more banks => more waking and sleeping

Workload also hard to estimate and has big impact on the power and performance tradeoff