class 10: cmos gate design
TRANSCRIPT
Joseph A. Elias, PhD 1
Class 10: CMOS Gate Design
Topics:1. Exclusive OR Implementation2. Exclusive OR Carry Circuit3. PMOS Carry Circuit Equivalent 4. CMOS Full-Adder 5. NAND, NOR Gate Considerations 6. Logic Example 7. Logic Negation 8. Mapping Logic ‘0’ 9. Equivalent Circuits 10. Fan-In and Fan-Out 11. Rise Delay Time 12. Rise Delay Time 13. Rise Delay Time 14. Fall Delay Time 15. Equal Delays
Joseph A. Elias, PhD 2
Class 10: CMOS Gate DesignExclusive OR Design (Martin c4.5)
Similar to how one derives a2-input XOR (Martin, p.183)using (a’+b’)=(ab)’ (a’b’)=(a+b)’
a XOR b = a’b + ab’ = a’a + a’b + ab’ + bb’= a’(a+b) + b’(a+b)= (a’+b’)(a+b)= (ab)’(a+b)= (ab + (a’b’) )’= (ab + (a + b)’ )’
3-input XOR Truth Table
Joseph A. Elias, PhD 3
Class 10: CMOS Gate DesignExclusive OR Carry Circuit (Martin c4.5)
Vout =
NMOS realization•A in parallel with B•A||B in series with C•AB in parallel with (A||B)C
PMOS equivalent•A in series with B•AB in parallel with C•A||B in series with (AB)||C
Joseph A. Elias, PhD 4
Class 10: CMOS Gate DesignPMOS Carry Circuit Equivalent (Martin c4.5)
•Martin indicates equivalency between these circuits•Is this true?
(AB+C)(A+B) = (A+B)C + (AB)ABA + ABB + AC + BC = AC +BC +ABAB + AB + AC + BC = AC + BC + ABAB + AC + BC = AB + AC + BC equivalent
Joseph A. Elias, PhD 5
Class 10: CMOS Gate DesignCMOS Full-Adder (Martin c4.5)
Carry: (A+B)C + AB
Sum: (A+B+C) Carry + ABC
Joseph A. Elias, PhD 6
Class 10: CMOS Gate DesignNAND, NOR Gate Considerations (Martin c4.5)
•NAND is preferable to NOR - why?•What makes p-ch undesirable?•How does one compensate for it?
Joseph A. Elias, PhD 7
Class 10: CMOS Gate DesignLogic Example (Martin c4.5)
Desired Truth Table Corresponding Karnaugh Map
Grouping of 1’ (meaning what gates?):
Joseph A. Elias, PhD 8
Class 10: CMOS Gate DesignLogic Negation (Martin c4.5)
Joseph A. Elias, PhD 9
Class 10: CMOS Gate DesignMapping Logic ‘0’ (Martin c4.5)
Using (a’b’)=(a+b)’
•Choice of which map to use depends on whether inputs are negated
Joseph A. Elias, PhD 10
Class 10: CMOS Gate DesignEquivalent Circuits (Martin c4.5)
Joseph A. Elias, PhD 11
Class 10: CMOS Gate DesignFan-In and Fan-Out (Weste p264-267)
Joseph A. Elias, PhD 12
Class 10: CMOS Gate DesignRise Delay Time (Weste p264-267)
Rise time delay
where
Joseph A. Elias, PhD 13
Class 10: CMOS Gate DesignRise Delay Time (Weste p264-267)
Re-writing
Joseph A. Elias, PhD 14
Class 10: CMOS Gate DesignRise Delay Time (Weste p264-267)
Has the form:
where
Joseph A. Elias, PhD 15
Class 10: CMOS Gate DesignFall Delay Time (Weste p264-267)
Similar to rise time delay, the fall time delay as a function of fan-in and fan-out:
Assuming equal-sized gates (n/p size fixed) is the case(as in standard cells and gate arrays)
Joseph A. Elias, PhD 16
Class 10: CMOS Gate DesignEqual Delays (Weste p264-267)
Assuming equal delays gives
Where the beta ratios are
So p-ch would be made (βn / m βp) times widerfor equal rise and fall delay