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DESIGN AND IMPLEMENTATION OF CS2FF FOR LOW POWER

DIGITALVLSI’S

M.V.MOUNIKA,

14204116.

INTRODUCTION

Ultra-low power CMOS VLSIs have attracted much attention for use in power-

aware applications such as wireless smart sensor networks and implantable bio-

medical systems.

Several low-power techniques have been investigated .

Among them, reducing the supply voltage for digital circuits is the most direct

and effective way to achieve low power dissipation because of the quadratic

dependence of the power dissipation on the supply voltage.

One big issue for ultra-low voltage digital circuits is in the design of a flip-

flop (FF) circuit because FFs are widely used in modern digital VLSI

systems such as a general purpose register, a pipeline register, and a finite

state machine.

However, their performance tends to degrade at lower supply voltage and,

moreover, they require a number of transistors to achieve stable and low

voltage operation.

CONVENTIONAL FF'S

TBFF

NLFF

CLFF

CONVENTIONAL FFS

The TBFF consists of only 24 transistors and is used in most

standard cell libraries. However, the function becomes difficult to

operate at extremely low supply voltage, such as below the

threshold voltage, because the outputs of the tri-state buffers are

connected in wired-OR

And the contention increases power dissipation and results in functional

error .

Moreover, both the operation of tristate buffers and that of transmission

gates used in the TBFF tend to fail at lower supply voltage.

The NLFF and CLFF consist of only static CMOS gates.

The NLFF are suitable for low voltage operation because they are

composed of only general-purpose CMOS gates without using additional

stacking transistors.

The stacking transistors need higher supply voltage as the number of

stacking transistors increases .

However, the NLFF requires 40 transistors and occupies a large area,

resulting in high power dissipation.

The CLFF can slightly reduce the number of transistors, but it uses

modified NAND and NOR gates marked with asterisks to introduce delay

time for proper operation and still requires 34 transistors.

Proposed cs2ff

In light of this background, we herein propose a circuits shared

static FF (CS2FF) suitable for extremely low-power digital circuits

with a small number of transistors.

The CS2FF consists of five static NORs and two inverters (INVs).

Thus, the CS2FF uses only 24 transistors

The INVs are used to generate control signals of CKB and CK2 from root

clock of CK.

NOR1, NOR2, and NOR3 form a master latch,while NOR3, NOR4, and

NOR5 form a slave latch.

Note that NOR3 is shared both in the master and slave latches, and is used

to acquire data in the master latch and transfer it to the slave latch.

The master latch operates using a positive edge of control signal of CK2.

When input data, CK2, and CKB are “D0”, low, and high, respectively,

NOR1 works as an inverter and the output of NOR3 is reset to low.

Thus, NOR2 also works as an inverter, and the data is transferred to QM

as“D0”.

Then, when CK2 and CKB become high and low, respectively, the output

of NOR1 is reset to low.

Therefore, NOR2 and NOR3 form the master latch, and the data is held at

MFB as “D0B”.

Meanwhile, the slave latch operates using a negative edge of clock signal

of CK.

When CK and CKB are high and low, respectively, the output of NOR4 is

reset to low and NOR5 works as an inverter.

Therefore, the data is transferred from MFB to the output of Q as “D0”.

Then, when CK and CKB become low and high, respectively, the output

NOR3 is reset to low.

Therefore, NOR4 and NOR5 form the slave latch, and the data is held at Q

as “D0”.

This way our proposed CS2FF operates as a master-slave flip-flop with a

small number of transistors.

SIMULATION RESULTS

CONCLUSION

• In this paper, we proposed a compact and low-power circuit

shared static flip-flop (CS2FF) for extremely low-power digital VLSIs. The

circuit consists of five static NORs and two inverters (INVs). The total

number of transistors was only 24, which is the same as the conventional

tri-state buffer based flip flop (TBFF) used in most standard cell libraries.

SPICE simulations demonstrated that our CS2FF achieved.

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