circuit analysis & design contest 2021
TRANSCRIPT
Mahdi Yektaei Looking forward a Ph.D. position
PAGE 1
PAGE 3
What are important here? 1) A positive feedback. 2) The system cannot latch. 3) The topology guarantees always a
positive gain margin.
Supposed: Latching has Amplification + Positive Feedback
For 1 and 2, We have to reduce the amplifier gain. For 3, It will design at advanced section.
Outline
Analysis
DD DD
2× IS
V V
Simple Latch
out out
= β = − ∗ + ∗
=
∗ ∗ +
The feedback is positive and close-loop gain is: = −
=
− − ∗ + ∗
The feedback factor is: = − , that ever < . Stability is important for positive gain margin, therefore we would like to have not the poles and zeros at right of imaginary axis for the close loop. if < < , the function will be stable.
Block diagram of feedback (Shunt-Shunt)
A
β
+ VoutVin
2 + + + − + 1 + −
Approximate, if the function is stable. It means amplifier is reduced. Therefore, | |< 1
o gm .vgs
PAGE 6
V =0in
Without Input
At Positive Feedback, if we ever increase amplification, we have a faster comparator. On the other hand, if numbers of poles are equal with zeros, width of output signal is infinite (system is a oscillator). // Capacitor between input and output can create a Zero=0 and a Pole.
Outline
Analysis
Positive Feedback without amplification (The topology guarantees stability)
I am designing a source-follower with the positive feedback at most difficult state (Oscillator by LTspice)
PAGE 8
Block Diagram of the Proposed-Topology
PAGE 9
Vout,ARF RL
1 + ∗ ∗
1
+
The feedback is positive and close-loop gain is: = −
Also, || is < 1 and |β| is < 1. Therefore, |Aβ| is <1. is between input and output (It is series in the circuit). Therefore, we have one Zero=0 and one pole at −
.
.
Also, we have positive gain margin, because close-loop function is always stable. For Stability of − =0,
S2 RFCF 2 1+gmRL
2− gmRL 2 +
1+gmRL 2
Due to feedback factor, all poles and zeros are stable. On the other hand, If RFCF>>1, we have more positive gain margin
PAGE 10
(A)
(B)
Vi
Vo
V_latching
VT1VT2
If V_latching=0, or VT1=VT2, The Schmitt-trigger is a simple comparator.
For fig.(A): ==0 → R2=0
For fig.(B): ==0 → R4=0
VDD= -VSS
Here is just a experiment for reminder of hysteresis (LTspice)
Here is just a experiment for reminder of hysteresis (LTspice)
PAGE 11
Videos of the Fig. (A) Videos of the Fig. (B) With Hysteresis Vin: 20Hz, 5vp R2=R4=5K R1=R3=10K
Without Hysteresis Vin: 20Hz, 5vp R2=R4=0 R1=R3=10K
Outline
Analysis
We have 4 advanced-method for study of stability.
1. Routh Hurwitz 2. Root Locus 3. Bode Diagram 4. Nyquist
For positive gain margin, I would like to use the Nyquist method. Because the positive gain margin is important for the question and, from my understanding, we could describe stability of the close-loop function by the open-loop function. Also, we will know locations of the gain and the phase by the variable frequency. Finally, we would be able to change the positive gain margin.
PAGE 13
Harry Nyquist
2
-1
In the Nyquist stability criterion, If 0 < 1 , close loop function is stable. Due to, gm∗RL
1+∗ is always < 1, as gm∗RL
1+∗ × gm∗RL
1+∗ is always < 1.
created the main pole, because the is very more than capacitors of NMOS.
Outline
Analysis
https://wiki.analog.com/university/courses/electronics/electronics-lab-24m.
[2] Ali. Hajimiri “114N. Kelvin Generator, water FET, positive feedback” https://www.youtube.com/c/AliHajimiriChannel/.
https://youtu.be/-wEV3sHTKNA (accessed Jan 30, 2019).
[3] H. Khorramabadi, "Data Converters," E. L. 20, Ed., ed. https://inst.eecs.berkeley.edu/~ee247/fa04/fa04/lectures/L20_f04.pdf
University of California, Berkeley, 2004.
[4] "Simulation, LTspice" ed. https://analog.com: Linear Technology, Analog Device, Feb 19 2021.
[5] M. R. Motedayen, Linear Control Systems (Persian language): Jahesh publication, 2014.
[6] H. Nyquist, “Image,” Wikipedia, https://en.wikipedia.org/wiki/Harry_Nyquist.
PAGE 16
Thanks in advance
Mahdi Yektaei Mahdi is looking forward for a Ph.D. position at the best universities in the
world. Now, He is trying to improve his English for the applying.
Mahdi (Student Member, IEEE) received the B.Sc. degree in electrical engineering from the Shamsipour Technical College, Tehran, Iran, in 2015, and the M.S. degree from the Integrated Circuits and Systems Laboratory (ICAS), Shahed University, Tehran, in 2016-2019. He is a teaching assistant of Digital- Electronics Laboratory at Shahed University in 2017 to present. From 2013 to 2015, he was with Rayene Andis Arsin Startup Company, Tehran, and an Electronics Designer with Rabo Startup Company, Tehran, in 2015. From 2018 to 2019, he was with Pars Hesgar Damun, Tehran, developing circuits for measurement. His research interests include MOS current mode logic, energy- efficient integrated circuits, serial links (SerDes), low-voltage and ultralow- power (ULP) circuits in the wireline and the wireless applications. He has received the Best Inventor Award from the National Sahand Research and Technology Festival in 2012 and he has received the Best Idea Award from the Shahed University in 2019. He has 2 patents and one paper on the TVLSI journal. He was a reviewer for 13 manuscripts at TCAS-II, ISCAS-2021 and IEEE Access.
PAGE 17
Outline
Analysis
Outline
Outline
Block Diagram of the Proposed-Topology
Here is just a experiment for reminder of hysteresis (LTspice)
Here is just a experiment for reminder of hysteresis (LTspice)
Outline
PAGE 1
PAGE 3
What are important here? 1) A positive feedback. 2) The system cannot latch. 3) The topology guarantees always a
positive gain margin.
Supposed: Latching has Amplification + Positive Feedback
For 1 and 2, We have to reduce the amplifier gain. For 3, It will design at advanced section.
Outline
Analysis
DD DD
2× IS
V V
Simple Latch
out out
= β = − ∗ + ∗
=
∗ ∗ +
The feedback is positive and close-loop gain is: = −
=
− − ∗ + ∗
The feedback factor is: = − , that ever < . Stability is important for positive gain margin, therefore we would like to have not the poles and zeros at right of imaginary axis for the close loop. if < < , the function will be stable.
Block diagram of feedback (Shunt-Shunt)
A
β
+ VoutVin
2 + + + − + 1 + −
Approximate, if the function is stable. It means amplifier is reduced. Therefore, | |< 1
o gm .vgs
PAGE 6
V =0in
Without Input
At Positive Feedback, if we ever increase amplification, we have a faster comparator. On the other hand, if numbers of poles are equal with zeros, width of output signal is infinite (system is a oscillator). // Capacitor between input and output can create a Zero=0 and a Pole.
Outline
Analysis
Positive Feedback without amplification (The topology guarantees stability)
I am designing a source-follower with the positive feedback at most difficult state (Oscillator by LTspice)
PAGE 8
Block Diagram of the Proposed-Topology
PAGE 9
Vout,ARF RL
1 + ∗ ∗
1
+
The feedback is positive and close-loop gain is: = −
Also, || is < 1 and |β| is < 1. Therefore, |Aβ| is <1. is between input and output (It is series in the circuit). Therefore, we have one Zero=0 and one pole at −
.
.
Also, we have positive gain margin, because close-loop function is always stable. For Stability of − =0,
S2 RFCF 2 1+gmRL
2− gmRL 2 +
1+gmRL 2
Due to feedback factor, all poles and zeros are stable. On the other hand, If RFCF>>1, we have more positive gain margin
PAGE 10
(A)
(B)
Vi
Vo
V_latching
VT1VT2
If V_latching=0, or VT1=VT2, The Schmitt-trigger is a simple comparator.
For fig.(A): ==0 → R2=0
For fig.(B): ==0 → R4=0
VDD= -VSS
Here is just a experiment for reminder of hysteresis (LTspice)
Here is just a experiment for reminder of hysteresis (LTspice)
PAGE 11
Videos of the Fig. (A) Videos of the Fig. (B) With Hysteresis Vin: 20Hz, 5vp R2=R4=5K R1=R3=10K
Without Hysteresis Vin: 20Hz, 5vp R2=R4=0 R1=R3=10K
Outline
Analysis
We have 4 advanced-method for study of stability.
1. Routh Hurwitz 2. Root Locus 3. Bode Diagram 4. Nyquist
For positive gain margin, I would like to use the Nyquist method. Because the positive gain margin is important for the question and, from my understanding, we could describe stability of the close-loop function by the open-loop function. Also, we will know locations of the gain and the phase by the variable frequency. Finally, we would be able to change the positive gain margin.
PAGE 13
Harry Nyquist
2
-1
In the Nyquist stability criterion, If 0 < 1 , close loop function is stable. Due to, gm∗RL
1+∗ is always < 1, as gm∗RL
1+∗ × gm∗RL
1+∗ is always < 1.
created the main pole, because the is very more than capacitors of NMOS.
Outline
Analysis
https://wiki.analog.com/university/courses/electronics/electronics-lab-24m.
[2] Ali. Hajimiri “114N. Kelvin Generator, water FET, positive feedback” https://www.youtube.com/c/AliHajimiriChannel/.
https://youtu.be/-wEV3sHTKNA (accessed Jan 30, 2019).
[3] H. Khorramabadi, "Data Converters," E. L. 20, Ed., ed. https://inst.eecs.berkeley.edu/~ee247/fa04/fa04/lectures/L20_f04.pdf
University of California, Berkeley, 2004.
[4] "Simulation, LTspice" ed. https://analog.com: Linear Technology, Analog Device, Feb 19 2021.
[5] M. R. Motedayen, Linear Control Systems (Persian language): Jahesh publication, 2014.
[6] H. Nyquist, “Image,” Wikipedia, https://en.wikipedia.org/wiki/Harry_Nyquist.
PAGE 16
Thanks in advance
Mahdi Yektaei Mahdi is looking forward for a Ph.D. position at the best universities in the
world. Now, He is trying to improve his English for the applying.
Mahdi (Student Member, IEEE) received the B.Sc. degree in electrical engineering from the Shamsipour Technical College, Tehran, Iran, in 2015, and the M.S. degree from the Integrated Circuits and Systems Laboratory (ICAS), Shahed University, Tehran, in 2016-2019. He is a teaching assistant of Digital- Electronics Laboratory at Shahed University in 2017 to present. From 2013 to 2015, he was with Rayene Andis Arsin Startup Company, Tehran, and an Electronics Designer with Rabo Startup Company, Tehran, in 2015. From 2018 to 2019, he was with Pars Hesgar Damun, Tehran, developing circuits for measurement. His research interests include MOS current mode logic, energy- efficient integrated circuits, serial links (SerDes), low-voltage and ultralow- power (ULP) circuits in the wireline and the wireless applications. He has received the Best Inventor Award from the National Sahand Research and Technology Festival in 2012 and he has received the Best Idea Award from the Shahed University in 2019. He has 2 patents and one paper on the TVLSI journal. He was a reviewer for 13 manuscripts at TCAS-II, ISCAS-2021 and IEEE Access.
PAGE 17
Outline
Analysis
Outline
Outline
Block Diagram of the Proposed-Topology
Here is just a experiment for reminder of hysteresis (LTspice)
Here is just a experiment for reminder of hysteresis (LTspice)
Outline