chisel accelerating hardware design - risc-v · chisel – accelerating hardware design ... january...
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Chisel – Accelerating Hardware Design
Jonathan Bachrach +Patrick Li + Adam Israelivitz + Henry Cook + Andrew Waterman +Palmer Dabbelt + Richard Lin + Howard Mao + Albert Magyar +Scott Beamer + Jack Koenig + Stephen Twigg + Colin Schmidt +
Jim Lawson + Huy Vo + Sebastian Mirolo + Yunsup Lee +John Wawrzynek + Krste Asanovic +
many more
EECS UC Berkeley
January 16, 2015
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Berkeley Chisel Team 1
jonathan chris henry palmer adam donggyubachrach celio cook dabbelt izraelivitz kim
patrick yunsup richard jim albert howieli lee lin lawson magyar mao
colin danny stephen andrew john krsteschmidt tang twigg waterman warzynek asanovic
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Dire Hardware Design Situation 2
slow hardware design1980’s style languages and baroque tool chains with ad hoc scriptsmanual optimization obscuring designsminimal compile-time and run-time errorsarmy of people in both CAD tools and design – costs $10Ms
slow and expensive to synthesizetakes order daysnot robust and so largely manual processproprietary tools – cost > $1M / year / seat
slow testing and evaluationruns 200M x slower than code runs in productionarmy of verification people – costs $10Ms
slow and expensive fabricationvery labor intensive – costs $1Ms
design costs dominatevery few ASIC designs and chip startups
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Design Loop 3
“Iron Law of Design Performance”
Tdesign = n ∗ (Tprogram + Tbuild + Teval)
every step in loop is potentialbottleneckbetter results happen byiterating through design loopcurrently can only go arounddesign loop a few times
program build
eval fab
need to shorten design loop and get through it more timesneed to lower costs on all steps
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Our Steps – “the Chisel Plan” 4
1 generation – use good software ideas – embedded host language2 composition – design by composing bigger reusable pieces3 transformation – specification + transformations = FIRRTL4 optimization – parameterization + design space exploration5 layering – incrementally higher level and strategic6 simulation – speed up testing and evaluation methods7 realization – fast + affordable deployment technology
will get increases in productivity and decreases in costs leading toshorter time to marketmore efficient designsmore “tapeouts” and chip startups
UC Berkeley uniquely positioned to jump start revolutionstrong VLSI tools and architecture programsnon-profit orientation and open source ( BSD ) tradition
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(1) Hardware Generators 5
problemhardware design is too low levelhard to write generators for family of designs
solution
leverage great ideas in software engineering in hardware designembed hardware construction in programming languageleverage host language ideas and software engineering techniqueszero cost abstractions
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Status Quo Generators 6
1 write verilog design structurally – literal2 verilog generate command – limited3 write perl script that writes verilog – awkward
module counter (clk, reset);
input clk;
input reset;
parameter W = 8;
reg [W-1:0] cnt;
always @ (posedge clk)
begin
if (reset)
cnt <= 0
else
cnt <= cnt + 1
end
endmodule
reset
1
+
0
W
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Chisel 7
A hardware construction language“synthesizable by construction”creates graph representinghardware
Embedded within Scala languageto leverage mindshare andlanguage designBest of hardware and softwaredesign ideasMultiple targets
Simulation and synthesisMemory IP is target-specific
Not Scala app -> Verilog arch
write once
CPUC++
FPGAVerilog
ASICVerilog
Chisel
multiple targets
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Synthesizable By Construction 8
Well formed Chisel graphs are synthesizable.
Use small number of basic nodessimple semanticseasy to synthesize
During construction check thattypes, directions and widths matchthere are no combinational loops
If it passes these checks then it’s synthesizable
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The Scala Programming Language 9
Object OrientedFactory Objects, ClassesTraits, overloading etcStrongly typed with type inference
FunctionalHigher order functionsAnonymous functionsCurrying etc
ExtensibleDomain Specific Languages (DSLs)
Compiled to JVMGood performanceGreat Java interoperabilityMature debugging, execution environments
Growing PopularityTwittermany Universities
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Primitive Datatypes 10
Chisel has 3 primitive datatypesUInt – Unsigned integerSInt – Signed integerBool – Boolean value
Can do arithmetic and logic with these datatypes
Example Literal Constructions
val sel = Bool(false)
val a = UInt(25)
val b = SInt(-35)
where val is a Scala keyword used to declare variables whose valueswon’t change
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Aggregate Data Types 11Bundle
User-extendable collection of values with named fieldsSimilar to structs
class MyFloat extends Bundle {
val sign = Bool()
val exponent = UInt(width=8)
val significand = UInt(width=23)
}
Vec
Create indexable collection of valuesSimilar to arrayUseful Methods: contains, indexWhere, ...
val myVec = Vec.fill(5){ SInt(width=23) }
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Abstract Data Types 12
The user can construct new data typesAllows for compact, readable code
Example: Complex numbersUseful for FFT, Correlator, other DSPDefine arithmetic on complex numbers
class Complex(val real: SInt, val imag: SInt) extends Bundle {
def + (b: Complex): Complex =
new Complex(real + b.real, imag + b.imag)
...
}
val a = new Complex(SInt(32), SInt(-16))
val b = new Complex(SInt(-15), SInt(21))
val c = a + b
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Example 13
class GCD extends Module {
val io = new Bundle {
val a = UInt(INPUT, 16)
val b = UInt(INPUT, 16)
val z = UInt(OUTPUT, 16)
val valid = Bool(OUTPUT) }
val x = Reg(init = io.a)
val y = Reg(init = io.b)
when (x > y) {
x := x - y
} .otherwise {
y := y - x
}
io.z := x
io.valid := y === UInt(0)
}
GCD
Bool
UFix
valid
z
UFix
UFix
b
a
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Valid Wrapper 14
class Valid[T <: Data](dtype: T) extends Bundle {
val data = dtype.clone
val valid = Bool()
override def clone = new Valid(dtype)
}
class GCD extends Module {
val io = new Bundle {
val a = UInt(INPUT, 16)
val b = UInt(INPUT, 16)
val out = new Valid(UInt(OUTPUT, 16))
} }
...
io.out.data := x
io.out.valid := y === UInt(0)
}
Bool
T
valid
data
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Function Filters 15
abstract class Filter[T <: Data](dtype: T) extends Module {
val io = new Bundle {
val in = new Valid(dtype).asInput
val out = new Valid(dtype).asOutput
} }
class FunctionFilter[T <: Data](f: T => T, dtype: T) extends Filter(dtype) {
io.out.valid := io.in.valid
io.out := f(io.in)
}
Bool
UFix
valid
data
Bool
UFix
valid
data
f
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Clipping / Shifting Filters 16
def clippingFilter[T <: Num](limit: Int, dtype: T) =
new FunctionFilter(x => min(limit, max(-limit, x)), dtype)
def shiftingFilter[T <: Num](shift: Int, dtype: T) =
new FunctionFilter(x => x >> shift, dtype)
Bool
UFix
valid
data
Bool
UFix
valid
data
clip
Bool
UFix
valid
data
Bool
UFix
valid
data
shift
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Chained Filter 17
class ChainedFilter[T <: Num](dtype: T) extends Filter(dtype) = {
val shift = new ShiftFilter(2, dtype)
val clipper = new ClippingFilter(1 << 7, dtype)
io.in <> shift.io.in
shift.io.out <> clipper.io.in
clipper.io.out <> io.out
}
Bool
UFix
valid
data
Bool
UFix
valid
data
Shift
Bool
UFix
valid
data
Bool
UFix
valid
data
clip
Bool
UFix
valid
Bool
UFix
valid
datadata
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Generator 18
def delays[T <: Data](x: T, n: Int): List[T] =
if (n <= 1) List(x) else x :: delays(Reg(next = x), n-1)
def FIR[T <: Num](hs: Seq[T], x: T): T =
(hs, delays(x, hs.length)).zipped.map( _ * _ ).reduce( _ + _ )
class TstFIR extends Module {
val io = new Bundle{ val x = SInt(INPUT, 8); val y = SInt(OUTPUT, 8) }
val h = Array(SInt(1), SInt(2), SInt(4))
io.y := FIR(h, io.x)
}
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Other Generators 19
Rocket Chip – cook + lee + waterman + ...BOOM – celioFFT generator – twiggSpectrometer – baileySha-3 generator – schmidt + izraelivitz + ...CS250 accelerators – berkeley EECS graduate studentsmany more
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Our Steps – “the Chisel Plan” 20
1 generation – use good software ideas – embedded host language2 composition – design by composing bigger reusable pieces3 transformation – specification + transformations = FIRRTL4 optimization – parameterization + design space exploration5 layering – incrementally higher level and strategic6 simulation – speed up testing and evaluation methods7 realization – fast + affordable deployment technology
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(2) Composition 21
problempeople reinvent blocks over and over againhow to reuse blocks and compose
solutionbuild hardware out of bigger piecesconstruct common libraries and package managerbuild communityprovide target specific composers
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Build Community and Common Library 22
open source on github accepting pull requestswebsite, mailing lists, blog, twitteronline documentation and tutorialclasses, bootcamps, and materialslibrary of high level and reusable components
> 1 FTE for community outreach, support, development
chisel.eecs.berkeley.edu
https://github.com/ucb-bar/chisel
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Growing Library of Modules 23
functional Vec interface,counters,shift-registers, pipes, queues,priority-mux, decoders, encoders,fixed-priority, round-robin, and locking arbiters,cross-bar, time multiplexor,popcount, scoreboards,ROMs, RAMs, CAMs, TLB, caches, prefetcher,integer ALUs, LFSR, Booth multiplier, iterative dividerIEEE-754/2008 floating-point unitsprocessor + uncore building blocks
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RISC-V ISA and Rocket-Chip – BAR 24
Open Source Berkeley ISASupports GCC, LLVM, LinuxAccelerator InterfaceGrowing Adoption – LowRisc etcRocket-Chip is Processor Generator in Chisel
http://www.riscv.org
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NOC + SOC Builder – LBNL 25
NOCMemory BlocksIO / AXI interfaces
SOC NOC
http://opensocfabric.lbl.gov/
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Our Steps – “the Chisel Plan” 26
1 generation – use good software ideas – embedded host language2 composition – design by composing bigger reusable pieces3 transformation – specification + transformations = FIRRTL4 optimization – parameterization + design space exploration5 layering – incrementally higher level and strategic6 simulation – speed up testing and evaluation methods7 realization – fast + affordable deployment technology
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(3) Graph Transformations 27problem
designs are too complex and obfuscated with optimizationssolution
factor design intosimple specification +composable and reusable graph transformations
standard RTL core called FIRRTL (virtually impossible in verilog)file formats and APIlanguage neutral
Reg
Reg
Reg
Reg
Reg
Reg
Ctr
Ctr
Ctr
input => outputprogrammatic insertion of activity counters on registers
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LLVM Success 28
clean intermediate representation (IR) for codedefined APIfile formattools
easier to writefront-endstransformational passesback-ends
leads to explosion inlanguagescompilersarchitectures
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FIRRTL – Patrick Li 29
Flexible Intermediate Representation for RTL ( FIRRTL )language neutral RTL IR with text format“LLVM for hardware”simple coresemantic / structural informationannotations
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FIRRTL Flow 30
Chisel
FIRRTL FIRRTL VerilogFIRRTL
C++
Verilog
Chipper DREAMER
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Example Passes 31
rate balancingauto pipeliningauto threadingunrolling
evaluation and debugactivity counterssnapshot dumping / restoring
additional featuresfault tolerance
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Our Steps – “the Chisel Plan” 32
1 generation – use good software ideas – embedded host language2 composition – design by composing bigger reusable pieces3 transformation – specification + transformations = FIRRTL4 optimization – parameterization + design space exploration5 layering – incrementally higher level and strategic6 simulation – speed up testing and evaluation methods7 realization – fast + affordable deployment technology
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(4) Design Space Exploration – Izraelevitz et al 33problem
hard to find great designs by hand
solution: facility for parameterizing and searching design spacecalled Jackhammer – autotuner for hardwareframework for organizing parameterslanguage for specifying objective functionparallel mechanism for optimizing over design space
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Parameterization Challenge – Izraelevitz et al 34
simple solution doesn’t work:
class Cache(lineSize: Int, ...) extends Module ...
need first class parametersorganize parameters and thread through constructionwant to split specification from hierarchy from explorationdesigns are hierarchical and need to specify various elementswhat’s minimal description that is robust to changes in hierarchy?how to constrain parameters?how to export design space?
got a solution in Chisel ...
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Exploration Results – Israelivitz et al 35
tuning parameters on rocket-chip on workloadsability to launch thousands of results on clusterpresent pareto optimal plots
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Our Steps – “the Chisel Plan” 36
1 generation – use good software ideas – embedded host language2 composition – design by composing bigger reusable pieces3 transformation – specification + transformations = FIRRTL4 optimization – parameterization + design space exploration5 layering – incrementally higher level and strategic6 simulation – speed up testing and evaluation methods7 realization – fast + affordable deployment technology
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(5) Layered Languages 37
problemHLS is intractableno dominant design language (silver bullet)
solution:series of layered languagesmix and match strategieszero or measurable overhead
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Our Steps – “the Chisel Plan” 38
1 generation – use good software ideas – embedded host language2 composition – design by composing bigger reusable pieces3 transformation – specification + transformations = FIRRTL4 optimization – parameterization + design space exploration5 layered languages – incrementally higher level and strategic6 simulation – speed up testing and evaluation methods7 realization – fast + affordable deployment technology
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(6) Simulation: Fast Evaluation and Testing 39
problemsimulation/evaluation is a big bottleneckchoose fast runtime or fast compile timedifficult to debug hardware
solutionpay as you go emulation with DREAMERstatistical power estimationcycle accurate multicore on multicore
program build
eval fab
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C++ Simulator 40
cycle accurate simulatoreasy way to debug designs
compiles Chisel to one C++ classexpand multi words into single word operationstopologically sorts nodes based on dependencies
simulates using two phasesclock_lo for combinationalclock_hi for state updates
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Simulator Comparison 41
Comparison of simulation time when booting Tessellation OS
Simulator Compile Compile Run Run Total TotalTime (s) Speedup Time (s) Speedup Time (s) Speedup
VCS 22 1.000 5368 1.00 5390 1.00Chisel C++ 119 0.184 575 9.33 694 7.77Virtex-6 3660 0.006 76 70.60 3736 1.44
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Simulation Crossover Points 42
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Scalable Simulation – Bachrach + Lawson 43
work in progress ...OpenNOC pushing our C++ backend toolsscalable compile time and run time performanceautomatically split graph into combinational islandscan split into separate functions/filesparallize compilation and executionalready have much better compile timesx86 barrier runs at a 1MHzcould scale up multicore cycle accurate simulation
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Debug Interface – Richard Lin 44
standard protocol text based protocolpeek poke step snapshot ...
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Tester – Magyar + Twigg 45
scala interface to debug interface using chisel namesadvanced tester allows decoupled support
class Stack(val depth: Int) extends Module {val io = new Bundle {val push = Bool(INPUT)val pop = Bool(INPUT)val en = Bool(INPUT)val dataIn = UInt(INPUT, 32)val dataOut = UInt(OUTPUT, 32)
}val stack_mem = Mem(UInt(width = 32), depth)val sp = Reg(init = UInt(0, width = log2Up(depth+1)))val dataOut = Reg(init = UInt(0, width = 32))when (io.en) {when(io.push && (sp < UInt(depth))) {stack_mem(sp) := io.dataInsp := sp + UInt(1)
} .elsewhen(io.pop && (sp > UInt(0))) {sp := sp - UInt(1)
}when (sp > UInt(0)) {dataOut := stack_mem(sp - UInt(1))
}}
io.dataOut := dataOut}
class StackTests(c: Stack) extends Tester(c) {var nxtDataOut = 0val stack = new ScalaStack[Int]()for (t <- 0 until 16) {val enable = rnd.nextInt(2)val push = rnd.nextInt(2)val pop = rnd.nextInt(2)val dataIn = rnd.nextInt(256)val dataOut = nxtDataOutif (enable == 1) {if (stack.length > 0)nxtDataOut = stack.top
if (push == 1 && stack.length < c.depth) {stack.push(dataIn)
} else if (pop == 1 && stack.length > 0) {stack.pop()
}}poke(c.io.pop, pop)poke(c.io.push, push)poke(c.io.en, enable)poke(c.io.dataIn, dataIn)step(1)expect(c.io.dataOut, dataOut)
}}
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Our Steps – “the Chisel Plan” 46
1 generation – use good software ideas – embedded host language2 composition – design by composing bigger reusable pieces3 transformation – specification + transformations = FIRRTL4 optimization – parameterization + design space exploration5 layered languages – incrementally higher level and strategic6 simulation – speed up testing and evaluation methods7 realization – fast + affordable deployment technology
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(7) Create Affordable Deployment Technology 47
problemfabbing ASICSs is expensive and time consumingFPGAs are hard to program and use
solutionnew coarse grained “FPGA”* based on DREAMERfast / open source tools
program build
eval fab
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Chisel versus Hand-Coded Verilog 48
3-stage RISCV CPU hand-coded in VerilogTranslated to ChiselResulted in 3x reduction in lines of codeMost savings in wiringLots more savings to go ...
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UC Berkeley Classes 49
3x CS152 – Undergraduate Computer ArchitectureSodor edu cores – 1/2/3/5 stage, microcode, out of order, ...Multicore and Vector
3x CS250 – VLSI System DesignProcessorsImage ProcessingRISC-V Rocket Accelerators
1x CS294-88 – Declarative Design SeminarHigh Level SpecificationAutomated Design Space Exploration
1x EE290C – Advanced Topics in CircuitsDSP ASICSSoftware Defined Radio
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Chisel Projects 50
SOC and NOC generator – Lawrence Berkeley National LabsNOC generator – Microsoft ResearchOblivious RAM – Maas et al @ BerkeleyGarbage Collector – Maas et al @ BerkeleyOut of Order Processor Generator – Celio et al @ BerkeleySpectrometer Chip – Nasa JPL / BerkeleyMonte Carlo Simulator – TU KaiserslauternPrecision Timed Machine (Patmos) – EC funded projectPrecision Timed Machine (PRET) – Edward Lee’s GroupChisel-Q – Quantum Backend – John Kubiatowicz’s GroupGorilla++ – Abstract Actor Network LanguageLowRisc – New Raspberry Pi SOCRiscV Processors and Uncore – Madras IITEvidence of many other projects on mailing lists
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Related Work 51
Feature Verilog SystemVerilog Bluespec ChiselADTs no yes yes yesDSLs no no no yes
FP no no yes yesOOP no no yes yesGAA no no only yes*
open source yes** no no yes
where ADT is Abstract Data Types, DSL is Domain Specific Language,FP is Functional Programming, OOP is Object Oriented Programming,and GAA is Guarded Atomic Actions.
* can layer it on top of Chisel** although simulator free, rest of tools still cost money
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Conclusions 52
Advocated a six step plan1 generation – use best software engineering ideas2 composition – bigger pieces and network effects3 transformation – spec + transformations FIRRTL4 layers – incrementally higher level and focussed5 optimization – design space exploration6 simulation – speed up testing and evaluation methods7 realization – fast + affordable deployment technology
Note thatbetter RTL design is already a winchisel library and community are growingthere are huge opportunities for improving design cyclethere are lots of low hanging fruit along the way
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Current But Lesser Known Features 53
fix point typesfloating point typescomplex numbersparameterizationjackhammermultiple clock domainsOpenNOC – http://opensocfabric.lbl.gov/
debug apichisel random testerFIRRTL draft spec ASAP
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Features Available in Next 3-6 Months 54basics
llvm backendcomposition
software definedplatformsarduino for fpga’sprocessor toolkitadvanced cookbookROCC acceleratorsstandard librarylibrary mechanismadvanced cookbook
spec + transformationFIRRTL implementationChisel 3.0 + FIRRTLtranformations
scan chainsauto pipelining...
declarativeDSE DSL
layered languagesstreaming DSP DSLtransactor DSL
simulationchisualizerdebug machine on fpga’sstatistical power samplingmulticore on multicoresimulation
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Next Steps to Learn Chisel 55
Website – chisel.eecs.berkeley.edu
Getting Started Guide – documentationRoCC Labs – NextSodor Cores – https://github.com/ucb-bar/riscv-sodor/
Rocket Chip Generator – www.riscv.org
Bootcamp at HPCA – http://darksilicon.org/hpca
Chisel Sources – https://github.com/ucb-bar/chisel/
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Chisel Bootcamp at HPCA 56
Workshop / BootcampHPCA – IEEE High Performance Computer ArchitectureAll Day Saturday Feb 7thSan Francisco Airport Marriott Waterfront HotelRegister – http://darksilicon.org/hpca
Sign up for chisel tutorial on saturday
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Getting the Chisel Tutorial 57
git clone https://github.com/ucb-bar/chisel-tutorial.git
cd chisel-tutorial
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Chisel Resources 58
https://chisel.eecs.berkeley.edu/documentation.html
getting started getting-started.pdf
tutorial tutorial.pdf
manual manual.pdf
https://github.com/ucb-bar/chisel/
setup readme.md
utils src/main/scala/ChiselUtils.scala
https://chisel.eecs.berkeley.edu/download.html
sodor https://github.com/ucb-bar/riscv-sodor/
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Scala Resources 59
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Keep in Touch 60
website chisel.eecs.berkeley.edu
mailing list groups.google.com/group/chisel-users
github https://github.com/ucb-bar/chisel/
features + bugs https://github.com/ucb-bar/chisel/issues
more questions stackoverflow.com/quesions/tagged/chisel
twitter #chiselhdl
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Funding 61
funding initiated underProject Isis: under DoE Award DE-SC0003624.Par Lab: Microsoft (Award #024263) and Intel (Award #024894)funding and by matching funding by U.C. Discovery (Award#DIG07-10227). Additional support came from Par Lab affiliatesNokia, NVIDIA, Oracle, and Samsung.
ongoing support fromASPIRE: DARPA PERFECT program, Award HR0011-12-2-0016.Additional support comes from Aspire affiliates Google, Intel, Nokia,Nvidia, Oracle, and Samsung.CAL (with LBNL): under Contract No. DE-AC02-05CH11231.