chipstart soc system manager (ssm) non-nda overview
DESCRIPTION
As complex SoCs continue to evolve towards platforms capable of supporting thousands of applications, so is the complexity of architecting, testing and assuring the multitude of hardware state changes on the SoC that grow at an exponential rate because of the multicore nature of SoCs and the programmable processors used on them. The paper submitted and this presentation focuses on the growing challenges of management boot and reset sequencing, error recovery, and even power and security management which we combined to call system management, and how system management can be optimized under very complex operations.TRANSCRIPT
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SoC System Manager (SSM)
The Industry’s First SoC IP Subsystem forPolicy Based System Management
Processor SubsystemMultilevel Complex InterconnectsOut of Band SignalingMemory Access Scheduling
Processor SelectionBus SelectionArbitration LogicOff Chip Memory Sharing
Evolution of Multicore SoCs
2
Core 1 Core 2
I/O MemCtl
Circa 2002Core
1
Processor Subsystem
VideoProcessing
AudioProcessing
Core 2
I/O Subsystem
Global Interconnect
MemoryScheduler &Controller
COMProcessing
Circa 2012
Design Challenges Grow
System Management Has NOT Evolved at Same Pace as Complexity Growth (Reset, Boot, Error Recovery, Power Management, Memory Access)
3
Shift to Policy Based System Management
Software Controlled Hardware State ManagementWith Full System Control and Dynamic System Adoption
Add control plane framework and abstract
system management into a software driven
architecture
Allow software policies to DYNAMICALLY drive system operations in
real time
4
Introducing SSM:Industry’s First Policy Based System Management Subsystem IP
Dynamically Load Software Policies into Programmable SSM Controller
Core 1
Processor Subsystem
VideoProcessing
AudioProcessing
Core 2
I/O Subsystem
Global Interconnect
MemoryScheduler &Controller
COMProcessing
SS
MC
on
tro
lle
r
Power Management 1
Power Management 2
Security Policies
Reset Policy 1
Reset Policy 2
Error Recovery 1
Error Recoveryt 2
Soft Boot Sequencing
Hard Boot Sequencing
SSM Controller Converts Software Policies to Hardware Signals and Routes to Connected Hardware Blocks via SSM Bus
Policies
SSM Also Supports Message Passing to Hardware
Host Processor Triggers Policy Changes
Video OptimizedPolicy Suite
5
Dynamic System Adoption:Real Time System Management Based on User Behavior
Power Management 1
Video Optimized Security
Reset Policy 1
Error Recovery 1
Soft Boot Sequencing
Hard Boot Sequencing
Streaming Memory Schedules
Data OptimizedPolicy Suite
Power Management 2
Internet Security
Reset Policy 2
Error Recovery 2
Soft Boot Sequencing
Hard Boot Sequencing
Packet Memory Schedules Version UpdatePolicy Suite
Power Management 1
Version Update Sequence
Offline Sequencing
Testing Sequences
Soft Boot Sequencing
Hard Boot Sequencing
Memory Flush and Updating
Application Use TriggersOptimized Policy Suite Loading
Also Ideal for Controlled Version Update Sequencing
The “Ripple Savings” Effect
Architecture Standardizes system management modeling via a uniform high-reuse architecture
that yields predictable system operation EARLY in the design cycle Design Pre-defined software based functions replaces ad hoc hardware based equivalentsVerification Verification policy suites accelerates unit and system check out and error isolationSoftware Development Enables system software to be developed early in hardware development cycle
Bring Up and Test Enables step by step bring up, test, and debugging.
Production Engineering Mature policy suites developed during deign phase are immediately available for
production test use.
These Savings Multiply During Development
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SSM Technical Overview
8
SSM Hardware Connectivity
• SSM Controller connects to SSM Bus• SSM Register blocks connect to appropriate IP block signals• SSM Controller IDs register blocks• SSM Signaling mapped to appropriate IP block signals via SSM Register Block Map
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A Load and Execute Operation Model
• Host Processor (Subsystem) Loads Appropriate Policy Suite From System RAM to SSM Controller SRAM
• SSM Controller Converts Policy Suite Commands to Hardware Signals • SSM Posts Signals on SSM Bus and SSM Register Block ID(s)
• SSM Register Blocks Read Signals and Map to IP Block Signals
SSM Controller SupportsConditional or Unconditional Command Execution
SSMController
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Policy Based Soft Reset Example
Suspend DSP; Send message to DSP O/S on DSP, Wait for ACK, toggle IP core enable signal inactive
Suspend MPE; Same as above
Reset Host; Send message to host O/S, wait for ACK, toggle reset
Resume DSP; Activate enable signal, send message to DSP O/S
Resume MPE; Same as above
Controlled Sequencing for Safe ShutdownAnd Predictable Bring Up
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IP Video Example
OFF
OFF
ONOFF
OFF
IP Video Policies
Store IP Packets
ON
De-encapsulate
ON
ON
Application Linked Power Management
ONON
Process Video
Conditional Policy Execution:Host Processor Toggles SSM Policy Sequencing
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SSM Hardware Connectivity
• SSM Controller connects to SSM Bus• SSM Register blocks connect to appropriate IP block signals• SSM Controller IDs register blocks• SSM Signaling mapped to appropriate IP block signals via SSM Register Block Map
13
SSM Hardware Connectivity
• SSM Controller connects to SSM Bus• SSM Register blocks connect to appropriate IP block signals• SSM Controller IDs register blocks• SSM Signaling mapped to appropriate IP block signals via SSM Register Block Map
14
SSM Advantages
Provides global control of all managed IP blocks Guaranteed synchronization between hardware and
software while executing complex sequences Virtualization of system management functions
Replaces logic and arbitration with policy driven softwareDirectly links state sequencing with application behavior
Lowers Overall Design ComplexityImproves Applications Execution
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