chip synthesis workshop 1392

Table of Contents

31833-000-S16B i Synopsys Chip Synthesis Workshop

Day 1: Pre-Synthesis Processes

Introduction & Overview

Workshop Goal.................................................................................................................. i-3

Workshop Prerequisites...................................................................................................... i-4 Workshop Target Audience ................................................................................................ i-5 Workshop Agenda.............................................................................................................. i-6

Unit 1: Introduction to Synthesis

Unit Objectives .................................................................................................................. 1-2 Just What Is Synthesis? .................................................................................................. 1-3

Synthesis is Constraint-Driven............................................................................................ 1-7 Synthesis is Path-Based...................................................................................................... 1-8 Chip Synthesis Process ..................................................................................................... 1-9 Design Compiler Interfaces............................................................................................... 1-10

Need Help? .................................................................................................................... 1-11 Search in Acrobat Reader ................................................................................................ 1-12 Module Synthesis Roadmap............................................................................................. 1-13 Analyze, Elaborate - Read................................................................................................ 1-14

Unit 2: Setup, Libraries, and Objects Chapter Overview.............................................................................................................. 2-3 Synthesis Review ............................................................................................................... 2-4 Technology Library............................................................................................................ 2-5

Target Library.................................................................................................................... 2-6 Link Library Variable ......................................................................................................... 2-7 Use link to Resolve Design References ............................................................................... 2-9 The search_path Variable ................................................................................................. 2-10

Design Compiler Interfaces............................................................................................... 2-13 Design Compiler Three Initialization Files.......................................................................... 2-14 .synopsys_dc.setup File: Example..................................................................................... 2-15 .synopsys_dc_setup: Tcl and dcsh Mode.......................................................................... 2-16

Design Objects: VHDL Perspective.................................................................................. 2-18 Design Objects: Verilog Perspective ................................................................................. 2-19

Table of Contents

31833-000-S16B ii Synopsys Chip Synthesis Workshop

Design Objects: Schematic Perspective............................................................................. 2-20 Multiple Objects with the Same Name.............................................................................. 2-21

The get Command............................................................................................................ 2-22 What Is a List?................................................................................................................. 2-23 Other Handy List Commands........................................................................................... 2-25 Finding objects with dc_shell-t.......................................................................................... 2-26

Appendix - Synopsys DesignWare................................................................................... 2-32

Unit 3: Partitioning for Synthesis

What is Partitioning?........................................................................................................... 3-3 Why Partition a Design? .................................................................................................... 3-4 Partitioning Within the HDL Descrip tion.............................................................................. 3-5

Eliminate Unnecessary Hierarchy........................................................................................ 3-6 No Hierarchy Dividing Combinational Paths........................................................................ 3-7 Partition at Register Boundaries .......................................................................................... 3-9 Avoid Glue Logic: Example .............................................................................................. 3-10

Balance Block Size With Run Times ................................................................................. 3-12 Separate Core Logic, Pads, Clocks, and JTAG................................................................ 3-14 Partitioning Within Design Compiler.................................................................................. 3-15 The group Command ....................................................................................................... 3-16

The ungroup Command.................................................................................................... 3-17 Partitioning Strategies for Synthesis................................................................................... 3-19

Unit 4: Coding for Synthesis

The Importance of Quality of Source .................................................................................. 4-3 RTL Coding Guide............................................................................................................. 4-4

The Big Picture: Think Hardware! ...................................................................................... 4-5 The Big Picture: Think Synchronous! ................................................................................. 4-6 The Big Picture: Think RTL! .............................................................................................. 4-7 RTL Synthesis Cookbook.................................................................................................. 4-8

Synthesis of if Statements............................................................................................... 4-9 if-else Statements ............................................................................................................. 4-10 if Statements and Latches ................................................................................................. 4-12 if-then-elseif Statements.................................................................................................... 4-13

Priority Interrupt Circuit - Synthesis Results ...................................................................... 4-15

Table of Contents

31833-000-S16B iii Synopsys Chip Synthesis Workshop

When NOT to Use if-then-elseif ...................................................................................... 4-16 Synthesis of case Statements ........................................................................................... 4-17

case Statements .............................................................................................................. 4-18 Synthesis of loop Statements ............................................................................................ 4-25 Unrolling Loops ............................................................................................................... 4-26 Tradeoffs with Loops....................................................................................................... 4-27

Hardware Result .............................................................................................................. 4-28 Recoded Loop................................................................................................................. 4-29 Synthesis of Flip-Flops..................................................................................................... 4-30 Inferring Sequential Devices.............................................................................................. 4-31

Synthesis of Arithmetic Circuits......................................................................................... 4-34 Inferring Arithmetic Parts.................................................................................................. 4-35 DesignWare Arithmetic Resources.................................................................................... 4-36 DesignWare Implementation Selection.............................................................................. 4-37

Implying a Structure by Operand Placement...................................................................... 4-39 Verilog Preprocessor Directive ......................................................................................... 4-41 Appendix: Verilog Inference and Instantiation.................................................................... 4-44

Day 2: Constraining the Design

Unit 5: Timing and Area

RTL Block Synthesis.......................................................................................................... 5-3 Specifying an Area Goal..................................................................................................... 5-4 Timing Goals: Synchronous Designs.................................................................................... 5-5

Defining a Clock ................................................................................................................ 5-7 Defining a Clock in Design Compiler................................................................................... 5-8 Timing Goals: Synchronous Designs, I/O............................................................................. 5-9 Constraining the Input Paths ............................................................................................. 5-10

set_input_delay: Effect on Input Paths............................................................................... 5-13 Constraining Output Paths of a Design.............................................................................. 5-14 set_output_delay: Effect on Output Paths.......................................................................... 5-17 Useful Commands............................................................................................................ 5-19

Unit 6: Environmental Attributes

RTL Block Synthesis.......................................................................................................... 6-3

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31833-000-S16B iv Synopsys Chip Synthesis Workshop

Constraining for Timing Whats Missing? ........................................................................ 6-4 Describing Environmental Attributes.................................................................................... 6-5

Modeling Capacitive Load ................................................................................................. 6-6 set_load examples.............................................................................................................. 6-7 Modeling Input Drive Strength............................................................................................ 6-8 set_driving_cell Examples .................................................................................................. 6-9

Variations in cell delays .................................................................................................... 6-10 Operating Conditions ....................................................................................................... 6-11 Net delays ....................................................................................................................... 6-14 What is a Wire load model? ............................................................................................ 6-15

Specifying Wire Loads in Design Compiler ....................................................................... 6-17 Wireload Model Mode .................................................................................................... 6-18 Check Your Constraints .................................................................................................. 6-19 Appendix - Create an Operating Condition....................................................................... 6-25

Unit 7: Time and Load Budgeting

RTL Block Synthesis.......................................................................................................... 7-3 Time Budgeting .................................................................................................................. 7-4 Load Budgeting.................................................................................................................. 7-8 Summary of Describing Constraints .................................................................................. 7-14

Unit 8: Timing Analysis

Does Your Design Meet its Goals?..................................................................................... 8-3 Timing Analysis: What Tool Do I Use? .............................................................................. 8-4 Static Timing Analysis......................................................................................................... 8-5 Timing Paths in Design Compiler......................................................................................... 8-6

Organizing Timing Paths Into Groups .................................................................................. 8-7 Schematic Converted to a Timing Graph........................................................................... 8-10 Components of Static Timing Analysis .............................................................................. 8-11 How DesignTime Calculates Delays ................................................................................. 8-12

Non-Linear Delay Model................................................................................................. 8-13 Wire Delay Calculations and Topology............................................................................. 8-15 Operating Conditions ....................................................................................................... 8-16 Edge Sensitivity in Path Delays ......................................................................................... 8-17

Setup Relationship Between Flip-Flops............................................................................. 8-18

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31833-000-S16B v Synopsys Chip Synthesis Workshop

DesignTime Timing Reports.............................................................................................. 8-19 Timing Report: Path Information Section........................................................................... 8-20

Timing Report: Path Delay Section.................................................................................... 8-21 Timing Report: Path Required Section............................................................................... 8-22 Timing Report: Summary Section...................................................................................... 8-23 Timing Report: Options .................................................................................................... 8-24

Timing Analysis: Diagnose Synthesis Results...................................................................... 8-25

Unit 9: DC Shell Tcl Interface

What is Tcl?....................................................................................................................... 9-4 Why Tcl? .......................................................................................................................... 9-5 Converting from dc_shell to dc_shell t............................................................................... 9-6

Executing DC-Tcl Script.................................................................................................... 9-7 Getting Help....................................................................................................................... 9-8 Comments in DC-Tcl....................................................................................................... 9-11 Nesting Commands and Quoting ...................................................................................... 9-12

Using Wildcards............................................................................................................... 9-13 Tcl Data Types ................................................................................................................ 9-14 Using Variables................................................................................................................ 9-15 Arithmetic Expressions ..................................................................................................... 9-17

Using Lists in dc_shell-t.................................................................................................... 9-18 Definitions: Objects and Attributes.................................................................................... 9-19 Definitions: Collections & Collection Handle ..................................................................... 9-20 Creating Collections ......................................................................................................... 9-21

Manipulating Collections................................................................................................... 9-23 Filtering Collections.......................................................................................................... 9-26 Running dc_shell t Interactively ....................................................................................... 9-27

Day 3: Synthesizing the Design

Unit 10: Timing Revisited

Timing Goals: Part Two.................................................................................................... 10-5 Modeling Clock Trees...................................................................................................... 10-6 Modeling Uncertainty on Clock Edges.............................................................................. 10-7

set_clock_uncertainty and Setup Timing............................................................................ 10-8

Table of Contents

31833-000-S16B vi Synopsys Chip Synthesis Workshop

Modeling Source Latency................................................................................................. 10-9 Pre/Post Layout Clock................................................................................................... 10-10

Multiple Clocks - Synchronous....................................................................................... 10-11 Synchronous Multiple Clock Designs.............................................................................. 10-12 Creating a Virtual Clock................................................................................................. 10-14 Timing Goals for Multiple Clock Designs ........................................................................ 10-15

Hints for Multiple Clock Designs ................................................................................... 10-20 Multiple Clocks - Asynchronous..................................................................................... 10-21 Asynchronous Multiple Clock Designs............................................................................ 10-22 Synthesizing with Asynchronous Clocks.......................................................................... 10-23

The set_false_path command.......................................................................................... 10-24 Timing Goals Summary................................................................................................... 10-26 check_timing.................................................................................................................. 10-27 Appendix: Multi-Cycle Behavior..................................................................................... 10-29

Unit 11: Optimization

Three Phases of Optimization........................................................................................... 11-3 Architectural Optimization ................................................................................................ 11-4 Arithmetic Operators........................................................................................................ 11-5 DesignWare Implementation Selection.............................................................................. 11-6

Other High-Level Optimizations........................................................................................ 11-8 Sharing Common Sub Expressions ................................................................................... 11-9 Coding To Force Sharing ............................................................................................... 11-10 Resource Sharing: Example ............................................................................................ 11-11

Operator Reordering...................................................................................................... 11-13 Reordering Operators for Fast Design ............................................................................ 11-14 High-Level Synthesis is Constraint-Driven ...................................................................... 11-15 Logic-Level Optimization ............................................................................................... 11-16

What is Structuring? ...................................................................................................... 11-18 What is Flattening? ........................................................................................................ 11-19 Structuring vs. Flattening................................................................................................. 11-20 Three Phases of Optimization......................................................................................... 11-21

Combinational Mapping................................................................................................. 11-22 Sequential Mapping ....................................................................................................... 11-23 Fixing Design Rule Violations.......................................................................................... 11-24

Table of Contents

31833-000-S16B vii Synopsys Chip Synthesis Workshop

Unit 12: Compile Strategies

Compile Completion ........................................................................................................ 12-3 User Interrupt.................................................................................................................. 12-5 Compile Report ............................................................................................................... 12-6

Compile Strategies........................................................................................................... 12-7 Constraint and Timing Analysis ......................................................................................... 12-8 Things to Look for ........................................................................................................... 12-9 Use Re-Compile ............................................................................................................ 12-12

Change the Effort Level.................................................................................................. 12-13 Use Incremental Mapping............................................................................................... 12-16 When You Have Design Rule Violations ........................................................................ 12-19 What if You Have Hold Time Violations? ...................................................................... 12-20

Checking For Hold Time Violations ............................................................................... 12-23 Use Simultaneous Min-Max .......................................................................................... 12-24 Apply set_input_delay For Hold Time ........................................................................... 12-25 Apply set_output_delay For Hold Time .......................................................................... 12-26

Calculation of set_output_delay...................................................................................... 12-27 Fixing Hold Violations .................................................................................................... 12-28

Unit 13: Compiling a Hierarchical Design

Compiling a Hierarchical Design Under the Hood........................................................... 13-3

Compiling a Hierarchy ..................................................................................................... 13-4 First Phase of Compile ..................................................................................................... 13-5 Second Phase of Compile ................................................................................................ 13-6 Resolving Multiple Instances............................................................................................. 13-7

Designs Instantiated More Than Once .............................................................................. 13-8 check_design................................................................................................................... 13-9 Methods to Resolve Multiple Instances........................................................................... 13-10 Method #1: uniquify ....................................................................................................... 13-11 Method 2: compile + dont_touch.................................................................................... 13-13 Using set_dont_touch..................................................................................................... 13-15 uniquify vs. compile + dont_touch.................................................................................. 13-16

Table of Contents

31833-000-S16B viii Synopsys Chip Synthesis Workshop

Unit 14: DC-Tcl Procedures

Control Flow: Examples................................................................................................... 14-3 Looping Structures........................................................................................................... 14-4 Tcl Procedures................................................................................................................. 14-6

Scope of Variables........................................................................................................... 14-8 Procedure Information...................................................................................................... 14-9 Tcl Procedure Example .................................................................................................. 14-10

Table of Contents

31833-000-S16B ix Synopsys Chip Synthesis Workshop

Day 4: Post-Synthesis Processes

Unit 15: Compiling a Large Design

Techniques for Compiling a Hierarchical Design ................................................................ 15-3 Hierarchical Compile Techniques: Types........................................................................... 15-4

Top-Down Compile Methodology.................................................................................... 15-5 Advantages of Top-Down................................................................................................ 15-6 Simple Compile Mode ..................................................................................................... 15-7 Hierarchical Compile Techniques...................................................................................... 15-8

Bottom-Up Compile Methodology................................................................................... 15-9 Pros & Cons of Bottom-Up Compile ............................................................................. 15-12 Techniques for the Second-Pass Compile ....................................................................... 15-14 Problems After the First-Pass Compile ........................................................................... 15-15

Use report_constraint -all............................................................................................... 15-16 Use report_timing........................................................................................................... 15-17 Build a New Design Budget............................................................................................ 15-22 characterize.................................................................................................................... 15-23

Appendix - Design Budgeter .......................................................................................... 15-30

Unit 16: Design Exploration

Traditional Reactive Flow................................................................................................. 16-4 Proactive Design Methodology......................................................................................... 16-6 Design Exploration........................................................................................................... 16-7

Typical Compile Script (Basic) ....................................................................................... 16-11 Special WLM for Ports.................................................................................................. 16-13 set_max_capacitance ..................................................................................................... 16-15 set_max_transition.......................................................................................................... 16-16

set_max_fanout.............................................................................................................. 16-17 Fanout Loads................................................................................................................. 16-18 Fastest Runtimes for Design Exploration......................................................................... 16-21 Scenarios: Exploring Subdesigns..................................................................................... 16-23

I/O Timing Constraint Options........................................................................................ 16-28 Exploring Combinational Paths ....................................................................................... 16-30 User-Defined Path Groups ............................................................................................. 16-31

Table of Contents

31833-000-S16B x Synopsys Chip Synthesis Workshop

Path Groups vs Critical Range........................................................................................ 16-34

Unit 17: Synthesizing for Test

Chip Defects: Theyre Not My Fault! ............................................................................... 17-3

Manufacturing Defects...................................................................................................... 17-4 Why Test for Manufacturing Defects? .............................................................................. 17-5 How Is Manufacturing Test Performed? ........................................................................... 17-6 The Stuck-At Fault Model ............................................................................................... 17-7

Controllability................................................................................................................... 17-9 Observability.................................................................................................................. 17-10 Fault Coverage .............................................................................................................. 17-11 Testing a Multistage, Pipelined Design............................................................................. 17-12

Scan Chains Help .......................................................................................................... 17-13 Use One-Pass Scan Synthesis ........................................................................................ 17-15 DFT Checking: Example ................................................................................................ 17-17 Testability Violation: Example......................................................................................... 17-18

Running ATPG............................................................................................................... 17-19 What Is DFTC?............................................................................................................. 17-20 Test Tools Summary ...................................................................................................... 17-22 Synthesizing for Test Summary ......................................................................................... 17-2

Unit 18: Conclusion

Some Thoughts on Coding ............................................................................................... 18-3 Synthesis Quality Depends on Algorithms!........................................................................ 18-4 Classic Algorithms, Architectures, & Tradeoffs ................................................................. 18-5 Reflections on Synthesis: .................................................................................................. 18-6

Pre-Compile Checklist ..................................................................................................... 18-7 What Do You Do First? .................................................................................................. 18-8 Compile Strategy ............................................................................................................. 18-9 Timing Analysis to Diagnose the Problem........................................................................ 18-10

Need More Training? .................................................................................................... 18-12 Advanced Chip Synthesis ............................................................................................... 18-13 Coding Styles for Synthesis ............................................................................................ 18-14 Need More Information or Help? .................................................................................. 18-15

Synopsys on the World Wide Web................................................................................ 18-16

Table of Contents

31833-000-S16B xi Synopsys Chip Synthesis Workshop

How to Use solv-NET! ................................................................................................. 18-17 Human Sources for Information and Help ....................................................................... 18-18

Other Sources for Information and Help ......................................................................... 18-19

i-1

IntroductionChip Synthesis Workshop Synopsys 31833-000-S16

For BHNEC internal use only.

For BHNEC internal use only.

Chip Synthesis Workshop

31833-000-S16

Synopsys Customer Education Services 2000 Synopsys, Inc. All Rights Reserved

i-2


First Things First

? Instructor Introduction

? Student Guide

? Lab Guide

? Measurement of Learning Objectives

i-3


Workshop Goal

Acquire the basic skills to synthesize a design

using Synopsys Design Compiler

i-4


Workshop Prerequisites

? Understanding of digital IC design

? Some knowledge of Verilog or VHDL

? Familiarity with UNIX and X-Windows

? Familiarity with a Unix-based text editor

i-5


Workshop Target Audience

? Board, FPGA, or ASIC-level Digital Designers

? Some Verilog or VHDL knowledge

? Little or no formal experience with Design Compiler

i-6


4 Day Workshop Agenda

Synthesizing the Design

Day3

Post-synthesis Processes

Day4

Constraining the Design

Day2

Pre-synthesis Processes

Day1

i-7


Icons Used in this Workshop

Lab Exercise

Question

Checklist

Hint, Tip, or Suggestion

Caution

Note

Remember

i-8


Abbreviations and Acronyms: Exercise

Acronym Meaning

DCDC

RTLRTL

HDLHDL

GTECHGTECH

SDFSDFSOLDSOLD

Acronym Meaning

DFTDFTPDEFPDEF

TclTclATPGATPG

1-1

Introduction to SynthesisChip Synthesis Workshop Synopsys 31833-000-S16

Agenda: Day 1

DAY1

Introduction to Synthesis1

Topic LabUnit

Setup, Libraries, and Objects2

Partitioning for Synthesis3

Coding for Synthesis4

1-2


Unit Objectives

After completing this unit you should be able to:

? List the basic steps of synthesis

? Describe advantages of synthesis

1-3


Just What Is Synthesis?

Synthesis is the transformation of an idea into a manufacturable device to carry out an intended function

1-4


Our focus will be here

Levels of Abstraction

IdeaIdea captured on back of envelope

Gate-LevelNetlist

Register TransferArchitectural HDL

BehavioralHDL and

simulation language

FunctionalGraphical or textual

description

Physical DeviceSilicon

1-5


For Our Purposes, Synthesis isSynthesis =

residue = 16h0000;if (high_bits == 2b10)

residue = state_table[index];else

state_table[index] = 16h0000;

HDL Source

Generic Boolean (GTECH)

Translate

Target Technology

Optimize + Map

Translation + Optimization + Mapping

1-6


Why Synthesis?

Productivity

How else to do 10 6 gates in 6 months?

PortabilityIEEE standards; HDL portable across tools;

technology-independent designs

VerifiableValidate, implement, &

verify in same language, Less error-prone entry

AbstractionFocus on high-level

issues; tool & computer do dirty work to meet

constraints

Design TricksDC knows plenty, tries

them in context of loads, fanouts, library limitations

ReusabilityParameterized code;

Building-block approach; Retarget new libraries;

Prestige

Impress friends; hot skill on resume; job security;

wealth and fame

Why Me?

1-7


Synthesis is Constraint-Driven

Design Compiler optimizes the design to meet your goals

Large

Area

Small

Short Delay High

You set the goals (through constraints)

1-8


Synthesis is Path-Based

D Q

QB

D Q

QBFF2 FF3

MY_DESIGN

A

CLK

Z How many timing paths do you see in MY_DESIGN?

Design Compiler uses Static Timing Analysis (STA) to calculate the timing of the paths in the design.

1-9


Chip Synthesis Process

Chip Specification

Partition Chip

Floorplan

RTL Block Synthesis

Integrate Blocks

Insert Test

Floorplan

Place & Route

Final Verification

1-10


Design Compiler Interfaces

Three ways to interface to Design Compiler (DC):

1 2

3 Design Analyzer

dc_shell (DCSH)dc_shell-t (DC-Tcl)

4

Design Visionin 2000.11 release

1-11


Need Help?

%SOLDacroread \

$SYNOPSYS/doc/online/top.pdf

%alias sman man -M \$SYNOPSYS/doc/syn/man

%setenv MANPATH ${MANPATH}:$SYNOPSYS/doc/syn/man

or

1-12


There are More than 4000 SOLV-IT! articles

Search in Acrobat Reader

Search allows you to scan all documents in SOLD

DownloadAcrobat Reader with Search

www.acrobat.com

1-13


write

Module Synthesis Roadmap

gtech.db

GTECH

my_chip.v(hd)

write

OPTIMIZATION + MAPPING

include

DC_MEMORY

TRANSLATION

scripts

constraints.scr

mappedmy_chip.dbmy_chip.edif

compileDC_MEMORY

MY_CHIP

core_slow.db

target_library

readHDL source

unmappedmy_chip.db

read

analyze/elaborate

Y=A+BMY_CHIP

1-14


Analyze, Elaborate - Read

analyzed

mychip.synmychip.sim(VHDL)mychip.mra

DC MEMORY

Y=A+BMYCHIP

mychip.vmychip.vhd

read -f verilog mychip.v

unmapped

mychip.db

write -ouput ./unmapped/mychip.db -hier

analyze -f vhdl mychip.vhd

elaborate MYCHIP

1-15


Summary: Exercise

Synthesis = __________ + __________ + __________

Advantages of Synthesis:____________________ ________________________________________

1-16


Lab 1: Introduction

LAB 25 min

Run through the basic Synthesis Flow using scripts

Save the design

Inspect the design

Synthesise the design

Constrain the design

Bring in the design

1-17


Appendix

Synopsys Physical Synthesis

1-18


Physical Challenge

1.0? 0.5? 0.25? 0.18?

Per

cen

tag

e o

f D

elay

Wir

eG

ate

Silicon Technology

1-19


Physical Synthesis

0.8? 0.5? to 0.35?

Place& Route

LogicSynthesis

Place& Route

LogicSynthesis

?0.25?

Physical Synthesis

Flow

Place& Route

1-20


Synopsys Physical Synthesis

FlexRoute:Detailed Top

Level RoutingPin

assignment

Design Compiler :Logic Synthesis

Chip Architect:Detailed PlacementCoarse RoutingGates

MicroController

DatapathModule Compiler :Specialized

Datapath Synthesis

Chip Architect:BudgetingEstimationFloor PlanningIO Placement

Memory

Memory

Physical Compiler:RTL Synthesis &

PlacementTogether

PlacedGates

2-1

Setup, Libraries, and ObjectsSynopsys Workshop Synopsys 31833-000-S16

Agenda: Day 1


Topic LabUnit

Setup, Libraries and Objects2



DAY1111

2-2


Unit Measurable Objectives

After completing this unit, you should be able to:

Specify the target library

Create the setup file for DC

Differentiate between the design objects

Find objects in DCSH mode and Tcl mode

2-3


Chapter Overview

TechnologyLibraries

DC Setup File

Design Objects

2-4


Your ASIC vendor must provide a DC-compatible technology library for synthesis!

Synthesis Review

Recall the 3 steps involved in synthesis: Translation Optimization Mapping

When DC maps a circuit, how will it know which cell library you are using?How will it know the timing of your cells?

2-5


Technology Library

Y = A | B

tcell ( OR2_3 ) {area : 8.000 ;pin ( Y ) {

direction : output;timing ( ) {

related_pin : "A" ;timing_sense : positive_unate ;rise_propagation (drive_3_table_1) {

values ("0.2616, 0.2608, 0.2831,..)}rise_transition (drive_3_table_2) {values ("0.0223, 0.0254, ...)

. . . .

function : "(A | B)";max_capacitance : 1.14810 ;min_capacitance : 0.00220 ;

}pin ( A ) {

direction : input;capacitance : 0.012000;

. . . .

Cell nameCell Area

Pin A -> Pin Y nominal delays (look-up table)

Design Rules for Output Pin

Electrical Characteristics of Input Pins

Pin Y functionality

A

BY

Example of a cell description in .lib Format

2-6


set target_library my_tech.db

Target Library Variable

The Target Library is the library used by Design Compiler for building a circuit

During mapping, DC will choose functionally-correct gates from this library calculate the timing of the circuit using vendor-supplied

timing data for these gates

target_library is a reserved variable in DC Set it to point to the library file(s) provided by your silicon

vendor

2-7


DC Memory*

TargetLibrary

Link Library Variable

Used to resolve design references

First DC searches the memory and then the library files specified in the link_library variable

Second DC searches the all paths defined in the search_path variable

set link_library {* my_tech.db}

2-8


Example

UNIX% dc_shell-tdc_shell-t> read_verilog source/ALU.v

Loading db file standard.sldbLoading db file gtech.dbLoading db file my_tech.dbLoading verilog file source/ALU.vCurrent design is now ALU

ALU.vmodule ALU (A,B,OUT1);input A, B;output [1:0] OUT1;always @(A or B)begin . . .

bob/ my_tech.db

DECODE.db

source/

TOP.vALU.v

set target_library my_tech.dbset link_library {* my_tech.db}

2-9


Use link to Resolve Design References

dc_shell-t> read_verilog source/ALU.vdc_shell-t> read_verilog source/TOP.vdc_shell-t> link

Unable to resolve reference DECODE in TOP

TOP.vmodule TOP (A,B,OUT1);input A, B;output [1:0] OUT1;ALU U1 (.AIN (A), . .DECODE U2 (.A (BUS0), . .

How do we tell DC to find DECODE.db in bob?

bob/ my_tech.db

DECODE.db

source/

TOP.vALU.v

set target_library my_tech.dbset link_library {* my_tech.db}

2-10


Set the search_path Variable

bob/ my_tech.db

DECODE.db

source/

TOP.vALU.v


dc_shell-t> read_verilog source/ALU.vdc_shell-t> read_verilog source/TOP.vdc_shell-t> link

Loading db file bob/DECODE.dbdc_shell-t> which DECODE.db

/server/my_project/bob/DECODE.db

set target_library my_tech.dbset link_library {* my_tech.db}lappend search_path {bob}

2-11


Use of analyze / elaborate

bob/ my_tech.db

DECODE.db

source/

TOP.vALU.v


dc_shell-t> analyze -f vhdl source/ALU.vhddc_shell-t> analyze -f vhdl source/TOP.vhddc_shell-t> elaborate TOP

Loading db file bob/DECODE.dbCurrent design is now TOP

Where do we specify the directory for the analyzed files?

set target_library my_tech.dbset link_library {* my_tech.db}lappend search_path {bob}

2-12


Chapter Overview

TechnologyLibraries

DC Setup File

Design Objects

2-13


Design Compiler Interfaces

Four ways to interface to Design Compiler (DC), the Synopsys synthesis engine:

Design Vision

In release 2000.11

dc_shell-t

dc_shell

design_analyzer

Design Analyzer

dcsh modedcsh mode

Design Compiler

(DC)

Tcl mode

design_vision (-tcl)

2-14


Design Compiler Three Initialization Files

.synopsys_dc.setup

.synopsys_dc.setup .synopsys_dc.setup

$SYNOPSYS/admin/setup~user

risc_design

Users Specific Project Setup

Users General Setup

StandardSetup

1

3

2

./command.log

commandlog

./view_command.logcompletelog of DAsession

2-15


.synopsys_dc.setup File: Example

target_library = "tc6a.db"link_library = {"*" tc6a.db opcon.db}

symbol_library = "tc6a.sdb"search_path = search_path + "./unmapped

alias h historyalias rc report_constraint -all_violators

2-16


.synopsys_dc.setup: Tcl and dcsh Mode

#set target_library {tc6a.db}set link_library {* tc6a.db opcon.db}

set symbol_library {tc6a.sdb}set search_path $search_path ./unmapped

alias h historyalias rc "report_constraint -all_violators"

2-17


Chapter Overview

TechnologyLibraries

DC Setup File

Design Objects

2-18


Design Objects: VHDL Perspective

entity TOP isport (A, B, C, D, CLK: in STD_LOGIC;

OUTI: out STD_LOGIC_VECTOR (1 downto 0));end TOP;architecture STRUCTURAL of TOP is

...

signal INV1, INV0, BUS1, BUS0: STD_LOGIC;

beginU1: ENCODER port map (AIN=>A, . . . Q1=>BUS1);U2: INV port map (A => BUS0, Z => INV0);U3: INV port map (A => BUS1, Z=> INV1);U4: REGFILE port map (D0=>INV0, D1=>INV1, . . CLK=>CLK);

end STRUCTURAL; Reference

Pin

Net

Design

Cell

Clock

Port

2-19


module TOP (A,B,C,D,CLK,OUT1);input A, B, C, D, CLK;output [1:0] OUT1;

wire INV1,INV0,bus1,bus0;

ENCODER U1 (.AIN (A), . . . .Q1 (bus1));

INV U2 (.A (BUS0), .Z( INV0)),U3 (.A( BUS1), .Z( INV1));

REGFILE U4 (.D0 (INV0), .D1 (INV1), .CLK (CLK) );

endmodule

Design Objects: Verilog Perspective

PinCell

Reference

Port

Design

Clock

Net

2-20


D0 Q[1:0]

D1

REGFILE

U4

OUT[1:0]INV0

INV1

AIN

BIN

CIN

DIN

Q0

Q1

ENCODER

INV

INV

U1U2

ABCD

CLK

BUS0

BUS1

A

B

CD

CLK

U3

TOP

Pin

CLK

Design Objects: Schematic Perspective

Clock

Reference and Design

Design Cell Net

Port

Designs: {TOP, ENCODER, REGFILE}References: {ENCODER, REGFILE , INV}Cells: {U1, U2, U3, U4}

2-21


Multiple Objects with the Same Name

set_load 5 CLK

Does CLK refer to a clock, port, net, or pin object?

Does it matter onto which object DC places the load?

ADD

A

B

AIN

BIN

S

A

B

SINSUM

CLKDFF

D

CLK

Q

U2

U1TOP

CLK

2-22


The get Command

Searches the current_design

Can be used stand-alone or composed with other functions

get commands return a list of object names, if any are found, or an empty list

dc_shell-t> set_load 5 [get_nets CLK]

2-23


What Is a List?

Lists are a key component of Design Compiler

A list is a special type of character string A list begins and ends with a curly brace {} Each item is separated by white space

dc_shell-t> set mylist {el1 el2 el3}Information: Defining new variable mylistel1 el2 el3

More to lists and objects in Chapter 9

2-24


ADDA

B

AI

BI

S

A

BSIN SOUT

SUM

CLKDFF

D

CLK

QU2

U1TOP

CLK

get Command Exercise

Write find commands to do the following:1. List all of the ports in the design

2. List all of the cells with the letter U in their name

3. List all of the nets ending with CLK

4. List all of the Q pins in the design

2-25


Other Handy List Commands

List all the input ports of the current design:dc_shell-t> all_inputs

List all the output ports of the current design:dc_shell-t> all_outputs

List all designs in the current design:dc_shell-t> get_designs

2-26


Finding objects with dc_shell-t

Many of the get commands shown previously have an individual DC-Shell equivalent:

dcsh modeget_cells *U* find(cell, *U*)get_nets * find(net, *)get_ports CLK find(port, CLK)get_clocks CLK find(clock, CLK)all_inputs all_inputs()all_outputs all_outputs()

Tcl mode

2-27


Lab Details: Directory Structure

Source code for the CPU has been analyzed, elaborated, and saved (in .db format ) in the unmapped subdirectory

NOTE: Always invoke Design Compiler from the risc_design directory!

risc_design/

source/ unmapped/ scripts/ mapped/ reports/

vhdl/ verilog/

2-28


Lab Details: Hierarchy of RISC_CORE

PRGRM_CNT_TOPALU

RISC_CORE

CONTROL DATA_PATHINSTRN_LAT REG_FILE

STACK_TOP

OUT_VALIDPSW[10:0]RESULT_DATA[15:0]Rd_InstrSTACK_FULL

CLK

Xecutng_Instrn[31:0]

Instrn[31:0]

Reset

EndOfInstrn

RISC_CORE

PRGRM_CNT

PRGRM_DECODE

PRGRM_FSM

2-29


Lab Details: Design Specifications

Clock Speed

Clock Skew

Voltage

Operating Temperature

Technology Library

Symbol Library

200MHz (5ns)

300 psec max

1.8V 0.18V

0 C to 125 C

core_slow.db

core.sdb

2-30


Lab Details: Exercise

From the specifications on the previous page, define the library setup variables:

set target_library

set link_library

set symbol_library

2-31


Lab 2: Introduction

LAB

Save the design

Inspect the design

Synthesize the design

Constrain the design

Bring in the design

PRGRM_CNT_TOP

PRGRM_CNT

PRGRM_DECODE

PRGRM_FSM

Introduction to Design Analyzerand the Synthesis Flow

60 min

2-32


Appendix: SynopsysSynopsysSynopsysSynopsys DesignWareDesignWareDesignWareDesignWare

SiliconLibraries

StandardCells

Memories+ ProMA

Memory Generator

I/Os0.1

8

0.15

0.13

BuildingBlocks

>100 Components:memBIST, LFSR,FIFO CTL, etc

+ - > * Pipeline Mult, Floating Point

ComplexIP Cores

MPEG2USB2.0 PCI-X

8051 PCI 16550...

DesignWareComplete Sourcefor Commodity IP

IP Packaging and Delivery

HDL DRC ToolsReuse Tools

StarIPs

e.g.,ARMMIPS

2-33


DesignWare Standard Cells

0.18m and 0.15m Optimized for Design Compiler Optimized for Module Compiler Optimized for Power Compiler Over 600 cells

simple and complex gates, buffers, flip flops, latches, complex cells, gated-clock cells

Actual silicon based on DesignWare

standard cells

2-34


Single-port synchronous SRAM Dual-port synchronous SRAM Two-port register file ROM

DesignWare ProMA Memory Generators

2-35


Synopsys Silicon Libraries

SynopsysSilicon

Libraries

Design Creation Verification & Analysis

High Level

Physical

Design CompilerModule CompilerPower CompilerBehavioral Compiler

DFT Compiler

COSSAPVCS, Scirocco

Verilog-XL ModelSim

VERA, FormalityPrimeTimeTetraMAX

RailMillPathMillTimeMill

PowerMill

ArcadiaDracula

Calibre, Hercules

FlexRouteChip ArchitectPhysical Compiler

ApolloSilicon Ensemble

3-1

Partitioning for SynthesisChip Synthesis Workshop Synopsys 31833-000-S16


Topic LabUnit




DAY1111

Agenda: Day 1

3-2


Unit Objectives

After completing this unit you should be able to:

List two effects of partitioning a circuit through combinational logic

State the main guideline for partitioning for synthesis

State how partitions are created in HDL code

List two DC commands for modifying partitions

3-3


Partitioning is the process of dividing complex designs into smaller parts

Divide and conquer!

What is Partitioning?

Ideally, all partitions would be planned prior to writing any HDL Initial partitions are defined by the HDL Initial partitions can be modified using Design Compiler

3-4


Focus will be on partitioning for synthesis

Why Partition a Design?

Partitioning is driven by many (often competing) needs: Separate distinct functions Achieve workable size and complexity Manage project in team environment Design Reuse Meet physical constraints And many, many others ...

3-5


ADR_BLK

DEC

OK

ADR

ASOK

INSTCLK

module ADR_BLK (...DEC U1(ADR,CLK,INST);OK U2(ADR,CLK,AS,OK);

endmodule

entity ADR_BLK is... end;architecture STR of ADR_BLK isU1:DEC port map(ADR, CLK, INST);U2:OK port map(ADR,CLK,AS,OK);

end STR;

U1

U2

Partitioning Within the HDL Description

entity and module statements define hierarchical blocksInstantiation of an entity or module also creates a new level ofhierarchy

Inference of Arithmetic Circuits (+, -, *, ..) can create a new level of hierarchy

process and always statements do not create hierarchy

3-6


CLK

REGA

COMBOLOGICA

A

COMBOLOGIC

B

B

COMBOLOGICC CLK

REGC

C

? ?

Are these partitions truly needed?

Eliminate Unnecessary Hierarchy

Design Compiler must preserve port definitions Logic optimization does not cross block boundaries

Adjacent blocks of combinational logic cannot be merged Path from REG A to REG C may be larger and slower

than necessary!

3-7


Better Partitioning

CLKCLK

REGA

REGC

COMBO LOGICA & B & C

A C

No Hierarchy in Combinational Paths

Related combinational logic is grouped into one blockNo hierarchy separates combinational functions A, B, and C

Combinational optimization techniques can now be fully exploited

3-8


Best Partitioning

CLK

REGA

CLK

REGC

COMBO LOGICA & B & C

A C

No Hierarchy in Combinational Paths (cont)

Related combinational logic is grouped into the same block with the destination register

Combinational optimization techniques can still be fully exploited

Sequential optimization may now absorb some of the combinational logic into a more complex Flip-Flop

(JK, T, Muxed, Clock-enabled)

3-9


Good Partitioning

CLK

REGA

A

CLK

REGB

B

CLK

REGC

C

Try to design so hierarchy boundaries follow register outputs.

Partition at Register Boundaries

Simplifies timing constraints:

All inputs to each block arrive with the same relative delay

3-10


Poor Partitioning

TOP

COMBOLOGIC C

CLK

REGC

COMBOLOGIC A

CLK

REGA

A C

COMBOLOGIC B

CLK

REGB

B

Avoid Glue Logic: Example

The NAND gate at the top level serves only to gluethe instantiated cells:Optimization is limited because the glue logic cannot be absorbed

3-11


Good Partitioning

Nothing but netsat top level

TOP

COMBOLOGIC C

+

GLUE

CLK

REGC

COMBOLOGIC A

CLK

REGA

A C

COMBOLOGIC B

CLK

REGB

B

Remove Glue Logic Between Blocks

The glue logic can now be optimized with other logic

Top-level design is only a structural netlist, doesnt need to be compiled

3-12


Poor Partitioning

Too Small

500Gates

TEENY

Too Big

100,000Gates

370,000Gates

8,000Gates

BIG

Balance Block Size With Run Times

If blocks are too small, the designer may be restricting optimization with artificial boundaries

If blocks are too big, compile run times can be very long

3-13


Good Partitioning

150,000Gates

BIGGER

50,000Gates

BIG

5,000Gates

SMALL

Balance Block Size With Run Times

For quick turnaround, partition so that each block has 5,000 - 150,000 gates

Design Compiler has no inherent limit

Match module size to CPU and memory: Larger modules are fine if sufficient resources are available Choose smaller sizes when workstation power is limited

3-14


Partition the Top-Level design into at least three levels of hierarchy:1. Top-level2. Mid-level 3. Core

Separate Core Logic, Pads, Clocks, and JTAG

CLOCK GEN

JTAG

CORE

MID

ASYNCH

This partitioning is recommended due to: Possible technology-dependent ( black box) I/O pad cells Possible untestable Divide By clock generation Possible technology-dependent JTAG circuitry

TOP

3-15


Partitioning within Design Compiler

The group and ungroup commands modify the partitions in a design

group ungroup

3-16


DES_A

TOP_DESIGN

U1

The group Command

group creates a new hierarchical block

group -design_name NEW_DES-cell_name U23{U2 U3}DES_A DES_B

TOP_DESIGN

U1 U2 U3

DES_C

NEW_DES

U23

DES_B DES_C

U2 U3

3-17


DES_A

TOP_DESIGN

U1 U23

DES_B DES_C

U2 U3

The ungroup Command

ungroup removes either one or all levels of hierarchy

TOP_DESIGN

DES_A

U1

NEW_DES

U23

NEW_DES

current_design NEW_DESungroup {U2 U3}

3-18


The ungroup Command: Exercise

ungroup {U23}DES_A

TOP_DESIGN

U1 U23

DES_Y DES_Z

U2 U3

DES_B

What happens if you ungroup U23?

3-19


Partitioning Strategies for Synthesis

Do not separate combinational logic across hierarchical boundaries

Place hierarchy boundaries at register outputs

Size blocks for reasonable runtimes

Separate core logic, pads, clocks, and JTAG

3-20


Partitioning for Synthesis: Summary

What do we gain by partitioning for synthesis?

Better results -- smaller and faster designs

Easier synthesis process -- simplified constraints and scripts

Faster compiles -- quicker turnaround

3-21


LAB

Lab 3: Introduction

Design Problem: Timing Violation

Change Partition for Better Synthesis Results

PRGRM_FSMPRGRM_DECODE PRGRM_CNT

30 mingroup / ungroup

4-1

Coding for SynthesisChip Synthesis Workshop Synopsys 31833-000-S16

Agenda: Day 1


Topic LabUnit




DAY1111

4-2


Unit Measurable Objectives

After completing this unit you should be able to: Describe hardware implications for the following

coding constructs: if-else case loops

Compile HDL code and observe the effects in synthesis

Use DesignWare elements in your RTL source code

4-3


The Importance of Quality of Source

Code that is functionally equivalent, but coded differently, will give different synthesis results

You cannot rely solely on Design Compiler to fixa poorly coded design!

Try to understand the hardware you are describing, to give DC the best possible starting point

PoorStartPoint

BetterStartPoint

BestStartPoint

Goal

4-4


RTL Coding Guide

HDL

Coding cookbook

The three big picture guidelines

4-5


The Big Picture, Think Hardware!

Write HDL hardware descriptions Think of the topology implied by the code

Do not write HDL simulation models No explicit delays No file I/O

after 20 ns and2 clock cyclesOUTPUT

4-6


ADDRDECODEADDR_IN

ACK

ACK_SET

AS

+5

ACK_CLR

How am I going to synthesize this?

The Big Picture, Think Synchronous!

Synchronous designs run smoothly through synthesis, test, simulation, and layout

Asynchronous designs may require hand instantiation and extensive simulation to verify Isolate asynchronous logic into separately compiled blocks

4-7


The Big Picture, Think RTL!

RTL = Register Transfer Level Writing in an RTL coding style

means describing the register architecture, the circuit topology, and the functionality between

registers Design Compiler optimizes logic

between registers It does not optimize the register

placement

4-8


RTL Synthesis Cookbook

HDL

The three big picture guidelines

Coding cookbook

4-9


Synthesis of if Statements

Synthesis of loop statements

Synthesis of Flip-Flops

Synthesis of case statements

Synthesis of if statements

Synthesis of arithmetic circuits

4-10


if (Aflag = '1') thenOutData

4-11


if (Aflag == 1b1)begin

Op1

4-12


LS373: process (ALE, ADBUS)begin

if (ALE = 1) thenABUS

4-13


int0int1int2int3

active[0]active[1]active[2]active[3]

if-then-elseif Statements

Since VHDL and Verilog if-elseif statements imply priority, they should only be used if priority checking is a circuit requirement Otherwise, priority control logic will be synthesized Result will be more, and possibly slower logic

Example: Priority Interrupt Controller

One or more of four (input) interrupt lines (int0..int3) may be asserted

Only one output should be asserted int0 has the highest priority

4-14


if-then-elseif Statements (cont)

module test(active,int0,int1,int2,int3);input int0,int1,int2,int3;output [3:0] active;reg int0,int1,int2,int3;reg [3:0] active;

always@(int0 or int1 or int2 or int3) beginactive[3:0]

4-15


Priority Interrupt Circuit: Synthesis Results

Priority Logic

int0 active[0]

active[1]

active[2]

active[3]

int1

int2

int3

4-16


When NOT to Use if-then-elseif

When signals have equal priority When signals are mutually exclusive

4-17


Synthesis of case Statements



Synthesis of loop Statements


Synthesis of Arithmetic Circuits

4-18


case Statements

case statements in Verilog case statements in VHDL

4-19


case Statements

Case statements imply parallel mux function.

always@(SEL or A or B or C or D)begin

case (SEL)2b00 : OUTC = A;2b01 : OUTC = B;2b10 : OUTC = C;default : OUTC = D;

endcaseend

process (SEL,A,B,C,D) begincase SEL is

when 00 => OUTC OUTC OUTC OUTC

4-20


Interrupt Vector Address Generator

Build a logic that takes the signals of the priority interrupt circuit and generates a 16-bit memory address that is unique for each interrupt.

active[0]active[1]active[2]active[3]

vec[15:0]

interrupt address to be generated

active[0] 0000000000 00000100b (0004h)active[1] 0000000000 00000110b (0006h)active[2] 0000000000 00001000b (0008h)active[3] 0000000000 00001010b (000Ah)

Each of the above memory locations contain the starting address of an interrupt handling routine, which is read by the processor at anappropriate time after a valid interrupt is recognized.

4-21


always @(active[3] or active[2] or active[1] or active[0])begin

case ({active[3], active[2], active[1], active[0]})4b1000 : temp = 3b010;4b0100 : temp = 3b011;4b0010 : temp = 3b100;4b0001 : temp = 3b101;4b0000 : temp = 3b000;default : temp = 3bxxx;

endcaseendalways vec[15:4] = 12h000;always vec[0] = 0;always @(posedge clk) vec[3:1] = temp;

Address Generator: Verilog

What happens if you do not include the default clause?

4-22


Schematic of Address Generator

D Q

CLK

D Q

CLK

D Q

CLK

vec[0]

vec[1]

vec[2]

vec[3]

vec[15:4] vec[15:0]

gnd

active[2]

active[3]

active[0]

active[1]

clk

A schematic after compiling the source code of the Interrupt Vector Address Generator.

Without the default clause, the case statement would not be fully specified and infer latches.Can be controlled by compiler directives.

4-23


Compiler Directive full_case


case ({active[3], active[2], active[1], active[0]})//synopsys full_case

4b1000 : temp = 3b010;4b0100 : temp = 3b011;4b0010 : temp = 3b100;4b0001 : temp = 3b101;4b0000 : temp = 3b000;


4-24


Compiler Directive parallel_case


temp = 3b000;case (1b1) //synopsys parallel_case

active[3] : temp = 3b010;active[2] : temp = 3b011;active[1] : temp = 3b100;active[0] : temp = 3b101;


4-25








4-26


Unrolling Loops

In synthesis, for loops are unrolled during translation, and then synthesized

out(0)

4-27


Tradeoffs with Loops

always@(data)begin

sum = 0;/* Count the number of 1s */for (i = 0; i < 8; i = i + 1)

sum = sum + data[i];

/* Check if even or odd number */odd_parity = sum[0];

end;

process (data)variable sum : integer;

beginsum := 0;

-- Count the 1sfor i in 0 to 7 loop

sum := data(i) + sum;end loop;

--check parityodd_parity

4-28


Hardware Result

...2

Data(0)+

Data(1)/

+Data(2)

/2

+Data(7)

+Data(6)

/3

How could this be recoded?

4-29


Recoded Loop

always@ (data)begin

odd_parity = ^data;end

binary XOR

Verilog

VHDL

optimized design

process (data)variable odd_parity : bit;begin

odd_parity

4-30








4-31


Inferring Sequential Devices

Registering a signal means clocking it into a Flip-Flop For DC to infer Flip-Flops, your code must imply signal

assignments that take place in response to the edge of another signal

DC requires specific coding templates to infer registers

How do you:AB

CLK

RSTn

D Q+ S1assign A+B to S1

With an asynchronous reset?

in response to a rising edgeon CLK ?

4-32


Flip-Flop: Example

always@(posedge CLK or negedge RSTn)begin

if (! RSTn)S1

4-33


Latch

Latch w/

Async

Latch w/DualAsync

DFFw/

Async

DFFw/DualAsyncDFF

MuxedDFF JKFF

MSLatch

Latch w/Sync

Clr

DFFw/Sync

Cntl.

The registers in your final circuit depend on: Coding style (including attributes and directives) Types of registers available in the target_library

(V)HDL Compiler generates an inference report

Example: Inference Report for an AR Flip-Flop

Register Name Type Width Bus MB AR AS SR SS ST

Q_reg Flip-Flop 1 - - Y N N N N

Inferring Sequential Devices

Design Compiler can synthesize hardware using a wide variety of flip-flops and latches

4-34








4-35


Inferring Arithmetic Parts

process (A, B, C, D, addr)begin

if (addr = 12) thenResult

4-36


Technology Library

link_library,target_library

DesignWare Library

synthetic_library

AND Gates,OR Gates,Flip-Flops...

Adders,Multipliers,

Comparators...

if (A1 >= A2)Y

4-37


DesignWare Implementation Selection

Multiple architectures for each macro allow DC to evaluate speed/area tradeoffs and choose the best implementation

HDLOperator

+

smallest

fastest

Carry Look-Forward

Carry Look-Ahead

Ripple Carry

Z

4-38


synthetic_library = {dw_foundation.sldb}

Enabling Faster DW Implementations

DesignWare components come from synthetic libraries

Synopsys-provided synthetic library files reside in directory $SYNOPSYS/libraries/syn

The synthetic_library variable points to a list of synthetic library database (.sldb) files:

link_library = link_library + synthetic_library

4-39


SUM

4-40


Implying a Structure by Operand Placement (cont)

Change the order, or use parentheses to force a different topology:

+

SUM

EF

*

+ +CD

+G

*AB

Max Delay = Multiplier + 2 adders

SUM

4-41


Verilog Preprocessor Directive

module IFDEF(out,a,b,clk);output out;input clk,a,b;reg out;

always@(posedge clk)beginifdef SYN

out=b && a;else SYN

$display (The output is: );out=b && a;

endifendendmodule

set hdlin_enable_vpp trueanalyze -f verilog -d SYN IFDEF.velaborate IFDEF -lib WORK

4-42


Documentation

Synopsys On-Line Documentation

HDL Compiler for Verilog Reference Manual VHDL Compiler Reference Manual Guide to HDL Coding Styles for Synthesis

Nonblocking Assignments in Verilog Synthesis,Coding Styles That Kill!www.synopsys.com -> SNUG -> SNUG Papers -> 2000 San Jose

full_case parallel_case, the Evil Twins of Verilog Synthesiswww.synopsys.com -> SNUG -> SNUG Papers -> 1999 Boston

4-43


Lab 4: Introduction

LAB

Examine Coding Style Issues

Area

Path Value

LOOP_BAD LOOP_GOOD

IF_BAD IF_GOOD

LOOP_BEST

IF_BEST

compare_design IF_BAD IF_GOOD

60 min

4-44


Appendix

Inference and Instantiation

4-45


Verilog Inference and Instantiation

always @(A or B) begin :b1/* synopsys resource r0:map_to_module = "DW02_mult",implementation = "wall",ops = "a1"; */PROD

4-46


VHDL Inference and Instantiation

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

inside the architecture block:PROD

5-1

Timing and AreaChip Synthesis Workshop Synopsys 31833-000-S16

Agenda: Day 2

DAY2222

Timing and Area5

Topic LabUnit

Environmental Attributes6

Time and Load Budgeting7

Timing Analysis8

DC Tcl - Introduction9

5-2


Unit Objectives

After completing this unit, you should be able to:

Constrain a design for area

Constrain a design for timing

5-3


RTL Block Synthesis

SimulateOK?

Yes

Rewrite

Yes

No

MajorViolations?

No

Yes

No

Write RTLHDL Code

SynthesizeHDL CodeTo Gates

Met Constraints?Analysis

Constraints & AttributesArea & Timing Goals

5-4


dc_shell-t> current_design PRGRM_CNT_TOPdc_shell-t> set_max_area 100

dc_shell-t> current_design PRGRM_CNT_TOPdc_shell-t> set_max_area 100

Specifying an Area Goal

Units are those of target library, defined by the vendor

2-input-NAND-gate transistors square mils

5-5


Timing Goals: Synchronous Designs

Synchronous Designs: Data arrives from a clocked device Data goes to a clocked device

Objective: Define the timing constraints for all paths within a design: all input logic paths the internal (register to register) paths, and all output paths

5-6


Timing Goals: Synchronous Designs (cont)

D Q

QB

D Q

QB

D Q

QB

D Q

QB

Clk

TO_BE_SYNTHESIZED

FF1 FF2 FF3 FF4M N X S T

Example:

Clock Period = 10ns Setup = 1ns

What information must you provide to constrain all the register-to-register paths in your design?

Does the duty cycle of your clock matter?

What is the max delay requirements for the register-to-register paths in the block TO_BE_SYNTHESIZED?

5-7


Defining a Clock

User MUST Define: Clock Source (port or pin) Clock Period

Period

ClkN X SD Q D Q

TO_BE_SYNTHESIZED

FF2 FF3

User may also define: Duty Cycle Offset/Skew Clock Name

Clk

1 Clock Cycle

5-8

Timing and AreaChip Synthesis Workshop Synopsys 31833-

chip synthesis workshop 1392

Documents

synthesis review

synthesis unit objectives

chip synthesis process

module synthesis roadmap

workshop prerequisites

workshop agenda

design compiler interfaces

workshop target audience