chip and system-level integration technologies for silicon

© 2017 IBM Corporation

IBM Research - Zurich

Chip and system-level integration technologies

for silicon photonics

Bert Jan Offrein

5th International Symposium for Optical Interconnect in Data Centres



2

Outline

• The need for integration at component and system level

– CMOS silicon photonics with embedded III-V materials

– High channel count silicon photonics packaging

• Summary



Communication between two processors

3

• 1000 x Larger bandwidth

• 1000 x Lower loss

• 100 x Larger distance

Optical communication:

Optical communication requires many more components and assembly steps !!!

Scalability &

Power efficiency !!!

V

laser

drivermodulator

amplifierV

Electrical

Optical



Photonics technologies for system-level integration

System-level: Scalable chip-to-fiber connectivity

Chip-level: CMOS silicon photonics + Active photonics devices

Si photonics provides all required buliding blocks (except lasers) on chip-level:

- Modulators

- Drivers

- Detectors

- Amplifiers

- WDM filters

+ CMOS electronics

2

1

One step mating of numerous optical interfaces

Provide electrical and optical signal routing capability

Enable a simultaneous interfacing of electrical and optical connections



CMOS Embedded III-V on silicon technology

6

CMOS Si Photonics … + III-V functionality

Si wafer

SiO2

Si

FE

OL

Front-end

BE

OL

SiO2

Electrical

contacts

III-V

Ultra-thin III-V layer stack (300 nm) enables embedding in between FEOL and BEOL

Integration of III-V functionality in the CMOS processing flow

Power efficient lasers for silicon photonics by high modal overlap concept

Flexible design, on-chip control and cost-effective source integration


IBM Research - Zurich Challenges for III-V laser integration in CMOS

Current confinement

1E-7

1E-6

1E-5

1E-4

IBM

Au-free

v2

Without Au

With Au

Conta

ct re

sis

tvity (c

m2)

Doping Level

T

IBM

Au-free

v1

CMOS-compatible Ohmic contacts

on n and p-InP

Si waveguideIII-V mesa

III-V to silicon optical coupler

Adiabatic taper – top view

Silicon photonics Oxide cladding + CMP

Bonding of III-V epi waferIII-V pattering + BEOL

Optimized process flow



Processing scheme

8

SiPh wafer

Wafer bonding

SiO2

SiO2

SiO2

SiPh wafer

III-V epi layer

III-V structuring

Metallization

SiO2

epi

layer

Substrate removal

SiO2

5 InAlGaAs quantum wells

(MOCVD)

MQW section

Feedback grating



Optically pumped ring laser

9

Measured FSR: 0.194 nm

Estimated FSR from ring: 0.203 nm

Estimated FSR from III-V: 0.266 nm

Gain section

Directional coupler

Lasing with feedback from silicon photonics

output



Electrically pumped LED

10

LED test-device for process optimization

Good V-I characteristic

Electro-luminescence emission visible with

IR-camera

p-InGaAs/p-InP

n-InP

InAlGaAs

Cross-section SEM

Electrical probe

S G

IR camera photograph

DuT0 2000 4000 6000 8000 10000 12000 14000 16000

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Voltage (

V)

Current density (A/cm2)

V-I measurement



Electrically pumped lasers

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Laser devices: 10 dB optical loss at room temperature

Cooling down increases gain

Increased gain can overcome loss

Pulsed electrical pumping

1160 1180 1200 1220 1240 1260

0

1000

2000

3000

4000

5000

Co

unts

(a

.u.)

Wavelength (nm)

Optical spectrum at 100 K

Spontaneous emission

Lasing modes

Work in progress !



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Integration: SiPh optical interconnect (8x16) with 16nm CMOS switching ASIC

Scaling chip I/O towards Pb/s

Silicon photonics (single-mode) Increased reach

Reducing network layers: less latency, more servers & memory more throughput

High level of integration: Need on-chip lasers

H2020 EU project L3MATRIX



H2020 EU project DIMENSION

13



Photonics technologies for system-level integration

System-level: Scalable chip-to-fiber connectivity

Chip-level: CMOS silicon photonics + Active photonics devices

Si photonics provides all required buliding blocks (except lasers) on chip-level:

- Modulators

- Drivers

- Detectors

- Amplifiers

- WDM filters

+ CMOS electronics

2

1

One step mating of numerous optical interfaces

Provide electrical and optical signal routing capability

Enable a simultaneous interfacing of electrical and optical connections



Adiabatic optical coupling using polymer waveguides

Principle:

– Contact between the silicon waveguide taper and the polymer waveguide (PWG),

achieved by flip-chip bonding, enables adiabatic optical coupling

15

Schematic view of Si- photonics chip assembled

by flip-chip bonding

• Compatible with established electrical assembly

• Simultaneous E/O interfacing

• Scalable to many optical channels

- J. Shu, et al. "Efficient coupler between chip-level and board-level optical waveguides." Optics letters 36.18 (2011): 3614-3616.

- I. M. Soganci, et al. "Flip-chip optical couplers with scalable I/O count for silicon photonics." Optics express 21.13 (2013): 16075-16085.

- T. Barwicz, et al. "Low-cost interfacing of fibers to nanophotonic waveguides: design for fabrication and assembly tolerances.“, Photonics Journal, IEEE

6.4 (2014): 1-18.



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Single-mode polymer waveguide technology

SM polymer waveguides on

wafer-size flexible substrates

SM

wa

ve

gu

ide

50 mm

SM polymer waveguides on panel-size flexible substratesSM polymer waveguides on

chips (e.g. Si photonics chips)

Ch

ip-s

ize

Wafe

r-s

ize

Pan

el-

siz

e

R. Dangel, et al. Optics Express, 2015



Insertion loss characterization (1)

17

Schematic view of Si-

photonics chip assembled

by flip-chip bonding

1260 1280 1300 1320 1340 1360 13800

1

2

3

4

5

IL/facet (d

B)

Wavelength (nm)

TE, LC = 1.5 mm

TM, LC = 1.5 mm

Insertion loss measurement:

• Wavelength sweep over O-band

– Full path vs ref. PWG path

• Wavelength dependency mainly in the PWG

1260 1280 1300 1320 1340 1360 13800

1

2

3

4

5

IL/2

of re

fere

nce P

WG

(dB

)

Wavelength (nm)

TE, LPWG

= 3.0 cm

TM, LPWG

= 3.0 cm



Adiabatic coupler loss characterization

Coupler loss measurement:

• Direct-process vs Flip-chip bonding approach

• For Lc ≥ 1.0 mm: Coupler loss < 1.5 dB, PDL ≤ 0.7 dB

• Operating in the O and C-band

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Polymer waveguides attached by flip-chip bondingPolymer waveguides processed on chip



H2020 EU project ICT-STREAMS

19



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From Si photonics transceivers to chip-level assembly

Silicon photonics co-packaging with the ASIC chip

– Less components and assembly steps

– Improved electrical signal path, reduce # interfaces and length

– High density, scalable optical IO

– Minimum overhead, lowest cost

Today Next integration step

Ultra-short electrical line. Overcome CDR and FEC

50% reduction of total link power anticipated



Summary

• Miniaturized Photonic Packaging

– Chip level integration

• CMOS+Passive+Active photonics

– System-level integration

• Adiabatic optical coupling as a scalable, efficient, broadband and

polarization independent fiber-to-chip interfacing solution

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Path towards high level of electro-optical integration & scalability



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Acknowledgements

• Collaborators in IBM

– Marc Seifried, Herwig Hahn, Gustavo Villares, Lukas Czornomaz, Folkert Horst, Daniele Caimi, Charles Caer,

Yannick Baumgartner Daniel Jubin, Norbert Meier, Roger Dangel, Antonio La Porta, Jonas Weiss, Jean

Fompeyrine, Ute Drechsler

– And many others

• Co-funded by the European Union Horizon 2020 Programme and the Swiss National Secretariat for Education,

Research and Innovation (SERI)

• The opinion expressed and arguments employed herein do not necessarily reflect the official views of the Swiss

Government.

Agreement No 688172

Agreement No 688003

Agreement No 688544

Agreement No 688572

Contract No 15.0313

Contract No 15.0339

Contract No 15.0346

Contract No 15.0309



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Thank you for your attention

• Bert Jan Offrein

• [email protected]

chip and system-level integration technologies for silicon

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