CHARACTERIZATION OF PLANAR AND VERTICAL N-CHANNEL MOSFET

IN NANOMETER REGIME

IMA BINTI SULAIMAN

A project report submitted in partial fulfillment of the

requirements for the award of the degree of

Master of Engineering (Electrical – Electronics and Telecommunications)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

MAY 2007

iii

“To my beloved family and friends, thanks for being there, throughout this journey”

iv

ACKNOWLEDGEMENT

In the name of Allah, Most Merciful, Most Compassionate. It is by God’s

willing, I was able to complete this project within the time given. This project would

not have been possible without the support of many people. Firstly, I would like to

take this opportunity to thank my supervisor, Associate Professor Dr. Razali bin

Ismail for his guidance, patience and support for me throughout the period of time in

doing this project. My deepest gratitude also goes out to my examiners, Dr. Abu

Khari A’ain and Dr Abdul Manaf for their constructive comments and suggestions in

evaluating my project.

A very special thanks to my family and all my friends for always being there

for me and giving their love and support when I most needed it. Lastly I would like

to thank all staff and lecturers of Faculty of Electrical Engineering, Universiti

Teknologi Malaysia for their help and support.

v

ABSTRACT

In recent years, there is more and more design on MOSFET that has been

developed to fulfill the market need. This project focused on the comparison of

planar and vertical n-channel MOS transistor characteristic with effective channel

length of 100nm down to 50nm. Planar and vertical n-channel MOS transistors with

effective channel length ranged from 50nm to 100nm has been developed.

Simulation of the device design is done by using Silvaco-DevEdit. Short channel

effect (SCE) is investigated through out the device simulation. SCEs affect on

device and circuit performance in off-state leakage current and VT roll-off. At the

device simulation process, using Silvaco Atlas, the electrical parameter is extracted

to investigate the device characteristic. Several design analysis are performed to

investigate the effectiveness and robustness of the method in order to prevent the

varying threshold voltage or short channel effect of a MOSFET device. A single

channel vertical NMOS shows better VT roll-off and better subthreshold swing at

~85mV/decade. On the other hand, planar NMOS has lower threshold voltage value

which is suitable for low voltage devices. With these advantages from each NMOS

analysis, one can decide which device to use to achieve required specification for

specific usage in future.

vi

ABSTRAK

Satu kajian telah dijalankan untuk membandingkan ciri-ciri antara MOSFET

saluran-n jenis mendatar dan menegak. Setiap peranti mempunyai saluran efektif

sepanjang 50nm hingga 100nm telah dibangunkan. Peranti telah direka

menggunakan Slvaco-DevEdit. Kesan kurang sempurna dalam rekaan MOSFET

seperti kesan saluran pendek telah dikaji. Kesan yang berlaku adalah seperti arus

bocor dan kejatuhan voltan ambang. Pada simulasi peranti, menggunakan Silvaco-

Atlas, parameter elektrikal telah diekstrak untuk megkaji ciri-ciri peranti. Beberapa

analisa peranti dilakukan untuk menyiasat keberkesanan kaedah yang telah

digunakan dalam mengurangkan perubahan voltan ambang atau kesan saluran

pendek bagi sesebuah MOSFET. NMOS menegak bersaluran tunggal

memperlihatkan kejatuhan voltan ambang yang lebih baik dan ayunan sub-ambang

dalam lingkungan 85mV/dekad. Manakala, NMOS mendatar memiliki voltan

ambang yang lebih rendah yang bersesuaian dengan peranti bervoltan rendah.

vii

TABLE OF CONTENT

CHAPTER TITLE PAGE

TITLE i

DECLARATION ii

DEDICATION iii

ACKNOWLEDGEMENT iv

ABSTRACT v

ABSTRAK vi

TABLE OF CONTENT vii

LIST OF TABLES x

LIST OF FIGURES xi

LIST OF ABBREVIATION xiv

LIST OF APPENDICES xv

1 INTRODUCTION 1

1.1 Introduction 1

1.2 Objectives 4

1.3 Scope of Project 4

1.4 Project Plan 5

1.5 Organization of the Report 6

2 LITERATURE REVIEW 7

2.1 Introduction 7

viii

2.2 Planar MOSFET 8

2.2.1 Works on planar MOSFET 9

2.3 Vertical MOSFET 13

2.3.1 Vertical MOSFETs based on selective

epitaxy

15

2.3.2 Vertical MOSFETs with etched sidewalls 17

2.3.3 Works on vertical MOSFET 18

2.4 Characteristics of an NMOS transistor 22

2.5 Short channel effects 23

2.6 MOS device physics in short-channel regime 23

2.7 Threshold voltage 26

2.7.1 Threshold reduction 27

2.8 Leakage current 28

2.9 Subthreshold characteristic 30

2.10 VT roll-off 32

2.11 Summary 33

3 METHODOLOGY 34

3.1 Process simulation 34

3.2 Process development 36

3.2.1 Work area 36

3.2.2 Adding silicon base region 37

3.2.3 Creating gate oxide 39

3.2.4 Adding contacts for source/drain 41

3.2.5 Adding substrate contact 42

3.2.6 Polysilicon gate formation 43

3.2.7 Source/drain doping 45

3.2.8 Creating mesh 49

3.2.9 Final device 51

3.3 Device simulation 54

3.3.1 Output characteristic 55

3.3.3 Transfer characteristic 56

ix

3.4 Summary 56

4 EXPERIMENTAL RESULTS AND ANALYSIS 57

4.1 Results 57

4.1.1 Output characteristic 57

4.1.2 Transfer characteristic 59

4.1.3 Threshold voltage 60

4.1.4 Leakage current 61

4.1.5 Subthreshold slope 62

4.1.6 Drain saturation slope 63

4.2 Analysis 64

4.2.1 Varied gate oxide thickness 64

4.2.1.1 Threshold voltage 64

4.2.1.2 Subthreshold slope 65

4.2.1.3 Leakage current 66

4.2.1.4 Conclusion 67

4.2.2 Varied body doping concentration 68

4.2.2.1 Threshold voltage 68

4.2.2.2 Subthreshold slope 69

4.2.2.3 Leakage current 70

4.2.2.4 Conclusion 71

4.3 Summary 72

5 CONCLUSION AND FUTURE WORK 73

5.1 Conclusion 73

5.2 Suggestion for Future Works 74

REFERENCES 75

APPENDICES 78

x

LIST OF TABLES

TABLE NO TITLE PAGE

3.1 Summary of NMOS process flow 35

xi

LIST OF FIGURES

FIGURE NO TITLE PAGE

1.1 Moore’s Law on increasing performance 3

1.2 Moore’s Law on decreasing cost 3

2.1 Cross section of a planar NMOS. 8

2.2 Simulation structure of the symmetrical MOSFET

with design parameters

9

2.3 Simulation structure for the asymmetric MOSFET 10

2.4 Schematic images of the device-design concepts for

the lateral S/D-junction control techniques. (a)

Conventional. (b) Thick offset spacer. (c) Notch,

offset spacer and reverse S/D

11

2.5 Schematic device cross section in the simulations: (a)

the asymmetric Schottky barrier MOSFET (ASB

structure); (b) the conventional Schottky Barrier

MOSFET (CSB structure)

12

2.6 Vertical MOSFET 13

2.7 Schematic cross section of VFET 15

2.8 Schematic cross section of VOXFET 16

2.9 Cross-section showing the concept of dielectric pocket

in a vertical MOSFET

17

2.10 Schematic cross sections of vertical nMOSFETs (a)

with deep drain junction and (b) with shallow drain

junction.

18

2.11 Structure of bVMOS 19

xii

2.12 Schematic cross section of a surround-gate vertical

MOSFET fabricated with the FILOX process

21

2.13 Transfer characteristic of an NMOS transistor 22

2.14 Drain current family of characteristic of an NMOS

transistor

22

2.15 Depletion region of an NMOS 27

2.16 Sources of current leakage in an n-channel MOSFET 29

2.17 (a) ID-VG curve and (b) inverse ID-VG that shows

subthreshold slope, S

31

3.1 Flow of process simulation 35

3.2 Work area’s depth and length values for (a) planar

NMOS and (b) vertical NMOS

36

3.3 Workspace for planar NMOS 37

3.4 Silicon region for (a) planar NMOS and (b) vertical

NMOS

38

3.5 Base impurity, boron, added to the silicon 39

3.6 SiO2 layer for (a) planar NMOS and (b) vertical

NMOS

40

3.7 Contacts for (a) planar NMOS and (b) vertical NMOS 41-42

3.8 Substrate electrode panel 43

3.9 Polysilicon gate region for (a) planar NMOS and (b)

vertical NMOS

44

3.10 Adding impurities to gate to create highly doped

region

45

3.11 Impurity added to create source for (a) planar NMOS

and (b) vertical NMOS

46

3.12 Impurity specification to create drain for (a) planar

NMOS and (b) vertical NMOS

47

3.13 Net doping for (a) planar NMOS and (b) vertical

NMOS

48

3.14 (a) Mesh parameters and (b) refinement on mesh for

planar and vertical NMOS

49

3.15 Mesh on (a) planar NMOS and (b) vertical NMOS 50

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3.16 Completed planar NMOS 51

3.17 Completed (a) single channel vertical NMOS and (b)

full vertical NMOS

52

3.18 (a) Planar NMOS and (b) vertical NMOS with

effective channel length of 100nm

53

4.1 ID-VDS curve for planar and single channel vertical

NMOS

58

4.2 ID-VGS curve for planar and single channel vertical

NMOS

59

4.3 Threshold voltage for planar and single channel

vertical NMOS

60

4.4 Leakage current for planar and single channel vertical

NMOS

61

4.5 Subthreshold slope for planar and single channel

vertical NMOS

62

4.6 Drain saturation slope for planar and single channel

vertical NMOS

63

4.7 Threshold voltage with varied gate oxide thickness for

planar and vertical NMOS

65

4.8 Subthreshold slope with varied gate oxide thickness

for planar and vertical NMOS

66

4.9 Leakage current with varied gate oxide thickness for

planar and vertical NMOS

67

4.10 Threshold voltage with varied body doping

concentration for planar and vertical NMOS

69

4.11 Subthreshold slope with varied body doping

concentration for planar and vertical NMOS

70

4.12 Leakage current with varied body doping

concentration for planar and vertical NMOS

71

xiv

LIST OF ABBREVIATION

ASB - Asymmetric Schottky barrier source/drain MOSFET

BTBT - Band-to-band tunneling

bVMOS - Vertical MOSFET with internal block layer

CMOS - Complementary MOS

CSB - Conventional Schottky Barrier MOSFET

DIBL - Drain induced barrier lowering

DITM - Drain-induced tunneling modulation

DOT - Drain on top

DT - Direct-tunneling

FILOX - Fillet local oxidation

GIDL - Gate-induced drain leakage

MOSFET - Metal-oxide semiconductor filed effect transistor

NMOS - N-channel MOSFET

PECVD - Plasma-enhanced chemical vapor deposition

PMOS - P-channel MOSFET

SCE - Short channel effect

SEG - Selective epitaxial growth

SOI - Silicon on insulator

SOT - Source on top

xv

LIST OF APPENDICES

APPENDIX TITLE PAGE

A Family of ID-VDS curve program 78

B ID-VGS at VDS=0.1V program 80

C Extract results from simulation 82

CHAPTER 1

INTRODUCTION

This project uses Silvaco DevEdit and Atlas as a primary fabrication process

and simulation tool. First part of the report will elaborate more on the project

background and fabrication process will be discussed regarding the development of

planar and vertical n-channel MOSFET. This chapter also mention on the objective

and scope of the project.

1.1 Introduction

Future high performance devices for higher speed and lower power

consumption would require active device dimensions in the sub-100 nm regime.

Chip complexity, chip performance, feature size, and the numbers of transistors

produced each year are a few of the parameters of the semiconductor industry that

have changed exponentially over the last 50 years. The size reduction is in great

improvement to MOSFET operation until the late 1990s with no deleterious

consequences. The difficulties with decreasing the size of the MOSFET have always

2

been associated with the semiconductor device fabrication process. A steady path of

constantly shrinking device geometries and increasing chip size has been followed by

the integrated circuit industry for more than 30 years. This strategy has been driven

by the increased performance that the smaller devices make possible and the

increased functionality that larger chips provide.

Moore, one of the founders of Intel, observed in an article in the April 19,

1965 issue of Electronics magazine that innovations in technology would allow a

doubling of the number of transistors in a given space every year (in an update article

in 1975, Moore adjusted the rate to every two years to account for the growing

complexity of chips), and that the speed of those transistors would increase. What is

less well-known is that Moore also stated that manufacturing costs would

dramatically drop as the technology advanced. Moore's prediction, now popularly

known as Moore's Law, had some startling implications, predicting that computing

technology would increase in value at the same time it would actually decrease in

cost. This was an unusual idea at the time since, in a typical industry, building a

faster, better widget with twice the functionality also usually means doubling the

widget’s cost. However, in the case of solid-state electronics, the opposite is true:

Each time transistor size shrinks, integrated circuits (ICs) become cheaper and

perform better.

There are two main reasons that smaller MOSFETs are desirable in today’s

world. First, smaller MOSFETs allow more current to pass and second, it has

smaller gates, thus lower capacitance. These two factors bring to lower switching

times and higher processing speeds. Logic gates incorporating smaller MOSFETs

have less charge to move as smaller MOSFETs have lower gate capacitance and the

amount of charge on a gate is proportional to its capacitance. There is another reason

for scaled down MOSFETs, which is smaller MOSFETS can be packed more

densely, resulting smaller chips and chips with more computing power in an area.

3

Figure1.1: Moore’s Law on increasing performance

Figure 1.2: Moore’s Law on decreasing cost

4

1.2 Objectives

The main objective of the project is to develop a planar and vertical n-channel

MOSFET (NMOS) with a range of effective channel length of 100nm down to 50

nm. Many design aspects has to be considered when the MOSFET device is scaled

down into deep submicron regime. Short channel effects will appear whenever the

MOSFET device is scaled down and gate oxide has to be thin enough to increase the

device performance.

The objectives of the study are listed as follows:

1. To develop planar and vertical n-channel MOSFET using TCAD.

2. To study the characteristic and to compare the performance between

planar and vertical MOSFET.

3. To analyze planar and vertical NMOS in nanometer regime

1.3 Scope of Project

Basic design structure has been implemented in designing the device in this

project. Generally, this project consists of two parts, which are the fabrication and

the simulation process.

1) Process simulation

The process used to fabricate the planar and vertical NMOS transistor will be

simulated using Silvaco-DevEdit. It is used to create the device structure, adding

dopant, defining electrodes and creating the mesh. It uses an advanced mesh

75

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