chapter 7state machines 1. one hot state machine

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CHAPTER 7 State Machines

How do things work without a CPU?• State Machines

also called Synchronous Sequential Circuits• Flip-Flops (Registers) all are edge triggered

with the same clock signal• Step-by-step execution

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1. One Hot State MachineExample with 3 states• Each state has its own flip-flop• Only a single “1” state at a time

clock

D Q D Q

CLK CLK

D Q

CLK

Y0 Y1 Y2

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Example One Hot State Machine

init (Y0=1, Y1=0, Y2=0)

1 0

clock

D Q D QCLK CLK

Y0 Y1 Y2

0D QCLK

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step

0 1

clock

D Q D QCLK CLK

Y0 Y1 Y2

0D QCLK

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step – step

0 0

clock

D Q D QCLK CLK

Y0 Y1 Y2

1D QCLK

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step – step – step …

1 0

clock

D Q D QCLK CLK

Y0 Y1 Y2

0D QCLK

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Timing Diagram for One Hot State Machine

State machine with 3 states, init (Y0=1, Y1=0, Y2=0)

clock

Y0

Y1

Y2

t

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Inversion Trick: All Flip-Flops initialized to 0

0 0

clock

D Q D QCLK CLK

Y0 Y1 Y2

0D QQ’ Q’ Q’

CLK

Difficult to initialize to “100” instead of “000”!

0 0 01 1 01 0 10 0 0

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Applications for State Machines

• Counters

• Code sequence detectors

• Sequential code generators

• Multi-input system controllers, etc…

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2. Counters

• Sequential circuit, which cycles through a prescribed number of states, triggered by input pulses from clock or other source.

• For every pulse one or more outputs change. After a sequence of N pulses, the sequence repeats.

• May use binary count or other sequence

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Binary Counter (2 bit) - Asynchronous

D Q

CLK

D Q

CLK

Y1 Y0

clock

Not a state machine!

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Init: 00Sequence:00 ® 01 ® 10 ® 11 ® 00

D Q

CLK

D Q

CLK

Y1 Y0

Binary Counter (2 bit) - Synchronous

clock

Task

? ?

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Init: 00Sequence:00 ® 01 ® 10 ® 11 ® 00

Synchronous Counter

Task

D QCLK

D QCLK

Y1 Y0clock

? ?

Present State Next StateQ1 Q0 D1 D00 00 11 01 1

0 11 01 10 0

D0 = Q0’D1 = Q1 XOR Q0

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Init: 00Sequence:00 ® 01 ® 10 ® 11 ® 00

D Q

CLK

D Q

CLK

Y1 Y0

Binary Counter (2 bit) - Synchronous

clock

Task

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Binary Counter (n bit) - Synchronous

D Q

CLK

D Q

CLK

D Q

CLK

Henable

Y2 Y1 Y0

c0c1c2

Init: 000Seq.: 000 ® 001 ® 010 ® 011 ® 100 ® 101 ® 110 ® 111 ®

clock

H H

Task

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Counter Example – Don’t careNot all counters count from 0 … 2n–1E.g. counter from 0 (000) to 5 (101)

ØWhat about unused states 6 and 7 ?ØDon’t care “*”. This will help to minimize the circuit later.

Present State Next State Q2 Q1 Q0 Q2 Q1 Q0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 * * * 1 1 1 * * *

001

010

011

100

101

000

Source: Boussaid

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Counter Example – Do care!

Present State Next State Q2 Q1 Q0 Q2 Q1 Q0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0

001

010

011

100

101

000

111110

• Safer to make unused states lead into starting state.• Guaranteed to enter a valid state if somehow enters an unused state.• Called self-starting counter.

Source: Boussaid Bräunl 2021 18

3. State Machine ExampleHow does a soda-vending machine operate ?Input• 5 buttons for beverage selection• 5 sensors for beverage availability• 6 coin detection for $0.10, $0.20 $0.50, $1.00, $2.00, invalid• 1 button for cancelTotal: 17

Output• 5 LEDs for indicating fill status• 1 coin return solenoid• 1 coin-to-cash-register solenoid• 5 beverage dispense motorsTotal: 12

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Vending Machine

Make it simpler for now:

Input• 1 button for beverage selection• 1 sensor for beverage availability• 2 coin detectors for $0.50, $1.00Total: 4

Output• 1 beverage dispense motors• 1 output LED for beverage availabiltyTotal: 2

Let�s assume thisnever happens…

– 3

– 1

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Vending MachineDefine: States, Transitions, inputs and outputs

Start

paid$0.50

Press beverage button$0.50

half-paid Press beverage button

Press beverage button- dispenses bottle- moves coins to cash register

$1

$1

$0.50$1

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Vending MachineConsistency:• Label states using binary numbers, e.g.:

Start = 00, half-paid = 01, paid = 10 (11 is unused)

• Specify what should happen for every input at every state!Note: only one input can happen at any time

beverage button

xx

$1 coin $0.50 coin

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Vending MachineTransition table:

old state input new state outputQ1 Q0 D1 D0 dispense0 0 50c 0 1 00 0 $1 1 0 00 0 button 0 0 00 1 50c 1 0 00 1 $1 1 0 00 1 button 0 1 01 0 50c 1 0 01 0 $1 1 0 01 0 button 0 0 1

D1 D0 dispense50c$1button50c$1button50c$1button

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Vending MachineFind Terms for new state D1, D0 and dispense:


For new state and outputs:1.Find all �1� entries2.AND (•) old states and inputs3.OR (+) all terms4.Minimize

Q1� • Q0� • 50cQ1� • Q0 • button

For D0:

Complete:D0 = Q1� • Q0� • 50c

+ Q1� • Q0 • button

Minimize:D0 = Q1� • (Q0� • 50c

+ Q0 • button)Bräunl 2021 24

Vending MachineFind Terms for new state D1, D0 and dispense:

For new state and outputs:1.Find all �1� entries2.AND (•) all inputs for this line3.OR (+) all terms4.Minimize

D1 = Q1� • Q0� • $1+ (Q1+Q0) • (50c+$1)

D0 = Q1� • (Q0� • 50c+ Q0 • button)

disp = Q1 • button


D0gates

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Vending MachineBuild Hardware (clock = 50c+$1+disp):

D1 = Q1� • Q0� • $1+ (Q1+Q0) • (50c+$1)

D0 = Q1� • (Q0� • 50c+ Q0 • button)

disp = Q1 • button

D0 Q0Q0’

D1 Q1Q1’

button50c$1

dispense

D1gates

D0gates

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Vending MachineBuild Hardware (clock = 50c+$1+disp):

D0 Q0Q0’

D1 Q1Q1’

button50c$1

dispense

D1gates

de-lay

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4. Sequence Recognition• A sequence recognizer is a sequential circuit that looks for a special input

bit pattern.• The recognizer circuit has only one input, X.

– One bit of input is supplied on every clock cycle.– Easy way to permit arbitrarily long input sequences.

• There is one output, Z, which is 1 when the desired pattern is found.• Our example will detect the bit pattern �1001�:

Inputs: 1 1 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 … Outputs: 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 …

• One input and one output bit appear every clock cycle.• Requires sequential circuit because circuit has to �remember� inputs from

previous clock cycles, for finding a match.

Source: Boussaid Bräunl 2021 28

Simple Method for Sequence Detection • Recognize e.g. 1001 using a shift register• AND Qi for 1 and Q’i for 0• Note that sequence enters bitwise, so will end up back-to-front• Disadvantage:

clock

0DCLK

Y1

1DCLK

Y0 Y2

0D QQ’CLK

Y2

1DCLK

input QQ’

QQ’

QQ’

Needs 4 FF instead of 2(general case: n instead of log2n)

output

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Sequence Recognition

Source: Boussaid

• What state do we need for the sequence recognizer?– We have to �remember� inputs from previous clock cycles.– For example, if the previous three inputs were 100 and the current

input is 1, then the output should be 1.– In general, we will have to remember occurrences of parts of the

desired pattern—in this case, 1, 10, and 100.• We�ll start with a basic state diagram (edges labeled input/output):

A B C D1/0 0/0 0/0

State MeaningA None of the desired pattern (1001) has been input yet.B We’ve already seen the first bit (1) of the desired pattern.C We’ve already seen the first two bits (10) of the desired pattern.D We’ve already seen the first three bits (100) of the desired pattern.

input/outputpresent state

next state

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• What happens if we�re in state D (the last three inputs were 100), and the current input is 1?– The output should be a 1, because we�ve found the desired pattern.– But this last 1 could also be the start of another occurrence of the

pattern! For example, 1001001 contains two occurrences of 1001.– To detect overlapping occurrences of the pattern, the next state

should be B.

A B C D1/0 0/0 0/0

1/1

State MeaningA None of the desired pattern (1001) has been input yet.B We’ve already seen the first bit (1) of the desired pattern.C We’ve already seen the first two bits (10) of the desired pattern.D We’ve already seen the first three bits (100) of the desired pattern.

Bräunl 2021 Source: Boussaid

Step 1: Making a state diagram/state table

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Filling in the other arrows + State Table

• Two outgoing arrows for each node, to account for X=0 and X=1.• Remaining arrows also handle detection of overlapping occ. of 1001.


A B C D1/0 0/0 0/0

1/1

0/0

0/0

1/0

1/0

PresentState Input

NextState Output

A 0 A 0A 1 B 0B 0 C 0B 1 B 0C 0 D 0C 1 B 0D 0 A 0D 1 B 1

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PresentState Input

NextState Output

A 0 A 0A 1 B 0B 0 C 0B 1 B 0C 0 D 0C 1 B 0D 0 A 0D 1 B 1

Step 2: Assigning binary codes to states

Present State

Input

Next State

Output

Q1 Q0 X D1 D0 Z 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 0 1 1

• We have four states ABCD, so we need at least two flip-flops Q1Q0.• The easiest thing to do is represent state A with Q1Q0 = 00, B with 01,

C with 10, and D with 11. • The state assignment can have a big impact on circuit complexity.


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• Now you can make K-maps and find equations for each of the two D-flip-flop inputs, as well as for the output Z.

• These equations are in terms of the present state and the inputs.

Step 3: Find equations for next states and output

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Present State

Input

Next State

Output

Q1 Q0 X D1 D0 Z 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 0 1 1

D1 = Q1’ Q0 X’ +Q1 Q0’ X’

D0 = Q1’ Q0’ X+Q1’ Q0 X+Q1 Q0’+Q1 Q0 X

Z = Q1 Q0 X

Simplified:D1 = X’ (Q1 XOR Q0)

D0 = X + Q1 Q0’

Z = Q1 Q0 X

Source: Bräunl, Boussaid 34

Step 4: Build the circuit• Lastly, we use these simplified equations to build the completed circuit.

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D1 = X’ (Q1 XOR Q0)

D0 = X + Q1 Q0’

Z = Q1 Q0 X

D0

Q0Q0’

D1

Q1Q1’

clock

X Z

Source: Bräunl, Boussaid

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Timing diagram

• Here is one example timing diagram for our sequence detector.– The flip-flops Q1Q0 start in the initial state, 00.– On the first three positive clock edges, X is 1, 0, and 0. These

inputs cause Q1Q0 to change, so after the third edge Q1Q0 = 11.– Then when X=1, Z becomes 1 also, meaning that 1001 was found.

• The output Z does not have to change at positive clock edges. Instead, it may change whenever X changes, since Z = Q1Q0X.

CLK

Q1

Q0

X

Z

1 2 3 4


state

input

output

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5. Mealy Machine and Moore Machine• Next state is function of current state and inputs• Outputs are function of current state & inputs: Mealy machine• Outputs are function of current state only: Moore machine

Mealy Machine Moore Machine

Outputs

next Statecurrent State

outputlogic

Mem

next statelogic

Inputs

Outputsoutputlogic

next Statecurrent State

Mem

next statelogic

Inputs

0/0

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Mealy Machine Example• Example: Sequence detector for: 001• Mealy: Output is function of transition

1/0

BA C0/0

1/1

1/0

current nextstate input state outputA 0 B 0A 1 A 0B 0 C 0B 1 A 0C 0 C 0C 1 A 1

0/0

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Moore Machine Example• Example: Sequence detector for: 001• Moore: Output is function of state

0

current next statestate input state outputA 0 B } 0A 1 AB 0 C } 0B 1 AC 0 C } 0C 1 DD 0 B } 1D 1 A

B/0 C/0 D/10 1

1

1

A/0

1

0

0

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Mealy-Moore Machine ComparisonMealy Machines• Fewer states• Outputs on transitions• Input change will immediately change output,

which can cause problems

Moore Machines• More states, therefore more gates required• Safer to use• Outputs on states, therefore change at clock edge • Need to wait 1 clock signal for output change if input

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6. Sequential Circuit Analysis

Combinatorialcircuit

Inputs

Memory

Outputs

Work backwards:• Given a circuit• Derive state table / state diagram describing circuit

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Sequential Circuit Analysis Example

D0

Q0Q0’

D1

Q1Q1’

clock

X Z

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Seq. Circuit Analysis

Derive state table:

D0 Q0Q0’

D1 Q1Q1’

clock

X Z

Present State Inputs Next State Outputs Q1 Q0 X D1 D0 Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

00000001

00101000

01011101

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Seq. Circuit Analysis

Draw State Diagram:

Present State Inputs Next State Outputs Q1 Q0 X D1 D0 Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

00000001

00101000

01011101 00 01

1011

1/0

0/00/0

0/0

0/0 1/0

1/01/1

input output

state

D0 Q0Q0’

D1 Q1Q1’

clock

X Z

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Sequential Circuit Analysis

Checking• n flip-flops should generate 2n states• m inputs should generate 2*m outgoing transitions

per state (one for 0, one for 1)

In Example:• 2 flip-flops à 4 states• 1 input à 2 transitions per state

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Excursion: Derived Clock Signals

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We have: Master ClockWe want: Derived Signals A, B

(half the frequency)

MasterA B

A

B

A

B

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Derived Clock SignalsSolution1: 4 FF

One-Hot State Machine• Outputs A and B directly from FF

MasterA B

A

B

A

BMaster

1D Q

CK0

D Q

CK0

D Q

CK0

D Q

CK

A B

46

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Derived Clock Signals

47

Solution2: 2 FF• 1 FF rising edge, 1 FF falling

Master

A

B

X

A B A B

A A

B B

Y

A

BMaster

J=1 QK=1 Q’

J=1 QK=1 Q’

X

Y

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Derived Clock Signals

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Master

A

B

A B A B

X

A A

B B

A A

B

A

B

Master

J=1 QK=1 Q’

X

Single FF

Not working: “Race Condition”

Do not link master and derived/delayed signal X with gate!

chapter 7state machines 1. one hot state machine

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