chapter 6 interrupt programming

8/19/2019 Chapter 6 Interrupt Programming

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Chapter 6Chapter 6

Interrupt ProgrammingInterrupt Programming

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Why Interrupt?Why Interrupt?

• A computer is much more than the CPUA computer is much more than the CPU

– Keyboard, mouse, screen, disk drives,Keyboard, mouse, screen, disk drives,

scanner, printer, sound card, camera, etc.scanner, printer, sound card, camera, etc.

• hese devices occasiona!!y need CPUhese devices occasiona!!y need CPUserviceservice

– "ut #e can$t predict #hen"ut #e can$t predict #hen

• %o!ution &' CPU periodica!!y checks%o!ution &' CPU periodica!!y checkseach device to see i( it needs service )each device to see i( it needs service )

Po!!ingPo!!ing

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*isadvantage o( Po!!ing*isadvantage o( Po!!ing

• ++Po!!ing is !ike picking up your phonePo!!ing is !ike picking up your phone

every (e# seconds to see i( you have aevery (e# seconds to see i( you have a

ca!!.ca!!.

• -ou may get a (e# phone ca!!s a day -ou may get a (e# phone ca!!s a day/ o( your e((ort #i!! be #asted/ o( your e((ort #i!! be #asted

checking the phone.checking the phone.

• akes CPU time even #hen no re0uestakes CPU time even #hen no re0uestpendingpending

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12amp!e o( Po!!ing in Chapter 312amp!e o( Po!!ing in Chapter 3

Create a s0uare #ave o( 34/ duty cyc!e onCreate a s0uare #ave o( 34/ duty cyc!e onP5"738 bit.P5"738 bit. Here the CPU spends most of theHere the CPU spends most of thetime of this program to check the interrupt flag.time of this program to check the interrupt flag.

bcf TRISB, 5 bcf TRISB, 5 ; Set PB5 as output; Set PB5 as output bcf PORTB, 5 bcf PORTB, 5

movlw B ‘00001000’ movlw B ‘00001000’ ; 16-bt, !t cl", !o p#escale#; 16-bt, !t cl", !o p#escale# movwf T0$O% movwf T0$O%&e#e' movlw 0())&e#e' movlw 0()) ; T*R0& + 0(; T*R0& + 0( movwf T*R0& movwf T*R0& movlw 0() movlw 0() ; T*R0. + 0(//; T*R0. + 0(// movwf T*R0. movwf T*R0.

bcf I%T$O%, T*R0I) bcf I%T$O%, T*R0I) ; $lea# tme# !te##upt fla; $lea# tme# !te##upt fla bsf T0$O%, T*R0O% bsf T0$O%, T*R0O% ; sta#t Tme# 0; sta#t Tme# 0

Again:btfss INTCON, TMR0IF Again:btfss INTCON, TMR0IF

bra Againbra Again

bt PORTB, 5 bt PORTB, 5 bcf T0$O%, T*R0O% bcf T0$O%, T*R0O%

b#a &e#e b#a &e#e ; loa T*R0& a! T*R0. aa!; loa T*R0& a! T*R0. aa! 4


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InterruptInterrupt

• Whenever a device needs the CPU$sWhenever a device needs the CPU$s

service, the device noti(ies it by sendingservice, the device noti(ies it by sending

an interrupt signa!.an interrupt signa!.

• CPU then stops and serves the device.CPU then stops and serves the device.

• ++Po!!ing is !ike picking up your phonePo!!ing is !ike picking up your phone

every (e# seconds to see i( you have aevery (e# seconds to see i( you have a

ca!!. Interrupts are !ike #aiting (or theca!!. Interrupts are !ike #aiting (or thephone to ring.phone to ring.

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9CU esponse to Interrupts9CU esponse to Interrupts

• I( the interrupt re0uest is present, the 9CU'I( the interrupt re0uest is present, the 9CU' – Comp!etes the e2ecution o( the current instructionComp!etes the e2ecution o( the current instruction – %aves the address o( the program counter on the%aves the address o( the program counter on the

stackstack

• 9CU is redirected to the memory !ocation9CU is redirected to the memory !ocation#here the interrupt re0uest can be met.#here the interrupt re0uest can be met.

• he set o( instructions #ritten to meet thehe set o( instructions #ritten to meet there0uest is ca!!ed an interrupt servicere0uest is ca!!ed an interrupt service

routine :I%;.routine :I%;. The interrupt flag has to beThe interrupt flag has to bereset in ISR reset in ISR ..• 5nce the re0uest is accomp!ished, the 9CU5nce the re0uest is accomp!ished, the 9CU

shou!d (ind its #ay back to the ne2tshou!d (ind its #ay back to the ne2tinstruction, #here it #as interrupted.instruction, #here it #as interrupted.

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PIC&< InterruptPIC&< Interrupt

• PIC&< 9icrocontro!!er (ami!yPIC&< 9icrocontro!!er (ami!y

– =as mu!tip!e sources that can send=as mu!tip!e sources that can send

interrupt re0uests that can be c!assi(iedinterrupt re0uests that can be c!assi(ied

into'into'• Interna! 1ventsInterna! 1vents

• 12terna! 1vents12terna! 1vents

– =as a priority scheme divided into t#o=as a priority scheme divided into t#o

groupsgroups• =igh Priority=igh Priority

• >o# Priority>o# Priority

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PIC&< Interrupt %ourcesPIC&< Interrupt %ources

• Interna! periphera! sourcesInterna! periphera! sources – 12amp!es' imers, A* Converter, UA12amp!es' imers, A* Converter, UA

• 12terna! sources12terna! sources –

hree pins o( P5" @"4I4, "&I&,andhree pins o( P5" @"4I4, "&I&,and"BIB"BIB• hese pins can be used to connect e2terna!hese pins can be used to connect e2terna!

interrupting sources such as keyboards orinterrupting sources such as keyboards ors#itchess#itches

• Can se!ect #hether a rising or (a!!ing edge triggersCan se!ect #hether a rising or (a!!ing edge triggersan interrupt.an interrupt.

– Change in !ogic !eve!s o( pins "@"D o(Change in !ogic !eve!s o( pins "@"D o(P5" can be recogniEed as interruptsP5" can be recogniEed as interrupts

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PIC&< Interrupt %ourcesPIC&< Interrupt %ources

• 1ach interrupt source has'1ach interrupt source has' – A (!ag bit to indicate #hether the interruptA (!ag bit to indicate #hether the interrupt

has occurred :e.g., 94IF;has occurred :e.g., 94IF;

–

An enab!e bit to enab!edisab!e the interruptAn enab!e bit to enab!edisab!e the interruptsource :e.g., 94I1;source :e.g., 94I1;

– A priority bit to se!ect priority. his bit hasA priority bit to se!ect priority. his bit has

e((ect on!y #hen the priority scheme ise((ect on!y #hen the priority scheme is

enab!ed. :e.g., 94IP;enab!ed. :e.g., 94IP;

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%pecia! Function egisters :%Fs;%pecia! Function egisters :%Fs;

• C5 register sets up g!oba! priority.C5 register sets up g!oba! priority.• IC5 registers dea! primari!y #ithIC5 registers dea! primari!y #ith

e2terna! interrupt sources.e2terna! interrupt sources. – I4, I&, IB' Pins connecting e2terna!I4, I&, IB' Pins connecting e2terna!

interrupting sourcesinterrupting sources – Change in !ogic !eve!s o( pins "@"D o(Change in !ogic !eve!s o( pins "@"D o(

P5"P5"

• PI' F!ag bits o( interna! periphera!PI' F!ag bits o( interna! periphera!

interrupt sources.interrupt sources.

• PI1' 1nab!e bits o( interna! periphera!PI1' 1nab!e bits o( interna! periphera!interrupt sources.interrupt sources.

• IP' Priority bits o( interna! periphera!IP' Priority bits o( interna! periphera!

interrupt sources.interrupt sources. 10


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Interrupt PrioritiesInterrupt Priorities

• he interrupt priority (eature is enab!edhe interrupt priority (eature is enab!ed

by "itD :IP1; in C5 register.by "itD :IP1; in C5 register.

• B Cases'B Cases'

– IP1 G 4' Interrupt priority is disab!ed.IP1 G 4' Interrupt priority is disab!ed.

– IP1 G &' Interrupt priority is enab!ed.IP1 G &' Interrupt priority is enab!ed.

• Interrupts are associated #ith high and !o#Interrupts are associated #ith high and !o#

priorities.priorities.• A high@priority interrupt can interrupt a !o#@A high@priority interrupt can interrupt a !o#@

priority interrupt in progress.priority interrupt in progress.

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Interrupt Priorities %et :IP1 G &;Interrupt Priorities %et :IP1 G &;

• =igh@priority interrupts are under the=igh@priority interrupts are under thecontro! o( acontro! o( a two-leel two-leel enab!ing schemeenab!ing scheme – H!oba! =igh@Priority Interrupt 1nab!e :HI1=; bitH!oba! =igh@Priority Interrupt 1nab!e :HI1=; bit – he enab!e bit o( the interrupt sourcehe enab!e bit o( the interrupt source

• >o#@priority interrupts are under the>o#@priority interrupts are under thecontro! o(contro! o( a three-leel a three-leel enab!ing schemeenab!ing scheme – H!oba! =igh@Priority Interrupt 1nab!e :HI1=; bitH!oba! =igh@Priority Interrupt 1nab!e :HI1=; bit – H!oba! >o#@Priority Interrupt 1nab!e :HI1>; bitH!oba! >o#@Priority Interrupt 1nab!e :HI1>; bit –

he enab!e bit o( the interrupt sourcehe enab!e bit o( the interrupt source• HI1= has the same !ocation as the HI1 bitHI1= has the same !ocation as the HI1 bit

and HI1> has the same !ocation as theand HI1> has the same !ocation as theP1I1 bit. hey are interpreted di((erent!yP1I1 bit. hey are interpreted di((erent!y

#hen IP1 G &.#hen IP1 G &. 13


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Interrupt %ervice outine :I%;Interrupt %ervice outine :I%;

• When an interrupt occurs, the 9CU'When an interrupt occurs, the 9CU' – Comp!etes the instruction being e2ecutedComp!etes the instruction being e2ecuted

– *isab!es g!oba! interrupt enab!e*isab!es g!oba! interrupt enab!e

–

P!aces the address (rom the program counter onP!aces the address (rom the program counter onthe stackthe stack

– ca!! I%ca!! I%

• he starting address o( the I% :aka interrupthe starting address o( the I% :aka interrupt

vector; is prede(ined'vector; is prede(ined' – =igh Priority Interrupt ) 4244444o# Priority Interrupt ) 424444&o# Priority Interrupt ) 424444&<

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Interrupt Priorities ot %et :IP1 G 4;Interrupt Priorities ot %et :IP1 G 4;

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ret(ie vs. returnret(ie vs. return

• "oth instructions pops the 5% into PC."oth instructions pops the 5% into PC.

• eca!!' he g!oba! interrupt enab!e :HI1;eca!!' he g!oba! interrupt enab!e :HI1;

(!ag has been disab!ed #hen an(!ag has been disab!ed #hen an

interrupt is evoked to prevent mu!tip!einterrupt is evoked to prevent mu!tip!einterrupts.interrupts.

• 1FI1 enab!es the g!oba! interrupt1FI1 enab!es the g!oba! interrupt

enab!e, #hi!e 1U does not.enab!e, #hi!e 1U does not.

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12amp!e #ith Interrupt Priorities *isab!ed12amp!e #ith Interrupt Priorities *isab!ed

• We have used po!!ing to create a s0uareWe have used po!!ing to create a s0uare#ave o( 34/ duty cyc!e on P5"738#ave o( 34/ duty cyc!e on P5"738

bit.bit.

• In this e2amp!e, #e imp!ement the sameIn this e2amp!e, #e imp!ement the samething using interrupt #ith interruptthing using interrupt #ith interrupt

priorities disab!ed :IP1 G 4;.priorities disab!ed :IP1 G 4;.

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OR2 0(0000OR2 0(0000oto *a!oto *a!

OR2 0(0003OR2 0(0003

oto T04ISR oto T04ISR

OR2 0(0100OR2 0(0100

*a!' *a!' bcf TRISB, 5 bcf TRISB, 5

bcf PORTB, 5 bcf PORTB, 5 movlw 0(03; Tme#0, 16-bt, !o p#escale, !te#!al c" movlw 0(03; Tme#0, 16-bt, !o p#escale, !te#!al c"

movwf T0$O% movwf T0$O%

movlw 0()) movlw 0())

movwf T*R0& movwf T*R0&

movlw 0() movlw 0()

movwf T*R0.; loa ))) to T*R0 movwf T*R0.; loa ))) to T*R0 bcf bcf R$O%, IP%; sable I!te##upt P#o#tes R$O%, IP%; sable I!te##upt P#o#tes

bcf bcf I%T$O%, T*R0I); $lea# !te##upt fla bt I%T$O%, T*R0I); $lea# !te##upt fla bt

bsf bsf I%T$O%, T*R0I; e!able Tme#0 !te##upt I%T$O%, T*R0I; e!able Tme#0 !te##upt

bsf bsf I%T$O%, 2I; e!able lobal !te##upt I%T$O%, 2I; e!able lobal !te##upt

bsf bsf T0$O%, T*R0O%; sta#t Tme#0 T0$O%, T*R0O%; sta#t Tme#0

b#a b#a 7 7 20


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OR2 0/000OR2 0/000T04ISR'T04ISR' btfss I%T$O%, T*R0I) btfss I%T$O%, T*R0I)

b#a /IT b#a /IT

bcf I%T$O%, T*R0I) bcf I%T$O%, T*R0I)

bt PORTB, 5; tole Po#tB85 to c#eate s98 wave bt PORTB, 5; tole Po#tB85 to c#eate s98 wave



movlw 0() movlw 0()

movwf T*R0.; Re!tal:e T*R0 to ))) movwf T*R0.; Re!tal:e T*R0 to )))

/IT'/IT' #etfe#etfe

%%

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12amp!e' 5bservations12amp!e' 5bservations

• We avoided using the memory space a!!ocatedWe avoided using the memory space a!!ocatedto the interrupt vector tab!e.to the interrupt vector tab!e. – When a#akened at address 424444, PIC&


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12amp!e' 5bservations12amp!e' 5bservations

• When 94IF (!ag is raised, the 9CU gets outWhen 94IF (!ag is raised, the 9CU gets outo( the in(inite !oop in 9ain and goes to 42444


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12amp!e o( a !o#@priority interrupt12amp!e o( a !o#@priority interrupt

• In this e2amp!e, #e imp!ement the sameIn this e2amp!e, #e imp!ement the samething as the !ast e2amp!e #iththing as the !ast e2amp!e #ith

– interrupt priorities enab!ed :IP1 G &;.interrupt priorities enab!ed :IP1 G &;.

– interrupt set to !o# priorityinterrupt set to !o# priority

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OR2 0(0000OR2 0(0000

oto *a!oto *a!OR2 0(0003OR2 0(0003

#etfe; -p#o#t< !te##upt#etfe; -p#o#t< !te##upt

OR2 0(0013OR2 0(0013

oto T04ISR; low-p#o#t< !te##uptoto T04ISR; low-p#o#t< !te##upt

OR2 0(0100OR2 0(0100

*a!' *a!' bcf TRISB, 5 bcf TRISB, 5

bcf PORTB, 5 bcf PORTB, 5 movlw 0(03 movlw 0(03

movwf T0$O% movwf T0$O%



movlw 0() movlw 0()

movwf T*R0. movwf T*R0.

bsf R$O%, IP%; e!able p#o#t< !te##upt bsf R$O%, IP%; e!able p#o#t< !te##upt bcf I%T$O%, T*R0I); clea# T*R0 !te##upt fla bcf I%T$O%, T*R0I); clea# T*R0 !te##upt fla

bsf I%T$O%, T*R0I; e!able T*R0 ove#flow !te##upt bsf I%T$O%, T*R0I; e!able T*R0 ove#flow !te##upt

bcf I%T$O%, T*R0IP; set T*R0 !te##upt to low bcf I%T$O%, T*R0IP; set T*R0 !te##upt to low ;; p#o#t


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OR2 0/000OR2 0/000T04ISR'T04ISR' btfss I%T$O%, T*R0I) btfss I%T$O%, T*R0I)

b#a /IT b#a /IT

bcf I%T$O%, T*R0I) bcf I%T$O%, T*R0I)

bt PORTB, 5 bt PORTB, 5



movlw 0() movlw 0()

movwf T*R0. movwf T*R0.

/IT'/IT' RT)IRT)I

%%

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12amp!e' 5bservation12amp!e' 5bservation

• o activate a !o#@priority interrupt, #eo activate a !o#@priority interrupt, #eneed to enab!e three bits'need to enab!e three bits'

– H!oba! =igh@Priority Interrupt 1nab!e :HI1=;H!oba! =igh@Priority Interrupt 1nab!e :HI1=;

bitbit >b>bsf I%T$O%, 2I&?sf I%T$O%, 2I&? – H!oba! >o#@Priority Interrupt 1nab!e :HI1>;H!oba! >o#@Priority Interrupt 1nab!e :HI1>;

bitbit >> bsf I%T$O%, 2I.? bsf I%T$O%, 2I.?

– he enab!e bit o( the interrupt sourcehe enab!e bit o( the interrupt source >> bsf bsf

I%T$O%, T*R1I?I%T$O%, T*R1I?

• >o# priority interrupt is served at memory>o# priority interrupt is served at memory

!ocation 4244&


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App!ication' *isp!ay the digits you enterApp!ication' *isp!ay the digits you enter

(rom a keypad(rom a keypad

• -ou may ask' In the e2amp!es, the main -ou may ask' In the e2amp!es, the main(unction is doing nothing any#ays, #hy(unction is doing nothing any#ays, #hy

not ust use po!!ing?not ust use po!!ing?

•here are situations #hen interrupt musthere are situations #hen interrupt mustbe used because there are t#o things thatbe used because there are t#o things that

must be hand!ed simu!taneous!y, e.g.'must be hand!ed simu!taneous!y, e.g.'

– *etecting #hat keys are entered (rom the*etecting #hat keys are entered (rom the

keypad.keypad.

– *isp!aying the digits that have been entered in*isp!aying the digits that have been entered in

the @digit D@segment >1*.the @digit D@segment >1*.

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App!ication' *isp!ay the digits youApp!ication' *isp!ay the digits you

enter (rom a keypadenter (rom a keypad

• 9ain Program'9ain Program' – %tore the (our digits that #as entered previous!y.%tore the (our digits that #as entered previous!y.

Initia!iEe the (our digits to be say +4444 #henInitia!iEe the (our digits to be say +4444 #hennothing has been entered yet.nothing has been entered yet.

– Initia!iEe the @digit D@segment >1* to disp!ay theInitia!iEe the @digit D@segment >1* to disp!ay the(irst digit.(irst digit.

– Per(orm keypad scanning operation.Per(orm keypad scanning operation.

• Use o( Interrupt'Use o( Interrupt' – Program imer 4 to generate a 3ms de!ay.Program imer 4 to generate a 3ms de!ay.

– 94IF is raised at the end o( 3ms.94IF is raised at the end o( 3ms. – Het out o( the main (unction to serve the interruptHet out o( the main (unction to serve the interrupt

re0uest #hen 94IF G &.re0uest #hen 94IF G &. – Program I% so that the ne2t digit is disp!ayed.Program I% so that the ne2t digit is disp!ayed.

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-ou shou!d be ab!e to .... -ou shou!d be ab!e to ....

• Identi(y the di((erence bet#een po!!ingIdenti(y the di((erence bet#een po!!ingand interruptand interrupt

• >ist the advantages o( interrupts>ist the advantages o( interrupts

• 1nab!e and disab!e PIC&< interrupts1nab!e and disab!e PIC&< interrupts• 12p!ain ho# interrupts are hand!ed12p!ain ho# interrupts are hand!ed

#hen g!oba! interrupt priority is#hen g!oba! interrupt priority is

disab!ed and enab!eddisab!ed and enab!ed• *e(ine the priorities o( di((erent interrupt*e(ine the priorities o( di((erent interrupt

sources in PIC&

chapter 6 interrupt programming

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