Chapter 5. The Memory System

OverviewBasic memory circuitsOrganization of the main memoryCache memory conceptVirtual memory mechanismSecondary storage

Some Basic Concepts

Basic ConceptsThe maximum size of the memory that can be used in any computer is determined by the addressing scheme.16-bit addresses = 216 = 64K memory locationsMost modern computers are byte addressable.2k4-2k3-2k2-2k1-2k4-2k4-012345670 042k1-2k2-2k3-2k4-32107654Byte addressByte address(a) Big-endian assignment(b) Little-endian assignment4Wordaddress

Traditional ArchitectureUp to 2k addressableMDRMARFigure 5.1. Connection of the memory to the processor.k-bitaddress busn-bitdata busControl lines( , MFC, etc.)Processor MemorylocationsWord length =n bitsWR/

Basic ConceptsBlock transfer bulk data transferMemory access timeMemory cycle timeRAM any location can be accessed for a Read or Write operation in some fixed amount of time that is independent of the locations address.Cache memoryVirtual memory, memory management unit

Semiconductor RAM Memories

Internal Organization of Memory ChipsFFFigure 5.2. Organization of bit cells in a memory chip.circuitSense / WriteAddressdecoderFFCScellsMemorycircuitSense / WriteSense / WritecircuitData input/output lines:A0A1A2A3W0W1W15b7b1b0WR/b7b1b0b7b1b0

16 words of 8 bits each: 16x8 memory org.. It has 16 external connections: addr. 4, data 8, control: 2, power/ground: 21K memory cells: 128x8 memory, external connections: ? 19(7+8+2+2)1Kx1:? 15 (10+1+2+2)

A Memory ChipFigure 5.3. Organization of a 1K 1 memory chip.CSSense/Writecircuitryarraymemory celladdress5-bit rowinput/outputData5-bitdecoderaddress5-bit columnaddress10-bitoutput multiplexer 32-to-1input demultiplexer3232WR/W0W1W31and

Static MemoriesThe circuits are capable of retaining their state as long as power is applied.YXWord lineBit linesFigure 5.4. A static RAM cell.bT2T1b

Static MemoriesCMOS cell: low power consumption

Asynchronous DRAMsStatic RAMs are fast, but they cost more area and are more expensive.Dynamic RAMs (DRAMs) are cheap and area efficient, but they can not retain their state indefinitely need to be periodically refreshed.Figure 5.6. A single-transistor dynamic memory cell TCWord lineBit line

A Dynamic Memory ChipColumnCSSense / Writecircuitscell arraylatchaddressRowColumnlatchdecoderRowdecoderaddress40965128()R/WA209-A80-D0D7RASCASFigure 5.7. Internal organization of a 2M 8 dynamic memory chip.Row Addr. StrobeColumn Addr. Strobe

Fast Page ModeWhen the DRAM in last slide is accessed, the contents of all 4096 cells in the selected row are sensed, but only 8 bits are placed on the data lines D7-0, as selected by A8-0.Fast page mode make it possible to access the other bytes in the same row without having to reselect the row.A latch is added at the output of the sense amplifier in each column.Good for bulk transfer.

Synchronous DRAMsThe operations of SDRAM are controlled by a clock signal.R/WRASCASCSClockCell arraylatchaddressRowdecoderRowFigure 5.8. Synchronous DRAM.decoderColumnRead/Writecircuits & latchescounteraddressColumnRow/ColumnaddressData inputregisterData outputregisterDataRefreshcounterMode registerandtiming control

Synchronous DRAMsR/WRASCASClockFigure 5.9. Burst read of length 4 in an SDRAM.RowColD0D1D2D3AddressData

Synchronous DRAMsNo CAS pulses is needed in burst operation.Refresh circuits are included (every 64ms).Clock frequency > 100 MHzIntel PC100 and PC133

Latency and BandwidthThe speed and efficiency of data transfers among memory, processor, and disk have a large impact on the performance of a computer system.Memory latency the amount of time it takes to transfer a word of data to or from the memory.Memory bandwidth the number of bits or bytes that can be transferred in one second. It is used to measure how much time is needed to transfer an entire block of data.Bandwidth is not determined solely by memory. It is the product of the rate at which data are transferred (and accessed) and the width of the data bus.

DDR SDRAMDouble-Data-Rate SDRAMStandard SDRAM performs all actions on the rising edge of the clock signal.DDR SDRAM accesses the cell array in the same way, but transfers the data on both edges of the clock.The cell array is organized in two banks. Each can be accessed separately.DDR SDRAMs and standard SDRAMs are most efficiently used in applications where block transfers are prevalent.

Structures of Larger MemoriesFigure 5.10. Organization of a 2M 32 memory module using 512K 8 static memory chips.19-bit internal chip addressdecoder2-bitaddresses21-bitA0A1A19 memory chipA20D31-24D7-0D23-16D15-8512K8Chip select memory chip19-bitaddress512K88-bit datainput/output

Memory System ConsiderationsThe choice of a RAM chip for a given application depends on several factors:Cost, speed, power, sizeSRAMs are faster, more expensive, smaller.DRAMs are slower, cheaper, larger.Which one for cache and main memory, respectively?Refresh overhead suppose a SDRAM whose cells are in 8K rows; 4 clock cycles are needed to access each row; then it takes 81924=32,768 cycles to refresh all rows; if the clock rate is 133 MHz, then it takes 32,768/(13310-6)=24610-6 seconds; suppose the typical refreshing period is 64 ms, then the refresh overhead is 0.246/64=0.0038

Memory ControllerProcessorRASCASR/WClockAddressRow/ColumnaddressMemorycontrollerR/WClockRequestCSDataMemoryFigure 5.11. Use of a memory controller.

Read-Only Memories

Read-Only-MemoryVolatile / non-volatile memoryROMPROM: programmable ROMEPROM: erasable, reprogrammable ROMEEPROM: can be programmed and erased electricallyFigure 5.12. A ROM cell.Word linePBit lineT

Flash MemorySimilar to EEPROMDifference: only possible to write an entire block of cells instead of a single cellLow powerUse in portable equipmentImplementation of such modulesFlash cardsFlash drives

Speed, Size, and CostProcessorPrimarycacheSecondarycacheMainMagnetic diskmemoryIncreasingsizeIncreasingspeedFigure 5.13. Memory hierarchy.secondarymemoryIncreasingcost per bitRegistersL1L2

Cache Memories

CacheWhat is cache?Why we need it?Locality of reference (very important)- temporal- spatialCache block cache lineA set of contiguous address locations of some sizePage 315

CacheReplacement algorithmHit / missWrite-through / Write-backLoad throughFigure 5.14. Use of a cache memory.CacheMainmemoryProcessor

* / 19Memory HierarchyCPUCacheMain MemoryI/O ProcessorMagnetic DisksMagnetic Tapes

* / 19Cache MemoryHigh speed (towards CPU speed)Small size (power & cost)CPUCache (Fast) CacheMain Memory(Slow) MemHitMiss95% hit ratioAccess = 0.95 Cache + 0.05 Mem

* / 19Cache MemoryCPUCache 1 MwordMain Memory1 Gword30-bit AddressOnly 20 bits !!!

* / 19Cache MemoryCacheMain Memory00000000000000013FFFFFFF0000000001FFFFFAddress Mapping !!!

Direct MappingtagtagtagCacheMainmemoryBlock 0Block 1Block 127Block 128Block 129Block 255Block 256Block 257Block 4095Block 0Block 1Block 12774Main memory addressTagBlockWordFigure 5.15. Direct-mapped cache.54: one of 16 words. (each block has 16=24 words)7: points to a particular block in the cache (128=27)5: 5 tag bits are compared with the tag bits associated with its location in the cache. Identify which of the 32 blocks that are resident in the cache (4096/128).Block j of main memory maps onto block j modulo 128 of the cache

* / 19Direct MappingCache0 1 A 64 7 C C0 0 0 5000150080005000140000900000 00500Address000Tag0 1 A 6DataCompareMatchNo match10 Bits (Tag)16 Bits (Data)00000FFFFF20 Bits (Addr)What happens when Address = 100 00500

* / 19Direct Mapping with BlocksCache0 1 A 6 0 2 5 44 7 C C A 0 B 40 0 0 5 5 C 0 400015008000500 00501 01400 01401 00900 00901 000 0050 0Address000Tag0 1 A 6DataCompareMatchNo match10 Bits (Tag)16 Bits (Data)FFFFF20 Bits (Addr)00000Block Size = 16

Direct Mapping74Main memory addressTagBlockWord5Tag: 11101Block: 1111111=127, in the 127th block of the cacheWord:1100=12, the 12th word of the 127th block in the cache11101,1111111,1100

Associative Mapping4tagtagtagCacheMainmemoryBlock 0Block 1BlockiBlock 4095Block 0Block 1Block 12712Main memory addressFigure 5.16. Associative-mapped cache.TagWord4: one of 16 words. (each block has 16=24 words)12: 12 tag bits Identify which of the 4096 blocks that are resident in the cache 4096=212.

* / 19Associative MemoryCache0000000001FFFFFMain Memory00000000000000010001200008000000150000003FFFFFFF000120001500000008000000Address (Key)DataCache Location

* / 19Associative MappingCache0 1 A 64 7 C C0 0 0 50001200015000000080000000001200030 Bits (Key)16 Bits (Data)0 1 A 6DataAddressCan have any number of locationsHow many comparators?

Associative MappingTag: 111011111111Word:1100=12, the 12th word of a block in the cache111011111111,1100412Main memory addressTagWord

Set-Associative MappingtagtagtagCacheMainmemoryBlock 0Block 1Block 63Block 64Block 65Block 127Block 128Block 129Block 4095Block 0Block 1Block 126tagtagBlock 2Block 3tagBlock 127Main memory address664TagSetWordSet 0Set 1Set 63Figure 5.17. Set-associative-mapped cache with two blocks per set.4: one of 16 words. (each block has 16=24 words)6: points to a particular set in the cache (128/2=64=26)6: 6 tag bits is used to check if the desired block is present (4096/64=26).

* / 19Set-Associative MappingCache0 1 A 64 7 C C0 0 0 5000150080005000140000900000 00500Address000Tag10 1 A 6Data1CompareMatch10 Bits (Tag)16 Bits (Data)00000FFFFF20 Bits (Addr)0 7 2 10 8 2 20 9 0 9010000000010Tag20 7 2 1Data2Compare10 Bits (Tag)16 Bits (Data)2-Way Set AssociativeNo match

Set-Associative MappingTag: 111011Set: 111111=63, in the 63th set of the cacheWord:1100=12, the 12th word of the 63th set in the cacheMain memory address664TagSetWord111011,111111,1100

Replacement AlgorithmsDifficult to determine which blocks to kick outLeast Recently Used (LRU) blockThe cache controller tracks references to all blocks as computation proceeds.Increase / clear track counters when a hit/miss occurs

* / 19Replacement AlgorithmsFor Associative & Set-Associative CacheWhich location should be emptied when the cache is full and a miss occurs? First In First Out (FIFO) Least Recently Used (LRU)Distinguish an Empty location from a Full one Valid Bit

* / 19Replacement AlgorithmsCPU ReferenceABCADEADCFMissMissMissHitMissMissMissHitHitMissCacheFIFO AABABCABCABCDEBCDEACDEACDEACDEAFDHit Ratio = 3 / 10 = 0.3

* / 19Replacement AlgorithmsCPU ReferenceABCADEADCFMissMissMissHitMissMissHitHitHitMissCacheLRU ABACBAACBDACBEDACAEDCDAECCDAEFCDAHit Ratio = 4 / 10 = 0.4

Performance Considerations

OverviewTwo key factors: performance and costPrice/performance ratioPerformance depends on how fast machine instructions can be brought into the processor for execution and how fast they can be executed.For memory hierarchy, it is beneficial if transfers to and from the faster units can be done at a rate equal to that of the faster unit.This is not possible if both the slow and the fast units are accessed in the same manner.However, it can be achieved when parallelism is used in the organizations of the slower unit.

InterleavingIf the main memory is structured as a collection of physically separated modules, each with its own ABR (Address buffer register) and DBR( Data buffer register), memory access operations may proceed in more than one module at the same time.m bitsAddress in moduleMM address(a) Consecutive words in a moduleik bitsModuleModuleModuleModuleDBRABRDBRABRABRDBR0n1-Figure 5.25. Addressing multiple-module memory systems.(b) Consecutive words in consecutive modulesik bits0ModuleModuleModuleModuleMM addressDBRABRABRDBRABRDBRAddress in module2k1-m bits

Hit Rate and Miss PenaltyThe success rate in accessing information at various levels of the memory hierarchy hit rate / miss rate.Ideally, the entire memory hierarchy would appear to the processor as a single memory unit that has the access time of a cache on the processor chip and the size of a magnetic disk depends on the hit rate (>>0.9).A miss causes extra time needed to bring the desired information into the cache.Example 5.2, page 332.

Hit Rate and Miss Penalty (cont.)Tave=hC+(1-h)MTave: average access time experienced by the processorh: hit rateM: miss penalty, the time to access information in the main memoryC: the time to access information in the cacheExample:Assume that 30 percent of the instructions in a typical program perform a read/write operation, which means that there are 130 memory accesses for every 100 instructions executed.h=0.95 for instructions, h=0.9 for dataC=10 clock cycles, M=17 clock cycles, interleaved memoryTime without cache 130x10Time with cache 100(0.95x1+0.05x17)+30(0.9x1+0.1x17)The computer with the cache performs five times better

= 5.04

How to Improve Hit Rate?Use larger cache increased costIncrease the block size while keeping the total cache size constant.However, if the block size is too large, some items may not be referenced before the block is replaced miss penalty increases.Load-through approach

Caches on the Processor ChipOn chip vs. off chipTwo separate caches for instructions and data, respectivelySingle cache for bothWhich one has better hit rate? -- Single cache Whats the advantage of separating caches? parallelism, better performanceLevel 1 and Level 2 cachesL1 cache faster and smaller. Access more than one word simultaneously and let the processor use them one at a time.L2 cache slower and larger. How about the average access time?Average access time: tave = h1C1 + (1-h1)h2C2 + (1-h1)(1-h2)Mwhere h is the hit rate, C is the time to access information in cache, M is the time to access information in main memory.

Other EnhancementsWrite buffer processor doesnt need to wait for the memory write to be completedPrefetching prefetch the data into the cache before they are neededLockup-Free cache processor is able to access the cache while a miss is being serviced.

Virtual Memories

OverviewPhysical main memory is not as large as the address space spanned by an address issued by the processor.232 = 4 GB, 264 = When a program does not completely fit into the main memory, the parts of it not currently being executed are stored on secondary storage devices.Techniques that automatically move program and data blocks into the physical main memory when they are required for execution are called virtual-memory techniques.Virtual addresses will be translated into physical addresses.

OverviewMemory Management Unit

Address TranslationAll programs and data are composed of fixed-length units called pages, each of which consists of a block of words that occupy contiguous locations in the main memory.Page cannot be too small or too large.The virtual memory mechanism bridges the size and speed gaps between the main memory and secondary storage similar to cache.

Example: Example of Address TranslationProg 1VirtualAddressSpace 1Prog 2VirtualAddressSpace 2Translation Map 1Translation Map 2Physical Address Space

Page Tables and Address TranslationThe role of page table in the virtual-to-physical address translation process.

Address TranslationPage frameVirtual address from processorin memoryOffsetOffsetVirtual page numberPage table addressPage table base registerFigure 5.27. Virtual-memory address translation.ControlbitsPhysical address in main memoryPAGE TABLEPage frame+

Address TranslationThe page table information is used by the MMU for every access, so it is supposed to be with the MMU.However, since MMU is on the processor chip and the page table is rather large, only small portion of it, which consists of the page table entries that correspond to the most recently accessed pages, can be accommodated within the MMU.Translation Lookaside Buffer (TLB)

TLBFigure 5.28. Use of an associative-mapped TLB.NoYesHitMissVirtual address from processorTLBOffsetVirtual page numbernumberVirtual pagePage framein memoryControlbitsOffsetPhysical address in main memoryPage frame=?

TLBThe contents of TLB must be coherent with the contents of page tables in the memory.Translation procedure.Page faultPage replacementWrite-through is not suitable for virtual memory.Locality of reference in virtual memory

Memory Management RequirementsMultiple programsSystem space / user spaceProtection (supervisor / user state, privileged instructions)Shared pages

Secondary Storage

Magnetic Hard DisksDisk

Disk drive

Disk controller

Organization of Data on a DiskSector 0, track 0Sector 3, tracknFigure 5.30. Organization of one surface of a disk.Sector 0, track 1

Access Data on a DiskSector headerFollowing the data, there is an error-correction code (ECC).Formatting processDifference between inner tracks and outer tracksAccess time seek time / rotational delay (latency time)Data buffer/cache

Disk ControllerProcessorMain memorySystem busFigure 5.31. Disks connected to the system bus.Disk controllerDisk driveDisk drive

Disk ControllerSeekReadWriteError checking

RAID Disk ArraysRedundant Array of Inexpensive DisksUsing multiple disks makes it cheaper for huge storage, and also possible to improve the reliability of the overall system.RAID0 data stripingRAID1 identical copies of data on two disksRAID2, 3, 4 increased reliabilityRAID5 parity-based error-recovery

Optical DisksAluminumAcrylicLabel(a) Cross-sectionPolycarbonate plasticSourceDetectorSourceDetectorSourceDetectorNo reflectionReflectionReflectionPitLand00010000100010010010(c) Stored binary patternFigure 5.32. Optical disk.PitLand1(b) Transition from pit to land

Optical DisksCD-ROMCD-Recordable (CD-R)CD-ReWritable (CD-RW)DVDDVD-RAM

Magnetic Tape SystemsFigure 5.33. Organization of data on magnetic tape.

FileFilemarkmarkFile7 or 9gapgapFile gapRecordRecordRecordRecordbits

Homework Page 361: 5.6, 5.9, 5.10(a)Due time: 10:30am, Monday, March 26

Requirements for Homework5.6. (a): 1 credits5.6. (b):Draw a figure to show how program words are mapped on the cache blocks: 2Sequence of reads from the main memory blocks into cache blocks:2Total time for reading blocks from the main memory: 2Executing the program out of the cache:Beginning section of program:1Outer loop excluding Inner loop:1Inner loop:1End section of program:1Total execution time:1

Hints for HomeworkAssume that consecutive addresses refer to consecutive words. The cycle time is for one wordTotal time for reading blocks from the main memory: the number of readsx128x10Executing the program out of the cacheMEM word size for instructionsxloopNumx1Outer loop excluding Inner loop: (outer loop word size-inner loop word size)x10x1Inner loop: inner loop word sizex20x10x1MEM word size from MEM 23 to 1200 is 1200-22MEM word size from MEM 1201 to 1500(end) is 1500-1200

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