chapter 5 - memory - cs.slu.educs.slu.edu/~fritts/csci2400/schedule/ddcaarm_ch5-memoryarrays.pdf ·...

Chapter5<1>DigitalDesignandComputerArchitecture:ARM®Edi>on©2015

Chapter5-Memory

DigitalDesignandComputerArchitecture:ARM®Edi*onSarahL.HarrisandDavidMoneyHarris


Chapter5::Topics

•  Introduc*on•  Arithme*cCircuits•  NumberSystems•  Sequen*alBuildingBlocks•  MemoryArrays•  LogicArrays


Address

Data

ArrayN

M

•  Efficientlystorelargeamountsofdata•  3commontypes:

–  Dynamicrandomaccessmemory(DRAM)–  Sta>crandomaccessmemory(SRAM)–  Readonlymemory(ROM)

•  M-bitdatavalueread/wriUenateachuniqueN-bitaddress

MemoryArrays


Address

Data

ArrayN

M

Address Data11

10

01

00

depth

0 1 0

1 0 0

1 1 0

0 1 1

width

Address

Data

Array2

3

•  2-dimensionalarrayofbitcells•  Eachbitcellstoresonebit•  NaddressbitsandMdatabits:

–  2NrowsandMcolumns–  Depth:numberofrows(numberofwords)–  Width:numberofcolumns(sizeofword)–  Arraysize:depth×width=2N×M

MemoryArrays


Address

Data

1024-word x32-bitArray

10

32

MemoryArrayExample•  4 KB memory array •  Number of words: 1024 •  Word size: 32-bits (4 bytes)


Address Data11

10

01

00

depth

0 1 0

1 0 0

1 1 0

0 1 1

width

Address

Data

Array2

3

•  22 × 3-bit array •  Number of words: 4 •  Word size: 3-bits •  For example, the 3-bit word stored at address 10 is 100

MemoryArrayExample


stored bit

wordlinebitline

stored bit = 0

wordline = 1

stored bit = 1

stored bit = 0

stored bit = 1

bitline =

(a) (b)

wordline = 1

wordline = 0

wordline = 0

bitline =

bitline =

bitline =

MemoryArrayBitCells


stored bit

wordlinebitline

stored bit = 0

wordline = 1

stored bit = 1

stored bit = 0

stored bit = 1

bitline =

(a) (b)

wordline = 1

wordline = 0

wordline = 0

bitline =

bitline =

bitline =

0

1

Z

Z

MemoryArrayBitCells


wordline311

10

2:4Decoder

Address

01

00

storedbit = 0wordline2

wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

bitline2 bitline1 bitline0

Data2 Data1 Data0

2

•  Wordline:–  likeanenable–  singlerowinmemoryarrayread/wriUen–  correspondstouniqueaddress–  onlyonewordlineHIGHatonce

MemoryArray


•  Randomaccessmemory(RAM):vola*le•  Readonlymemory(ROM):nonvola*le

TypesofMemory


•  Vola*le:losesitsdatawhenpoweroff•  ReadandwriUenquickly• MainmemoryinyourcomputerisRAM(DRAM)

Historicallycalledrandomaccessmemorybecauseanydatawordaccessedaseasilyasanyother(incontrasttosequen>alaccessmemoriessuchasataperecorder)

RAM:RandomAccessMemory


•  Nonvola*le:retainsdatawhenpoweroff•  Readquickly,butwri>ngisimpossibleorslow

•  Flashmemoryincameras,thumbdrives,anddigitalcamerasareallROMs

HistoricallycalledreadonlymemorybecauseROMswerewriUenatmanufacturing>meorbyburningfuses.OnceROMwasconfigured,itcouldnotbewriUenagain.ThisisnolongerthecaseforFlashmemoryandothertypesofROMs.

ROM:ReadOnlyMemory


•  DRAM(Dynamicrandomaccessmemory)•  SRAM(Sta>crandomaccessmemory)•  Differinhowtheystoredata:

–  DRAMusesacapacitor–  SRAMusescross-coupledinverters

TypesofRAM


•  InventedDRAMin1966atIBM

•  Otherswereskep>calthattheideawouldwork

•  Bythemid-1970’sDRAMinvirtuallyallcomputers

RobertDennard,1932-


stored bit

wordlinebitline

wordline

bitline

storedbit

•  Databitsstoredoncapacitor•  Dynamicbecausethevalueneedstoberefreshed

(rewriUen)periodicallyandaierread:–  Chargeleakagefromthecapacitordegradesthevalue–  Readingdestroysthestoredvalue

DRAM


wordline

bitline

wordline

bitline

+ +storedbit = 1

storedbit = 0

DRAM


stored bit

wordlinebitline

wordlinebitline bitline

SRAM


wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2

wordlinebitline bitline

wordline

bitline

DRAMbitcell: SRAMbitcell:

MemoryArraysReview


A1

A3WD3

WE3

A2

CLK

Array

RD2RD1 M

MNN

NM

•  Port:address/datapair•  3-portedmemory

–  2readports(A1/RD1,A2/RD2)–  1writeport(A3/WD3,WE3enableswri>ng)

•  Registerfile:smallmul>-portedmemory

Mul>-portedMemories


11

10

2:4 Decoder

Address

Data0Data1Data2

01

00

2

Address Data11

10

01

00

depth

0 1 0

1 0 0

1 1 0

0 1 1

width

ROMStorage


11

10

2:4 Decoder

Address

Data0Data1Data2

01

00

2

wordline

bitline

wordline

bitline

bit cellcontaining 0

bit cellcontaining 1

ROM:DotNota>on


Implementthefollowinglogicfunc>onsusinga22×3-bitmemoryarray:

–  X = AB –  Y = A + B –  Z = A B

LogicwithMemoryArrays


wordline311

10

2:4Decoder

A, B

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 0

storedbit = 0


X Y Z

2

Implementthefollowinglogicfunc>onsusinga22×3-bitmemoryarray:

–  X = AB –  Y = A + B –  Z = A B



storedbit = 1

storedbit = 0

00

01

2:4Decoder

A

storedbit = 0

bitline

storedbit = 0

Y

B

10

11

4-word x 1-bit Array

A B Y0 00 11 01 1

0001

TruthTable

A1

A0

Calledlookuptables(LUTs):lookupoutputateachinputcombina>on(address)



•  PLAs(Programmablelogicarrays)–  ANDarrayfollowedbyORarray–  Combina>onallogiconly–  Fixedinternalconnec>ons

•  FPGAs(Fieldprogrammablegatearrays)–  ArrayofLogicElements(LEs)–  Combina>onalandsequen>allogic–  Programmableinternalconnec>ons

LogicArrays


•  DevelopedmemoriesandhighspeedcircuitsatToshiba,1971-1994

•  InventedFlashmemoryasanunauthorizedprojectpursuedduringnightsandweekendsinthelate1970’s

•  Theprocessoferasingthememoryremindedhimoftheflashofacamera

•  Toshibaslowtocommercializetheidea;Intelwasfirsttomarketin1988

•  Flashhasgrownintoa$25billionperyearmarket

FujioMasuoka,1944-

chapter 5 - memory - cs.slu.educs.slu.edu/~fritts/csci2400/schedule/ddcaarm_ch5-memoryarrays.pdf ·...

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