chapter 5:
DESCRIPTION
Chapter 5:. Digital Logic Design. Synchronous Sequential Logic. Combinational Circuit. Inputs. Outputs. Memory Elements. Combinational Circuit. Inputs. Outputs. Flip-flops. Clock. Sequential Circuits. Asynchronous Synchronous. Latches. SR Latch. Q = Q 0. 0. 0. 1. 0. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/1.jpg)
Chapter 5:Chapter 5:
![Page 2: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/2.jpg)
22 / 60 / 60
Sequential CircuitsSequential Circuits
CombinationalCircuit Memory
Elements
Inputs Outputs
Asynchronous
Synchronous
CombinationalCircuit
Flip-flops
Inputs Outputs
Clock
![Page 3: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/3.jpg)
33 / 60 / 60
LatchesLatches
SR Latch
R
S
Q
Q
S R Q0 Q Q’0 0 0
0
1
0
0
0 1 Q = Q0
Initial Value
![Page 4: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/4.jpg)
44 / 60 / 60
LatchesLatches
SR Latch
R
S
Q
Q
S R Q0 Q Q’0 0 0 0 10 0 1
1
0
0
0
1 0 Q = Q0
Q = Q0
![Page 5: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/5.jpg)
55 / 60 / 60
LatchesLatches
SR Latch
R
S
Q
Q
S R Q0 Q Q’0 0 0 0 10 0 1 1 00 1 0 0
0
1
1
0
1 Q = 0
Q = Q0
![Page 6: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/6.jpg)
66 / 60 / 60
LatchesLatches
SR Latch
R
S
Q
Q
S R Q0 Q Q’0 0 0 0 10 0 1 1 00 1 0 0 10 1 11
0
1
0
0 1Q = 0
Q = Q0
Q = 0
![Page 7: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/7.jpg)
77 / 60 / 60
LatchesLatches
SR Latch
R
S
Q
Q
S R Q0 Q Q’0 0 0 0 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0
0
1
0
1
1 0
Q = 0
Q = Q0
Q = 1
![Page 8: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/8.jpg)
88 / 60 / 60
LatchesLatches
SR Latch
R
S
Q
Q
S R Q0 Q Q’0 0 0 0 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0 1 01 0 1
1
0
0
1
1 0
Q = 0
Q = Q0
Q = 1Q = 1
![Page 9: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/9.jpg)
99 / 60 / 60
LatchesLatches
SR Latch
R
S
Q
Q
S R Q0 Q Q’0 0 0 0 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0 1 01 0 1 1 01 1 0
0
1
1
1
0 0
Q = 0
Q = Q0
Q = 1
Q = Q’
0
![Page 10: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/10.jpg)
1010 / 60 / 60
LatchesLatches
SR Latch
R
S
Q
Q
S R Q0 Q Q’0 0 0 0 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0 1 01 0 1 1 01 1 0 0 01 1 1
1
0
1
1
0 0
Q = 0
Q = Q0
Q = 1
Q = Q’
0
Q = Q’
![Page 11: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/11.jpg)
1111 / 60 / 60
LatchesLatches
SR LatchR
S
Q
Q
S R Q0 0 Q0
0 1 01 0 11 1 Q=Q’=0
No changeResetSet
Invalid
S
R
Q
Q
S R Q0 0 Q=Q’=10 1 11 0 01 1 Q0
InvalidSet
ResetNo change
![Page 12: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/12.jpg)
1212 / 60 / 60
LatchesLatches
SR LatchR
S
Q
Q
S R Q0 0 Q0
0 1 01 0 11 1 Q=Q’=0
No changeResetSet
Invalid
S’ R’ Q0 0 Q=Q’=10 1 11 0 01 1 Q0
InvalidSet
ResetNo change
S
R
Q
Q
![Page 13: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/13.jpg)
1313 / 60 / 60
Controlled LatchesControlled Latches
SR Latch with Control Input
C S R Q0 x x Q0
1 0 0 Q0
1 0 1 01 1 0 11 1 1 Q=Q’
No changeNo change
ResetSet
Invalid
S
R
Q
Q
S
R
C
S
RQ
QS
R
C
![Page 14: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/14.jpg)
1414 / 60 / 60
Controlled LatchesControlled Latches
D Latch (D = Data)
C D Q0 x Q0
1 0 01 1 1
No changeResetSet
S
R
Q
Q
D
C
C
Timing Diagram
D
Q
t
Output may change
![Page 15: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/15.jpg)
1515 / 60 / 60
Controlled LatchesControlled Latches
D Latch (D = Data)
C D Q0 x Q0
1 0 01 1 1
No changeResetSet
C
Timing Diagram
D
Q
Output may change
S
R
Q
Q
D
C
![Page 16: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/16.jpg)
1616 / 60 / 60
Flip-FlopsFlip-Flops
Controlled latches are level-triggered
Flip-Flops are edge-triggered
C
CLK Positive Edge
CLK Negative Edge
![Page 17: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/17.jpg)
1717 / 60 / 60
Flip-FlopsFlip-Flops
Master-Slave D Flip-Flop
D Latch(Master)
D
C
Q D Latch(Slave)
D
C
Q QD
CLK CLK
D
QMaster
QSlave
Looks like it is negative edge-triggered
Master Slave
![Page 18: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/18.jpg)
1818 / 60 / 60
Flip-FlopsFlip-Flops
Edge-Triggered D Flip-Flop
D
CLKQ
Q
D Q
Q
D Q
Q
Positive Edge
Negative Edge
![Page 19: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/19.jpg)
1919 / 60 / 60
Flip-FlopsFlip-Flops
JK Flip-Flop
D Q
Q
Q
QCLK
J
K
J Q
QK
D = JQ’ + K’Q
![Page 20: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/20.jpg)
2020 / 60 / 60
Flip-FlopsFlip-Flops
T Flip-Flop
D = TQ’ + T’Q = T Q
J Q
QK
T D Q
Q
T
D = JQ’ + K’Q T Q
Q
![Page 21: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/21.jpg)
2121 / 60 / 60
Flip-Flop Characteristic TablesFlip-Flop Characteristic Tables
D Q
Q
D Q(t+1)0 01 1
ResetSet
J K Q(t+1)0 0 Q(t)0 1 01 0 11 1 Q’(t)
No changeReset
SetToggle
J Q
QK
T Q
Q
T Q(t+1)0 Q(t)1 Q’(t)
No changeToggle
![Page 22: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/22.jpg)
2222 / 60 / 60
Flip-Flop Characteristic EquationsFlip-Flop Characteristic Equations
D Q
Q
D Q(t+1)0 01 1
Q(t+1) = D
J K Q(t+1)0 0 Q(t)0 1 01 0 11 1 Q’(t)
Q(t+1) = JQ’ + K’QJ Q
QK
T Q
Q
T Q(t+1)0 Q(t)1 Q’(t)
Q(t+1) = T Q
![Page 23: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/23.jpg)
2323 / 60 / 60
Flip-Flop Characteristic EquationsFlip-Flop Characteristic Equations
Analysis / Derivation
J Q
QK
J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 00 1 11 0 01 0 11 1 01 1 1
No change
Reset
Set
Toggle
![Page 24: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/24.jpg)
2424 / 60 / 60
Flip-Flop Characteristic EquationsFlip-Flop Characteristic Equations
Analysis / Derivation
J Q
QK
J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 01 0 11 1 01 1 1
No change
Reset
Set
Toggle
![Page 25: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/25.jpg)
2525 / 60 / 60
Flip-Flop Characteristic EquationsFlip-Flop Characteristic Equations
Analysis / Derivation
J Q
QK
J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 01 1 1
No change
Reset
Set
Toggle
![Page 26: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/26.jpg)
2626 / 60 / 60
Flip-Flop Characteristic EquationsFlip-Flop Characteristic Equations
Analysis / Derivation
J Q
QK
J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0
No change
Reset
Set
Toggle
![Page 27: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/27.jpg)
2727 / 60 / 60
Flip-Flop Characteristic EquationsFlip-Flop Characteristic Equations
Analysis / Derivation
J Q
QK
J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0
K
0 1 0 0J 1 1 0 1
Q
Q(t+1) = JQ’ + K’Q
![Page 28: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/28.jpg)
2828 / 60 / 60
Flip-Flops with Direct InputsFlip-Flops with Direct Inputs
Asynchronous Reset
D Q
Q
R
Reset
R’ D CLK Q(t+1)0 x x 0
![Page 29: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/29.jpg)
2929 / 60 / 60
Flip-Flops with Direct InputsFlip-Flops with Direct Inputs
Asynchronous Reset
D Q
Q
R
Reset
R’ D CLK Q(t+1)0 x x 01 0 ↑ 01 1 ↑ 1
![Page 30: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/30.jpg)
3030 / 60 / 60
Flip-Flops with Direct InputsFlip-Flops with Direct Inputs
Asynchronous Preset and Clear
PR’ CLR’ D CLK Q(t+1)1 0 x x 0D Q
Q
CLR
Reset
PR
Preset
![Page 31: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/31.jpg)
3131 / 60 / 60
Flip-Flops with Direct InputsFlip-Flops with Direct Inputs
Asynchronous Preset and Clear
PR’ CLR’ D CLK Q(t+1)1 0 x x 00 1 x x 1
D Q
Q
CLR
Reset
PR
Preset
![Page 32: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/32.jpg)
3232 / 60 / 60
Flip-Flops with Direct InputsFlip-Flops with Direct Inputs
Asynchronous Preset and Clear
PR’ CLR’ D CLK Q(t+1)1 0 x x 00 1 x x 11 1 0 ↑ 01 1 1 ↑ 1
D Q
Q
CLR
Reset
PR
Preset
![Page 33: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/33.jpg)
3333 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
The State● State = Values of all Flip-Flops
Example
A B = 0 0
D Q
Q
CLK
D Q
Q
A
B
y
x
![Page 34: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/34.jpg)
3434 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
State EquationsD Q
Q
CLK
D Q
Q
A
B
y
x
A(t+1) = DA
= A(t) x(t)+B(t) x(t)
= A x + B x
B(t+1) = DB
= A’(t) x(t)
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
![Page 35: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/35.jpg)
3535 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
State Table (Transition Table)D Q
Q
CLK
D Q
Q
A
B
y
x
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
Present State Input Next
State Output
A B x A B y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
t+1 tt
0 0 00 1 00 0 11 1 00 0 11 0 00 0 11 0 0
![Page 36: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/36.jpg)
3636 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
State Table (Transition Table)D Q
Q
CLK
D Q
Q
A
B
y
x
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
Present State
Next State Output
x = 0 x = 1 x = 0 x = 1
A B A B A B y y0 0 0 0 0 1 0 00 1 0 0 1 1 1 01 0 0 0 1 0 1 01 1 0 0 1 0 1 0
t+1 tt
![Page 37: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/37.jpg)
3737 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
State Diagram
D Q
Q
CLK
D Q
Q
A
B
y
x
0 0 1 0
0 1 1 1
0/0
0/1
1/0
1/0
1/0
1/0 0/10/1
AB input/output
Present State
Next State Output
x = 0 x = 1 x = 0 x = 1
A B A B A B y y
0 0 0 0 0 1 0 00 1 0 0 1 1 1 01 0 0 0 1 0 1 01 1 0 0 1 0 1 0
![Page 38: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/38.jpg)
3838 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
D Flip-Flops
Example: D Q
Q
x
CLK
yA
Present State Input Next
StateA x y A0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
01101001
0 100,11 00,11
01,10
01,10
A(t+1) = DA = A x y
![Page 39: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/39.jpg)
3939 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
JK Flip-Flops
Example:
J Q
QK
CLK
J Q
QK
x
A
B
JA = B KA = B x’JB = x’ KB = A x
A(t+1) = JA Q’A + K’A QA
= A’B + AB’ + AxB(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’
Present State I/P Next
StateFlip-Flop
InputsA B x A B JA KA JB KB
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 0 1 00 0 0 11 1 1 01 0 0 10 0 1 10 0 0 01 1 1 11 0 0 0
0 10 01 11 01 11 00 01 1
![Page 40: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/40.jpg)
4040 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
JK Flip-Flops
Example:
J Q
QK
CLK
J Q
QK
x
A
BPresent State I/P Next
StateFlip-Flop
InputsA B x A B JA KA JB KB
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 0 1 00 0 0 11 1 1 01 0 0 10 0 1 10 0 0 01 1 1 11 0 0 0
0 10 01 11 01 11 00 01 1
0 0 1 1
0 1 1 0
1 0 1
0
1
0 0
1
![Page 41: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/41.jpg)
4141 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
T Flip-Flops
Example:
TA = B x TB = xy = A B
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’BxB(t+1) = TB Q’B + T’B QB
= x B
A
B
T Q
QR
T Q
QR
CLK Reset
xy
Present State I/P Next
StateF.F
Inputs O/P
A B x A B TA TB y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 00 10 01 10 00 10 01 1
0 00 10 11 01 01 11 10 0
00000011
![Page 42: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/42.jpg)
4242 / 60 / 60
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
T Flip-Flops
Example:
A
B
T Q
QR
T Q
QR
CLK Reset
xy
Present State I/P Next
StateF.F
Inputs O/P
A B x A B TA TB y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 00 10 01 10 00 10 01 1
0 00 10 11 01 01 11 10 0
00000011
0 0 0 1
1 1 1 0
0/01/0
0/0
1/0
1/0
1/1
0/00/1
![Page 43: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/43.jpg)
4343 / 60 / 60
Mealy and Moore ModelsMealy and Moore Models
Present State I/P Next
State O/P
A B x A B y0 0 0 0 0 00 0 1 0 1 00 1 0 0 0 10 1 1 1 1 01 0 0 0 0 11 0 1 1 0 01 1 0 0 0 11 1 1 1 0 0
MealyMealy
For the same statestate,the outputoutput changes with the inputinput
Present State I/P Next
State O/P
A B x A B y0 0 0 0 0 00 0 1 0 1 00 1 0 0 1 00 1 1 1 0 01 0 0 1 0 01 0 1 1 1 01 1 0 1 1 11 1 1 0 0 1
MooreMoore
For the same statestate,the outputoutput does not change with the inputinput
![Page 44: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/44.jpg)
4444 / 60 / 60
Moore State DiagramMoore State Diagram
State / Output
0 0 / 0 0 1 / 0
1 1 / 1 1 0 / 0
0
1
1
1
00
01
![Page 45: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/45.jpg)
4545 / 60 / 60
Timing DiagramTiming Diagram
0 0 / 0 0 1 / 0
1 1 / 1 1 0 / 0
0 0
1
1
0 0
1
1
CLK
StateA
B
y
x
No effect
0
0
0
1
1
0
0
0
0
1
0
1
A
Bx y
![Page 46: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/46.jpg)
4646 / 60 / 60
Timing DiagramTiming Diagram
0 0 0 1
1 1 1 0
0/0 0/0
1/0
1/1
0/0 0/0
1/1
1/0
CLK
StateA
B
y
x
1
0
A
Bx y
![Page 47: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/47.jpg)
4747 / 60 / 60
Design of Clocked Sequential CircuitsDesign of Clocked Sequential Circuits
Example:Detect 3 or more consecutive 1’s
S0 / 0 S1 / 0
S3 / 1 S2 / 0
0
1
1
0 0
1
0
1
State A BS0 0 0S1 0 1S2 1 0S3 1 1
![Page 48: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/48.jpg)
4848 / 60 / 60
Design of Clocked Sequential CircuitsDesign of Clocked Sequential Circuits
Example:Detect 3 or more consecutive 1’s
Present State Input Next
State Output
A B x A B y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 0 00 1 00 0 01 0 00 0 01 1 00 0 11 1 1
S0 / 0 S1 / 0
S3 / 1 S2 / 0
0
1
1
0 0
1
0
1
![Page 49: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/49.jpg)
4949 / 60 / 60
Design of Clocked Sequential CircuitsDesign of Clocked Sequential Circuits
Example:Detect 3 or more consecutive 1’s
Present State Input Next
State Output
A B x A B y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 0 00 1 00 0 01 0 00 0 01 1 00 0 11 1 1
A(t+1) = DA (A, B, x)
= ∑ (3, 5, 7)
B(t+1) = DB (A, B, x)
= ∑ (1, 5, 7)
y (A, B, x) = ∑ (6, 7)
Synthesis using DD Flip-Flops
![Page 50: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/50.jpg)
5050 / 60 / 60
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with DD F.F. F.F.
Example:Detect 3 or more consecutive 1’s
DA (A, B, x) = ∑ (3, 5, 7)
= A x + B x
DB (A, B, x) = ∑ (1, 5, 7)
= A x + B’ x
y (A, B, x) = ∑ (6, 7)
= A B
Synthesis using DD Flip-FlopsB
0 0 1 0A 0 1 1 0
x B
0 1 0 0A 0 1 1 0
xB
0 0 0 0A 0 0 1 1
x
![Page 51: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/51.jpg)
5151 / 60 / 60
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with DD F.F. F.F.
Example:Detect 3 or more consecutive 1’s
DA = A x + B x
DB = A x + B’ x
y = A B
Synthesis using DD Flip-Flops
D Q
Q
A
CLK
x
BD Q
Q
y
![Page 52: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/52.jpg)
5252 / 60 / 60
Flip-Flop Excitation TablesFlip-Flop Excitation Tables
Present State
Next State
F.F.Input
Q(t) Q(t+1) D0 00 11 01 1
Present State
Next State
F.F.Input
Q(t) Q(t+1) J K0 00 11 01 1
0 0 (No change)0 1 (Reset)0 x
1 xx 1x 0
0101
1 0 (Set)1 1 (Toggle)0 1 (Reset)1 1 (Toggle)0 0 (No change)1 0 (Set)
Q(t) Q(t+1) T0 00 11 01 1
0110
![Page 53: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/53.jpg)
5353 / 60 / 60
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JKJK F.F. F.F.
Example:Detect 3 or more consecutive 1’s
Present State Input Next
StateFlip-Flop
InputsA B x A B JA KA JB KB
0 0 0 0 00 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 11 1 0 0 01 1 1 1 1
0 x0 x0 x1 xx 1x 0x 1x 0
JA (A, B, x) = ∑ (3)dJA (A, B, x) = ∑ (4,5,6,7)KA (A, B, x) = ∑ (4, 6)dKA (A, B, x) = ∑ (0,1,2,3)JB (A, B, x) = ∑ (1, 5)dJB (A, B, x) = ∑ (2,3,6,7)KB (A, B, x) = ∑ (2, 3, 6)dKB (A, B, x) = ∑ (0,1,4,5)
Synthesis using JKJK F.F.
0 x1 xx 1x 10 x1 xx 1x 0
![Page 54: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/54.jpg)
5454 / 60 / 60
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JKJK F.F. F.F.
Example:Detect 3 or more consecutive 1’s
JA = B x KA = x’
JB = x KB = A’ + x’
Synthesis using JKJK Flip-FlopsB
0 0 1 0A x x x x
x
B
x x x xA 1 0 0 1
xB
0 1 x xA 0 1 x x
x
B
x x 1 1A x x 0 1
x
CLK
J Q
QK
x
A
B
J Q
QK y
![Page 55: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/55.jpg)
5555 / 60 / 60
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with TT F.F. F.F.
Example:Detect 3 or more consecutive 1’s
Present State Input Next
StateF.F.
InputA B x A B TA TB
0 0 0 0 00 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 11 1 0 0 01 1 1 1 1
00011010
Synthesis using TT Flip-Flops01110110
TA (A, B, x) = ∑ (3, 4, 6)TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
![Page 56: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/56.jpg)
5656 / 60 / 60
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with TT F.F. F.F.
Example:Detect 3 or more consecutive 1’s
TA = A x’ + A’ B x
TB = A’ B + B x
Synthesis using TT Flip-Flops
B
0 0 1 0A 1 0 0 1
x
B
0 1 1 1A 0 1 0 1
x
A
B
y
T Q
Q
x
CLK
T Q
Q
![Page 57: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/57.jpg)
5757 / 60 / 60
HomeworkHomework
Mano● Chapter 5
♦ 5-1
♦ 5-3
♦ 5-6
♦ 5-8
♦ 5-9
![Page 58: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/58.jpg)
5858 / 60 / 60
HomeworkHomework
5-1 The D latch is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation.
(a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed.
(b) Use NOR gates for all four gates. Inverters may be needed.
(c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate that goes to the SR latch to the input of the lower gate instead of the inverter output.
![Page 59: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/59.jpg)
5959 / 60 / 60
HomeworkHomework
5-3 Show that the characteristic equation for the complement output of a JK flip-flop is
Q’(t+1) = J’Q + K Q5-6 A sequential circuit with two D flip-flops, A and B; two
inputs, x and y; and one output, z, is specified by the following next-state and output equations:
A(t+1) = x’ y + x A B(t+1) = x’ B + x A z = B
(a) Draw the logic diagram of the circuit.
(b) List the state table for the sequential circuit.
(c) Draw the corresponding state diagram.
![Page 60: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/60.jpg)
6060 / 60 / 60
HomeworkHomework
5-8 Derive the state table and the state diagram of the sequential shown circuit. Explain the function that the circuit performs.
A B
CLK
T
Q Q
T
Q Q
![Page 61: Chapter 5:](https://reader036.vdocuments.site/reader036/viewer/2022062305/5681632d550346895dd3a77c/html5/thumbnails/61.jpg)
6161 / 60 / 60
HomeworkHomework
5-9 A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described by the following flip-flop input equations:
JA = x KA = B’
JB = x KB = A
(a) Derive the state equations A(t+1) and B(t+1) by substituting the input equations for the J and K variables.
(b) Draw the state diagram of the circuit.