chapter 4 bj ts dc biasing
DESCRIPTION
bipolar junction transistorTRANSCRIPT
The 1st transistor ever built
Transistor operation
Chapter 4 Chapter 4 DC biasing-DC biasing-
BJTsBJTs
Chapter 4 Chapter 4 DC biasing-DC biasing-
BJTsBJTs
Faculty of Electrical and Electronic Engineering
Topics objectives
• You’ll learn• Q-point of a transistor
operation• About DC analysis of a
transistor circuit• About Transistor biasing
configuration• Other available transistor
biasing circuits• Stability factor for transistor• Transistor switching
INTRODUCTION• BJTs amplifier requires a knowledge of both the DC analysis (LARGE-signal) and AC analysis (small signal).
• For a DC analysis a transistor is controlled by a number of factors including the range of possible operating points.
• Once the desired DC current and voltage levels have been defined, a network must be constructed that will establish thedesired operating point.
• BJT need to be operate in active region used as amplifier.• The cutoff and saturation region used as a switches.• For the BJTs to be biased in its linear or active operating region the following must be true:
a) BE junction forward biased, 0.6 or 0.7Vb) BC junction reverse biased
INTRODUCTION(CONTINUED)
• DC bias analysis assume all capacitors are open cct.
• AC bias analysis :1) Neglecting all of DC sources2) Assume coupling capacitors are short cct. The effect of
these capacitors is to set a lower cut-off frequency for the cct.3) Inspect the cct (replace BJTs with its small signal model). 4) Solve for voltage and current transfer function and i/o and
o/p impedances.
• For transistor amplifiers the resulting DC current and voltage establish an operating point that define the region that can be employed for amplification process.
15
18
12
9
6
3
IC(mA)
VCE(V)
IB=60 uA
10 20 30
IB=50 uA
IB=0 uA
IB=40 uA
IB=30 uA
IB=20 uA
IB=10 uA
40
A
C
B
VCEsat
PCmax
ICmax
VCEmaxCutoff
Saturation
Various operating points within the limits of operation of a transistor
Q-point A:• I=0A, V=0V• Not suitable for transistor to operate
Q-point B:• The best operating pointfor linear gain and largestpossible voltage and current
• It is a desired condition fora small signal analysis
Q-point C:• Concern on nonlinearities due to I B
curves is rapidly changes in this region.
FIXED-BIAS CCT
AC inputsignal
AC outputsignal
RB
RC
B
C
EVBE
VCE+
+
-
-
C1
C2
C1,C2 = coupling capacitors
VCC
IC
IB
AC ANALYSIS DC ANALYSIS
RB
RC
B
C
EVBE
VCE+
+
-
-
VCC
IC
IB
VCC
EMITTER-STABILIZED BIAS CCT
Vi
Vo
RC
C1
C2
VCC
IC
IB
RB
Fig. 5.11 RE
IE
Voltage divider bias
Vi
Vo
RC
C1
C2
VCC
R1
Fig. 5.18: Voltage-divider bias configuration
RER2
Forward Bias of Base-Emitter• Refer to fig. 5.1. This cct also known as input loop.
RB
B
C
EVBE
VCE+
+
-
-
IB
VCC
Fig. 5.1 : Base-emitter loop
+
-
B
BECCC
BC
B
BECCB
BEBBCC
RV-V
I
:follows as rearrange
can above equ. thusII that known
R
V-VI
get, weabove eq therearrange
0V-RI-V :KVL Use
RC
C
VCE
+
-
VCC
IC
Fig. 5.2 : Collector-emitter loop
+
-
Collector-Emitter Loop• Refer to fig. 5.2. Also known as output loop.
BBE
EEBBE
CCE
EECE
CCCE
ECCC
VV
get, wethus
0V,V since ,V-VV known that Also
.VV
get, wethus
V 0V since ,V-VVc known that
RcI-VVc
0Vc-RcI-V :KVL Use
The value of IC, IB and VCE shows the position of Q-point at o/p graph. The notation of this value changes to ICQ, IBQ and VCEQ.
Example 1:Determine the following for the fixed bias configuration of Fig 5.3.a) IBQ and ICQ b) VCEQ c) VB and VC d) VBC
AC inputsignal
AC outputsignal
RC=2.2kohm
B
C
EVBE
VCE+
+
-
-
C1
C2
VCC=+12V
IC
IB
10uF
10uF
RB=240kohm
Fig. 5.3
50
Solution
biased.
reverse isjunction -BC that indicatessign ve-
6.13V83.67.0VVV)d
V 6.83VVV
V 0.7VV )c
V83.6
k2.22.35m-12
RI-VV )b
mA 34.2u08.4750II
uA08.47k240
7.012R
VVI )a
CBBC
CCEQCE
BBE
CCCCCEQ
BQCQ
B
BECCBQ
90
Example 2:Determine the following for the fixed bias configuration of Fig 5.4.a) IBQ and ICQ b) VCEQ c) VB d)VC e) VE
RC=2.7kohm
B
C
EVBE
VCE+
+
-
-
VCC=+16V
IC
IB
RB=470kohm
Fig. 5.4
Solution
V0V)e
V 8.17VVd)V
V 0.7VV )c
V17.8
k7.22.93m-16
RI-VV )b
mA 93.2u55.3290II
uA55.32k470
7.016R
VVI )a
E
CCEQCE
BBE
CCCCCEQ
BQCQ
B
BECCBQ
Transistor Saturation• Saturation means the level of systems have reached their maximum values.• For a transistor operating in the saturation region, the current is maximum value for a particular design.• Saturation region are normally avoided because the B-C junction is no longer reverse-biased and the o/p amplified signal will be distorted.• Fig 5.5 shows the schematic diagram to determine ICsat for the fixed-bias configuration.
RC
VCE=0V
+
-
VCC
ICsat
RB
Fig. 5.5
+
-VRC=VCC
The saturation current for the fixed bias configuration is:
ICsat RC
VCC
Example 3:By refering to example 1 and Fig. 5.3 determine the saturation level.
Solution:
limit. the
withinoperates is I that theconcluded becan
It .mA34.2Iin 1 example ofdesign The
mA45.5k2.2
12
R
VI
CQ
CQ
C
CCCsat
Example 4:Find the saturation current for the fixed-bias configuration of Fig. 5.4.
Solution:
limit. the
withinoperates is I that theconcluded becan
It .mA93.2Iin 2 example ofdesign The
mA92.5k7.2
16
R
VI
CQ
CQ
C
CCCsat
Load line analysis• By refering to Fig. 5.2 (output loop) one straight line can be draw at output characteristics. This line is called load line.• This line connecting each separate of Q-point.• At any point along the load line, values of IB, IC and VCE can be picked off the graph.• The process to plot the load line as follows:
Step 1: Refer to fig. 5.2, VCE=VCC – ICRC (1)Choose IC=0 mA. Subtitute into (1), we get
VCE=VCC (2) located at X axis
Step 2: Choose VCE=0V and subtitute into (1), we getIC=VCC/RC (3) located at Y-axis
Step 3: Joining two points defined by (2) + (3), we get straight line that can be drawn as Fig. 5.6.
IC(mA)
VCE(V)
Load lineVCC/RC
IC=0 mA
VCC
IBQQ-pointVCE=0 V
Fig. 5.6
IC(mA)
VCE(V)
VCC/RC
VCC
IBQ2Q-point
Fig. 5.7:Movement of Q-point with increasinglevels of IB
Q-point
Q-point
IBQ3
IBQ1
Case 1:
• Level IB changed by varying the value of RB. • Q-point moves up and down
IC(mA)
VCE(V)
VCC/RC1
VCC
IBQQ-point
Fig. 5.8 : Effect of increasing levels of RC on theload line and Q-point
Q-pointQ-point
VCC/RC2
VCC/RC3
RC3 > RC2 > RC1
Case 2:
• VCC fixed and RC change the load line will shift as shown in Fig 5.8• IB fixed, the Q-point will move as shown in the same figure.
IC(mA)
VCE(V)
VCC1/RC
VCC1
IBQQ-point
Fig. 5.9: Effect of lower values of VCC on the load line and Q-point
Q-point
Q-point
VCC2/RC
VCC3/RC
VCC2VCC3
VCC1 > VCC2 > VCC3
Case 3:
• RC fixed and VCC varied, the load line shifts as shown in Fig. 5.9
Example 5:Given the load line of Fig. 5.10 and defined Q-point, determine the required values of VCE, RC and RB for a fixed bias configuration.
15
18
12
9
6
3
IC(mA)
VCE(V)
IB=60 uA
10 20 30
IB=50 uA
IB=0 uA
IB=40 uA
IB=30 uA
IB=20 uA
IB=10 uA
40
ICmax
Fig. 5.10
Q-point
Solution:
kohm 231117
7.040I
VVR
R
V-VI
kohm 67.2m15
40
I
VR
0V.Vat R
VI
mA 0Iat V 40VV
B
BECCB
B
BECCB
C
CCC
CE
C
CCC
CCCCE
:2 Step
:1 Step
Example 6:Determine the value of Q-point for Fig. 5.11. Also find the new value of Q-point if change to 150.
RC=560ohm
B
C
EVBE
VCE+
+
-
-
VCC=+12V
IC
IB
RB=100kohm
Fig. 5.11
100
Solution:
16.95mA) V, (2.51point -Q NewV51.2
56016.95m-12
RI-V V
:4 Step
mA 16.95113150II
same, is valuetheA 113100k
0.7-12I
150, new :3 Step
mA3.11,V67.5intpoQV67.5
560m3.11-12
RI-V V
:2 Step
mA 11.3113100II
A 113100k
0.7-12I
100,
:1 Step
CCCCCE
BC
B
CCCCCE
BC
B
The change of cause the big change ofQ-point value.
This shows that fixed
biased configuration is NOT stable
The change of cause the big change ofQ-point value.
This shows that fixed
biased configuration is NOT stable
EMITTER-STABILIZED BIAS CCT• The DC bias network of Fig 5.12 contains an emitter
resistor to improve the stability level of fixed-bias configuration.
• The analysis consists of two scope:a) Examining the base-emitter loop (i/p loop)b) Use the result to investigate the collector-emitter loop
(o/p loop)
Vi
Vo
RC
C1
C2
VCC
IC
IB
RB
Fig. 5.11 RE
IE
Base-Emitter Loop (i/p loop)• Refer to fig. 5.12.
RB
B
EVBE
+
-
IB
VCC
Fig. 5.12 : Base-emitter loop
+
-
RE
IE
EB
BECCB
EBBEBBCC
BE
EEBEBBCC
R1R
V-VI
get, finally we equ, theRearrange
0RI1 - V-RI-V
get, we(1) into subtitute,I1I known that
(1) 0RI - V-RI-V :KVL
Collector-Emitter Loop (o/p loop)• Refer to fig. 5.13.
EBEBBBCCB
CCCCCECEC
ECCE
EEE
ECCCCCE
CE
EECECCCC
VVV OR RI-VV
RI-VV OR VVV
V-VV
RIV
knowcan also weFig.5.13 theFrom
)R(RI-VV
get, we(1)equ rearrange II Assuming
(1) 0RI - V-RI-V :KVL
RC
C
VCE
+
-
VCC
IC
Fig. 5.13 : Collector-emitter loop
+
-
IERE
Example 7:For the emitter-bias network fo Fig.5.14 determine:a)IB b)IC c)VCE d)VC e)VE f)VB g)VBC
RC=2 kohm
VCC=+20V
IC
IB
RB=430kohm
Fig. 5.14 RE=1 kohm
IE
50
required) as biased (reverse
V27.1398.1571.2VVV)g
V71.201.27.0VVV)f
V01.2k1m01.2RIRIV
OR
V01.297.1398.15VVV)e
V98.1502.420
k2m01.220RIVV)d
V97.13
03.620k1k2m01.220
RRI-VV c)
mA01.21.4050II b)
A1.40k1150k430
7.020
R1R
V-V I a)
CBBC
EBEB
ECEEE
CEEE
CCCCC
ECCCCCE
BC
EB
BECCB
Solution:
Improved Bias Stability Issues: Comparison analysis for example 1 and example 7.
IB(A) IC(mA) VCE(V)
50 47.08 2.35 6.83
100 47.08 4.71 1.64
IB(A) IC(mA) VCE(V)
50 40.1 2.01 13.97
100 36.3 3.63 9.11
Data from example 1 (fixed-bias configuration)
Data from example 7 (emitter-bias configuration)
Takehome exercise:For the emitter-stabilized biase cct of Fig. 5.15, determine IBQ, ICQ, VCEQ, VC, VB, VE.
RC=2.4 kohm
VCC=+20V
IC
IB
RB=510kohm
Fig. 5.15 RE=1.5 kohm
IE100
The saturation current for an emitter-bias configuration is:
RC
VCE=0V
+
-
VCC
ICsatFig. 5.16
+
-
RE
EC
CCCsat
ECCsatCC
ECsatCCsatCC
RRVI
0RRIV0RIRIV
SaturationSaturation
Example 8:Determine the saturation current for the network of example 7.
Solution:
This value is about three times the level of ICQ (2.01mA =50) for the example 7. Its indicate the parameter that been used in example 7 can be use in analysis of emitter bias network.
mA67.6k3
20
k1k2
20
RRVI
EC
CCCsat
Load line analysis• The process to plot the load line as follows:
Step 1: Refer to fig. 5.13, VCE=VCC – IC(RC+RE) (1)Choose IC=0 mA. Subtitute into (1), we get
VCE=VCC (2) located at X axisStep 2: Choose VCE=0V, subtitute into (1) gives
axis Yat located (3) RR
VI 0VVCE
EC
CCC
Step 3: Joining two points defined by (2) + (3), we get straight line that can be drawn as Fig. 5.17:
IC
VCE(V)
VCC/(RC+RE)
VCC
IBQQ-point
Fig. 5.17: Load line for the emitter-bias configuration
VCEQ
ICQ
VOLTAGE-DIVIDER BIAS
IB(A) IC(mA) VCE(V)
50 40.1 2.01 13.97
100 36.3 3.63 9.11
Data from example 7
• ICQ and VCEQ from the table of example 7 is changing dependently the changing of .• The voltage-divider bias configuration such as in Fig. 5.18 is designed to have a less dependent or independent ofthe .• If the cct parameter are properly choosen, the resulting levels of ICQ and VCEQ can be almost totally independentof .
Vi
Vo
RC
C1
C2
VCC
R1
Fig. 5.18: Voltage-divider bias configuration
RER2
• Two method for analyzed the voltage-divider bias configuration:
a) Exact methodb) Approximate method
Exact AnalysisStep 1:• The i/p side of the network of Fig. 5.18 can be redrawn as shown in Fig. 5.19 for DC analysis.
Step 2:• Analysis of Thevenin equivalent network to the left ofbase terminal
R1
RER2
Fig. 5.19: Redrawn the i/p sideof the network of Fig 5.18
Thevenin
VCC
Exact AnalysisStep 2(a):Replaced the voltage sources with short-cct equivalent as shown in Fig 5.20 and gives us the value of RTH
R1
R2 RTH
Fig. 5.20: Determining RTH
21TH RRR
Exact AnalysisStep 2(b):Determining the ETH by replaced back the voltage sources and open cct Thevenin voltage as shown in Fig. 5.21. Then apply the voltage-divider rule.
R1
R2VCC VR2
+
-
ETH
+
-
Fig. 5.21: Determining ETH
21
CC2
2RTH
RR
VRVE
Exact AnalysisStep 3:The Thevenin network is then redrawn as shown in Fig. 5.22and IBQ can be determined by KVL
RTH
RE
Fig. 5.22: Inserting theThevenin equivalent cct.
ETH IE
IB VBE
+
-0RIVRIE EEBETHBTH
gives I1βI Subtitute BE
ETH
BETHB
R1R
VEI
Example 9:Determine the DC bias voltage VCE and current IC for the voltage-divider configuration of network below:
RC=10kohm
VCC=22V
R1=39kohm
RE=1.5kohmR2=3.9kohm
140
Solution:
kohm 3.55
k9.3k39
k9.3k39
RRR 21TH
V2
k9.3k39
22k9.3
RR
VRE
21
CC2TH
A05.6k5.11140k55.3
7.02
R1R
VEI
ETH
BETHB
mA85.005.6140II BC
V22.12
k5.1k10m85.022
RRIVV ECCCCCE
Example 10: For the voltage-divider bias configuration ofFig. 5.23, determine: IBQ, ICQ, VCEQ, VC, VE and VB.
RC=3.9kohm
VCC=16V
R1=62kohm
Fig. 5.23
RE=0.68kohmR2=9.1kohm
ICQ
IBQ
80
Solution:
kohm 7.93
k1.9k62
k1.9k62
RRR 21TH
V05.2
k1.9k62
16k1.9
RR
VRE
21
CC2TH
A4.21k68.0180k93.7
7.005.2
R1R
VEI
ETH
BETHBQ
mA712.14.2180II BCQ
V16.8
k68.0k9.3m712.116
RRIVV ECCCCCEQ
V32.9k9.3m712.116
RIVV CCCCC
V18.1
k68.0m712.14.21
k68.0II
RIV
CB
EEE
V88.1
7.018.1
VVV BEEB
Approximate AnalysisStep 1:
RE 10R2 Step 2:The i/p section can be represented by the network of Fig.5.24. R1 and R2 can be considered in series by assumingI1I2 and IB= 0A .
R1
RiR2
Fig. 5.24: Partial-bias cct for calculating theapproximate base voltage, VB
VCC
I1
I2
IB
VB
+
-
Ei
212i
R1R
IIRR
Approximate AnalysisStep 3:
21
CC2R2B
RR
VRVV
:determined becan voltagebase The
BEBE
EBBE
E
V-VV
V-VV
: wellas calculated becan V level and
ECQ
E
EE II and
R
VI
:determined becan current emitter theand
R1
RiR2
Fig. 5.24: Partial-bias cct for calculating theapproximate base voltage, VB
VCC
I1
I2
IB
VB
+
-
EE RR)1(R where
10RβR
:approach eapproximat
define that willCondition
i
2E
NPN Transistor simulation
Example 11:Repeat the analysis of example 9 using the approximate technique and compare solution for ICQ andVCEQ.
Solution:
!satisfiedkohm39kohm210
k9.310k5.1140
R10R
:Step1
2E
drawn becan cct biaspartial the
:2 Step
V2
k9.3k39
22k9.3
RR
VRV
:3 Step
21
CC2B
V3.17.02
VVV BEBE
mA867.0k5.1
3.1
R
VII
E
EECQ
V03.12
k5.1k10m867.022
RRIVV ECCCCCEQ
ICQ(mA) VCEQ(V)
Exact
Analysis
0.85 12.22
Approximate Analysis
0.867 12.03
ICQ and VCEQ are certainly close.
Example 12:Repeat the exact analysis of example 9 if isreduced to 70. Compare the solution for ICQ and VCEQ.
Solution:kohm 3.55RTH
V2ETH
A81.11k5.1170k55.3
7.02
R1R
VEI
ETH
BETHB
mA83.081.1170II BC
V46.12
k5.1k10m83.022
RRIVV ECCCCCE
ICQ(mA) VCEQ(V)
140 0.85 12.22
70 0.83 12.46
Conclusion: Even though is drastically half, the level ICQ and VCEQ are essentially same.
Solution (continued):
Example 13:Determine the levels of ICQ and VCEQ for the voltage-divider configuration fo Fig. 5.25 using the exact and approximate analysis. Compare the solution.
RC=5.6kohm
VCC=18V
R1=82kohm
Fig. 5.25
RE=1.2kohmR2=22kohm
ICQ
IBQ
50
Solution:
kohm 35.71
k22k82
k22k82
RRR
:AnalysisExact
21TH
V81.3
k22k82
18k22
RR
VRE
21
CC2TH
A6.39k2.1150k35.17
7.081.3
R1R
VEI
ETH
BETHBQ
mA98.16.3950II BCQ
V54.4
k2.1k6.5m98.118
RRIVV ECCCCCEQ
satisfied)(not 220kohm60kohm
k2210k2.150
R10R
:Analysis eApproximat
2E
Solution (continued):
V81.3
k22k82
18k22
RR
VREV
21
CC2THB
V11.37.081.3
VVV BEBE
mA59.2k2.1
11.3
R
VII
E
EECQ
V88.3
k2.1k6.5m59.218
RRIVV ECCCCCEQ
Solution (continued):
ICQ(mA)
%difference
VCEQ(V) %difference
Exact Analysis
1.98
23.5%
4.54
17%Approximate Analysis
2.59 3.88
The saturation collector-emitter cct for the voltage-dividerconfiguration has the same appearance as the emitter-biased configuration as shown in Fig. 5.27
RC
VCE=0V
+
-
VCC
ICsatFig. 5.27
+
-
RE
EC
CCCsat
RRVI
Load line analysis
• The similarities with the o/p cct of the emitter-biased configuration result in the same intersections for the load line of the voltage-divider configuration.
• The load line therefore have the same appearance with:
axis Yat located RR
VI 0VVCE
EC
CCC
axis Xat located VV 0mAICCCCE
DC Bias with Voltage Biasing
Another way to improve the stability of a bias circuit is to add a feedback path from collector to base. In this bias circuit the Q-point is only slightly dependent on the transistor
Beta .
Applying Kirchoff’s voltage law: VCC – ICRC – IBRB – VBE –IERE = 0
Note: IC = IC + IB -- but usually IB << IC -- so IC IC
Knowing IC = IB and IE IC then: VCC – IB RC – IBRB – VBE –IBRE = 0
Simplifying and solving for IB: )R(RR
VVI
ECB
BECCB
Base-Emitter Loop
Collector-Emitter Loop
Applying Kirchoff’s voltage law: IE + VCE + ICRC – VCC = 0
Since IC IC and IC = IB: IC(RC + RE) + VCE – VCC =0
Solving for VCE: )( ECCCCCE RRIVV
Transistor Saturation Level
EC
CCCC
RR
VmaxIsatI
Load Line Analysis
It is the same analysis as for the voltage divider bias and the emitter-biased circuits.
Simulation of a NPN type common-emitter transistor
Design Operation• We are able to design the transistor circuit
using the ideas that we have learnt before during analyzing dc biasing circuit.
• How?– Understand the Kirchof’s Law and other electric
circuit law such as Ohms Law, Thevenin Laws etc
– Identify the parameters given– Analyze into the input/output for the system and
build a loop using electric circuit’s law.
Miscellaneous configuration
Examples
Examples
Examples of design
• Design of a bias circuit with an emitter feedback resistor
• Design of a current-gain-stabilized circuit (beta independent)
Design of a bias circuit with an emitter feedback resistor
The emitter resistor is ¼ to 1/10 of the supply voltage
Design of a current-gain-stabilized circuit (beta independent)
The emitter resistor is ¼ to 1/10 of the supply voltage
To determine R1 and R2 use 10R2≤βRE
Transistor as switching networks
• Transistor works as an inverter in computer circuits.
• Operating point switch from cut-off to saturation along the load line for proper inversion.
• In order to understand, we assume that;• IC=ICEO=0mA• VCE=Vsat=0V
• One must understand the transistor graph output and load-line analysis to describe and discuss about the transistor switching networks.
Transistor as a switch
uAmAI
ITherefore
mARVk
VI
II
CsatB
C
cc
IB
CsatB
8.481251.6
,
1.6I
63uA 68
7.0
that, see ll we'figure, the withcompare
that ensure must We
Csat
Time interval
Time interval continued
Troubleshooting?
• How to define and encounter transistor circuit problem?
PNP configuration
Bias stabilization
• Stability of a system is a measure of the sensitivity of a network to variation in its parameter.– β increases with increase in temperature
– VBE decreases 7.5mV every degree celcius
– ICO doubles every 10 oC increase in temperature
Effect of non-stability circuit/system
Room temperature 100oC temperature
We’ll find thatWe’ll find that β increase after 100OC, base current is same but not suitable to use due it is very near to the saturation region.
Stability factors
• Emitter bias configuration
C
BE
CBE
CO
CCO
IS
VI
VS
II
IS
)(
)(
)(
E
BCO
E
B
CO
E
B
CO
E
B
E
B
E
B
CO
RRIS
RR
IS
RR
IS
RR
RR
RR
IS
)(, be willfactor
stability 1, to 1 from of ranges For
1)(
to reduce willit ),1( If
)1()(
to reduce willit ),1( If
)()1(
)(1)1()(
S(ICO)
• Fixed bias configuration
value maximum the reach and stable not sit' so)....1()(
obtain, ll we'0R assume andr,denumerato and
numerator the forR withequation above gmultiplyin If
)()1(
)(1)1()(
E
E
CO
E
B
E
B
CO
IS
RR
RR
IS
• Voltage divider bias configuration
rule. Thevenin using
analyze because only differs but stic,characteri
ionconfigurat bias-emitter the to same is This
)()1(
)(1)1()(
E
Th
E
Th
CO
RR
RR
IS
S(ICO)
• Feedback bias configuration
0 Where
)()1(
)(1)1()(
E
C
B
C
B
CO
R
RR
RR
IS
S(ICO)
• Physical impactFixed bias configuration ; IC=βIB+(β+1)ICO...IC increase but IB maintain, so it’s not stable
Emitter bias configuration ; Increase IC will increase ICO. It affect VE since VE=IERE=ICRE. In turn, the output loop will inform that IB will decrease if VE is increase, thus affect to reduce the collector current.
Feedback bias configuration ; same as result of emitter bias configuration where IB will decrease if IC increase. (IC proportional to VRC)
Voltage divider bias configuration ; Most stable where as long as 10R2>> βRE, VB remain constant for any changing in IC.
S(VBE)
)1 if(......1
)1(
or
)0R if(......
)1(
)(
E
E
B
E
E
B
E
B
EB
BE
CBE
RR
R
RR
R
R
RR
VI
VS
S(β)
)1(
)1(
)(
21E
B
E
BC
C
C
RRRR
II
IS
References:
1. Thomas L. Floyd, “ Electronic Devices, Sixth edition”, Prentice Hall, 2002.
2. Robert Boylestad, “Electronic Devices and Circuit Theory”, Eighth edition, Prentice Hall, 2002.
3. Puspa Inayat Khalid, Rubita Sudirman, Siti Hawa Ruslan, “ModulPengajaran Elektronik 1”, UTM, 2002.
4. Website : http://www2.eng.tu.ac.th