chapter 3 (part 2)
DESCRIPTION
Chapter 3 (part 2). Basic Logic Gates. 1. 3-7 The Inverter. Used to complement (invert) a digital signal When A = 1, X = 0 When A = 0, X = 1 Timing analysis. Truth table and Boolean equations for the Inverter. Truth Table. Boolean Equation: X = A Inversion bar - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/1.jpg)
Chapter 3 (part 2)
Basic Logic Gates
11
![Page 2: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/2.jpg)
3-7 The Inverter
• Used to complement (invert) a digital signal– When A = 1, X = 0
– When A = 0, X = 1
• Timing analysis
2
![Page 3: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/3.jpg)
Truth table and Boolean equations for the Inverter
• Truth Table • Boolean Equation:
X = A• Inversion bar
– Used to signify the complement
• Inverter is also called as NOT gate
3
![Page 4: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/4.jpg)
3-8 The NAND Gate
• Same as the AND gate except that its output is inverted– If A = 1 and B = 1, X = 0
– If A = 0 or B = 0, A = 1
4
![Page 5: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/5.jpg)
I/O of a 7400 quad NAND IC
5
![Page 6: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/6.jpg)
Truth table and Boolean equations for the NAND Gate
• Boolean Equation: X = AB
• Multiple inputs - the output is always HIGH unless all inputs go HIGH
6
![Page 7: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/7.jpg)
Symbols for three- and eight-input NAND gates
7
![Page 8: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/8.jpg)
8
![Page 9: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/9.jpg)
9
![Page 10: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/10.jpg)
10
![Page 11: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/11.jpg)
3-9 The NOR Gate
• Same as the OR gate except that its output is inverted– If A = 1 or B = 1, X = 0
– If A = 0 and B = 0, X = 1
11
![Page 12: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/12.jpg)
I/O of a 7402 quad NOR IC
12
![Page 13: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/13.jpg)
Truth Table and Boolean equation for The NOR Gate
• Truth Table• Boolean Equation: X = A + B
13
![Page 14: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/14.jpg)
14
![Page 15: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/15.jpg)
15
![Page 16: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/16.jpg)
16
![Page 17: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/17.jpg)
3-10 Logic Gate Waveform Generation
A popular generalPurpose Repetitive waveform generator
17
![Page 18: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/18.jpg)
Figure 3.44 Generating a 3-ms HIGH pulse using an AND gate and a Johnson shift counter.
18
![Page 19: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/19.jpg)
Example 3-13 Which Johnson counter outputs will you connect to an AND gate to get a 1ms HIGH-level output from 4 to 5ms?
19
![Page 20: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/20.jpg)
Example 3-14 Which Johnson counter outputs must be connect to a three-input AND gate to enable just the Cp#4 pulse only to be output?
20
![Page 21: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/21.jpg)
Example 3-15 Sketch the output waveform resulting from inputting the Johnson counter outputs shown:
21
![Page 22: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/22.jpg)
22
![Page 23: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/23.jpg)
23
![Page 24: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/24.jpg)
24
![Page 25: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/25.jpg)
25
![Page 26: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/26.jpg)
Figure 3.60 7404 TTL and 4049 CMOS inverter pin configurations.
26
![Page 27: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/27.jpg)
Figure 3.61 (a) 7402 TTL NOR and 4001 CMOS NOR pin configurations; (b) 7400 TTL NAND and 4011 CMOS NAND pin configurations.
27
![Page 28: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/28.jpg)
28
![Page 29: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/29.jpg)
3-12 IEEE/IEC Standard Logic Symbols
29
![Page 30: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/30.jpg)
30
![Page 31: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/31.jpg)
Summary
• The AND gate requires that all inputs are HIGH in order to get a HIGH output.
• The OR gate outputs a HIGH if any of its inputs are HIGH.
• An effective way to measure the precise timing relationships of digital waveforms is with an oscilloscope or a logic analyzer.
31
![Page 32: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/32.jpg)
Summary
• Beside providing the basic logic functions, AND and OR gates can also be used to enable or disable a signal to pass from one point to another.
• There are several integrated circuits available in both TTL and CMOS that provide the basic logic functions.
32
![Page 33: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/33.jpg)
Summary
• Two important troubleshooting tools are the logic pulser and the logic probe. The pulser is used to inject pulses into a circuit under test. The probe reads the level at a point in a circuit to determine is it is HIGH, LOW, or floating.
• An inverter provides an output that is the complement of its input.
33
![Page 34: Chapter 3 (part 2)](https://reader035.vdocuments.site/reader035/viewer/2022062221/56814953550346895db6a380/html5/thumbnails/34.jpg)
Summary
• A NAND gate outputs a LOW when all of its inputs are HIGH.
• A NOR gate outputs a HIGH when all of its inputs are LOW.
• Specialized waveforms can be created by using a repetitive waveform generator and the basic gates.
4034