chapter 3 fabrication of accelerometer -...
TRANSCRIPT
57
Chapter 3
Fabrication of Accelerometer
3.1 Introduction
There are basically two approaches for bulk micromachining of
silicon, wet and dry. Wet bulk micromachining is usually carried out
using anisotropic etchants like KOH (Potassium Hydroxide), TMAH (Tetra
Methyl Ammonium Hydroxide) and EDP (Ethylene Diamine Pyrocatecol).
Dry micromachining of silicon is done using Flourine based plasma
chemistry. For the fabrication of accelerometer, the wet bulk
micromachining approach is selected because of two major reasons (1)
proof-mass and beams are having different thicknesses (2) beams need to
be centralized w.r.t the proof-mass. Another critical process developed
here is controlled wet oxidation and precisely controlled patterning of
silicon dioxide using BHF (Buffered Hydro Fluoric acid). Silicon dioxide
is used as a mask for etching in KOH.
3.2 Wet bulk micromachining
Anisotropic chemical wet etching is a key technology in fabricating
Micro Electro Mechanical Systems (MEMS). A substantial amount of
research has been conducted to understand the mechanism and
58
eventually control the etched shape. Seidel et al. [40] Seidel [41] and
Glembocki et al. [42] and Palik et al. [43] modeled the etching process
and investigated the etching properties under a variety of KOH etching
conditions.
3.2.1 Theory
Single-crystal silicon has a diamond lattice structure as shown in
fig 3.1.
Fig 3.1 Silicon crystal structure
Each silicon atom has four covalent bonds. Each bond connects a
different pair of atoms. Silicon, with its four covalent bonds, coordinates
itself tetrahedrally, and these tetrahedrons make up the diamond-cubic
structure. This structure can also be represented as two
interpenetrating Face-Centered Cubic (FCC) lattices, one displaced w.r.t
the other. The lattice parameter „a‟ for Silicon is 5.4309 A and Silicon‟s
diamond-cubic lattice has a packing density of 34%, compared to 74%
for a regular FCC lattice. The {111} planes present the highest packing
59
density and the atoms are oriented such that three bonds are below the
plane.
When an atom is located on a surface, the bond belonging to the
atom loses a neighboring atom. It is known as a dangling bond. The
dangling bonds easily react with the etching agent. Though, in many
cases, the dangling bonds do not remain free-ended, that is, the surface
bonds are reconstructed by combining with each other in high vacuum,
or the bonds are terminated with hydrogen atom in water, those bonds
on the surface are still a source of surface reactions, i.e., etching. When
the number of dangling bonds on three differently oriented surfaces,
(100), (110), and (111) are compared, it is apparent that the (111) surface
has the smallest number of bonds. There is only one dangling bond per
surface atom for (111), whereas there are two for (100), and one dangling
bond plus two surface bonds for (110). This is a conventional
explanation for why (111) is stable against etching. Experimentally it is
found that in pure KOH solutions, {110} planes exhibit highest etching
rate. According Seidal et al, [10] the back bonds and the energy levels of
the associated surface states is not necessarily the same for {110} and
{111} planes, as that energy will also be influenced by the effect of the
orientation of these bonds. Another argument in favor of high etching
rates of {110} planes is the easier penetrability of {110} surfaces for water
molecules along the channels in that plane [46].
60
3.2.2 Etching solutions
Solutions showing orientation dependence on the etch rate of
silicon are KOH, TMAH, EDP (Ethylenediamine and Pyrocatecol), N2H4
(hydrazine) and NaOH. All are used as water solutions. The chemical
reaction for any of these etching solutions is described as follows:
𝑆𝑖 + 2𝑂𝐻− + 2𝐻2𝑂 𝑆𝑖𝑂2(𝑂𝐻)22− + 2𝐻2
Silicon reacts with water and an OH- ion and produces hydroxide ion and
hydrogen gas bubbles. Etching masks are usually made of either SiO2 or
Si3N4.
KOH shows strong anisotropy, and shows large values of etch rate
ratios among orientations of about (100). It means that high
controllability can be expected in etched profiles, while suppressing
mask undercut. KOH solutions are less toxic than other etchants, hence
are easy to process. These are the main reasons why KOH is widely used
for fabricating silicon microstructures in industry.
A drawback with KOH is that, it etches SiO2 mask also
significantly during long etching time. Selectivity of Si to SiO2 mask is
about 150 under normal conditions. Another drawback is that KOH
etching is incompatible to IC processes because contamination with
potassium ion is strictly prohibited in IC processes.
61
3.2.3 Etching shapes
Etching shapes are categorized into two, one is concave-etched
profiles and the other is convex etched profile. Concave-etched profiles
on silicon wafers have been fabricated so far for applications in pressure
sensors and ink-jet printer head structures. In the case of concave
profiles, orientations having an etch rate that is locally minimum appear
and Si (111) is the only orientation that has an etch rate of a local
minimum for any etching conditions.
Incase of convex profiles, orientations having an etch rate that is
locally maximum appear. It becomes far more difficult to predict and to
control etch profiles having large etch rates. Again, characterization of
anisotropy in etch rate is of great importance. The planes occurring at
convex corners during anisotropic etching of (100) silicon in aqueous
KOH were identified as {411} planes [40]. The etching rate of these
planes in relation to the rate of the {100} planes declines with increasing
Potassium Hydroxide concentration. In contrast, the temperature
dependence of this etch rate ratio is negligible in the relevant range
between 60°C and 100°C.
3.2.4 Silicon dioxide as masking material
In the case of KOH etching, the etch rate of SiO2 is not negligible,
even if it is a thermally grown oxide. With 40% KOH solution at a
temperature of 60°C, it is experimentally verified that etching rate of SiO2
62
is about 80 nm/hr. Growth of thin Oxide films (<1 µm) and multiple
oxidation steps are incorporated into the process to improve the quality
of oxide and also to reduce the pinhole density. The disadvantage of
higher etch rate of SiO2 when compared to other masking materials like
Si3N4, is converted into an advantage in the process for fabrication of
accelerometer structure by in-situ removal of oxide mask of required
thickness during silicon etching itself. Other advantages of using SiO2
as mask are easy to grow by thermal oxidation and easy to remove using
HF-based solutions.
3.2.5 Corner undercutting and compensation
When etching rectangular corners, deformation of the edges
occurs due to under cutting. This is an unwanted effect especially in the
fabrication of acceleration sensors where total symmetry and perfect 90o
convex corners on the proof-mass are mandatory for good device
prediction and specification. The undercutting is a function of etch time
and thus directly related to the desired etch depth. An undercut ratio is
defined as the ratio of undercut to etch depth.
Saturating KOH solutions with isopropanol (IPA) reduces the
convex corner undercutting. Unfortunately, this happens at the cost of
the anisotropy of the etchant. Undercutting can also be reduced or even
prevented by corner compensation structures which are added to the
corners in the mask layout. Depending on the etching solutions,
63
different corner compensation schemes are used. Commonly used
techniques are square compensation (EDP or KOH) and rotated
rectangle corner compensation methods (KOH) [46]. The second method
for corner compensation technique is used in this case.
In the rotated rectangular corner compensation method, a
properly scaled rectangle (Breadth „B‟ should be twice the etch depth „De‟)
is added to each of the mask corners. The four sides of the mesa square
(proof-mass) are still aligned along the <110> directions, but the
compensation rectangles are rotated 45o with their longer sides along the
<100> directions. The rectangular bar along <100> direction is undercut
by KOH along three preferential directions, namely <100> sidewalls,
<410> sidewalls and <410> of the free end [44]. When the length of the
<100> bar is kept at 1.6 B (for 33% KOH), the undercut of the latter two
directions should stop first, and only the lateral (100) sidewalls etching
determines the final undercut. Thus, the etching rate is the same as
that of the (100) etching along with the depth, so if the width of the bar is
twice the etching depth, complete convex corners can be obtained.
Here, etch depth De = 172 µm is used, as etching takes place from
both sides of the wafer (344 µm thick). Width of the rotated rectangle is
B = 344 µm and Length L= 1.5 x 344 = 516 µm. The factor 1.5 comes
from the fact that 40% KOH is used. This is explained further in section
3.3.2. But here, in the last KOH etching step, the mask above the proof-
64
mass is also removed for bringing down the proof-mass thickness to 300
µm. Therefore, the effective depth for which the corner compensation
mask was retained is only ((344 - 44)/2 = 150 µm). Taking this into
account, the new values are B = 300 µm and L = 450 µm. Considering
process alignment tolerances, the final values are finalized as B = 310
µm and L = 460 µm as shown in fig 3.2.
Fig 3.2 Corner compensation of the proof-mass
(LHS – full view and RHS – Zoomed view)
3.3 Simulations in Intellisuite
AnisE, an anisotropic etch process simulation tool from
Intellisuite software is used for anisotropic etching simulation. The input
to this is a two dimensional mask and the output is the three
dimensional etched structure. The mask used looks as shown in fig. 3.3.
65
Fig 3.3 Mask without corner compensation
The mask shown is used for etching the (100) plane of silicon wafer with
40% KOH concentration, at temperature 60oC.
Fig 3.4 Structure after etch simulation
After etching, the silicon structure is as shown in fig.3.4. The
structure consists of a proof -mass and four beams whose thickness is
same as that of the proof-mass. The beams are attached to a frame of
thickness 300 microns. It is apparent from the figure that the corners of
the proof-mass and the beams are etched off. The deformation of the
edges occurs due to undercutting and this necessitates the use of
compensation structures.
66
3.3.1 Dimensions of corner compensation structure
The experiments of Mayer et al showed that the undercutting of
convex corners in pure KOH etches are determined exclusively by {411}
planes. At the wafer surface, the sectional line of {411} and a {111} plane
points in the <410> direction, forming an angle of 30.96o with the <110>
direction. From literature [44], it is clear that for a rotated rectangle
compensation structure, the width „B‟ should be equal to twice the etch
depth if etching is done from only one side. Meanwhile, the necessary
length of the compensation bar depends on its width, hence the etching
depth as well as the ratio of etching rates of <410> and <100> [45]. The
length of the rectangle is given by L = 1.6 B for 33% KOH [44]. This is
verified using Anis-E module of Intellisuite. Here one of the corners of the
proof-mass is covered with compensation rectangle structure. The
structures after etching are shown in fig 3.5. For 40% KOH solution, the
length is even shorter and can fairly approximated as L = 1.5 B taking in
to account of the fact that the lateral etching (Etch rate along <410> /
Etch rate along <100>) decreases with increase in concentration of KOH
[44].
67
L = B L = 1.2 B
L = 1.4 B L = 1.6 B
Fig 3.5 Proof-mass structures showing effect of length
variation of compensation mask (33% KOH)
3.3.2 Centralization of beams with respect to proof-mass
To realize the beams at the center of the proof-mass, a technique
known as self aligned etching is used. The anisotropic etching of KOH
68
takes place in three phases. In the first phase, the silicon wafer is etched
for 55µm by masking the proof-mass and beam areas. In the second
phase of etching silicon, the beams are unmasked and the structure is
realized with the proof-mass of whole wafer thickness and the beams are
centralized with a thickness of 99 µm. In the final phase of etching
(44µm), the oxide over the proof-mass is also removed and the complete
structure is realized with a proof-mass thickness of 300 µm and beam
thickness of 55µm. The etched structure looks as shown in fig 3.6 (a)
and (b).
Fig 3.6(a) Etch simulation
result after first phase etching
Fig 3.6(b) Etch simulation
result after final phase etching
69
3.4 Process flow for fabrication
3.4.1 Silicon wafer processing for microstructure
fabrication
1. (100) Oriented P-type silicon wafer 344 5 µm Thick, Resistivity
of 0.1-cm
The processed wafer thickness measured is 344 µm.
2. Wet thermal oxidation for a final oxide thickness of 1.1µm
Silicon
SiO2
70
3. Pattern oxide in the contact area. Oxide is etched using BHF to depth
of 0.2µm.(Mask1)
Photoresist
MASK 1
The etch rate of silicon dioxide in BHF is 0.1µm / min. The above step is
required since in the final step, a bulk BHF etching of oxide is to be
carried out to open the contact area and also to reduce the oxide
thickness in the frame area to 0.15µm-0.2µm. This step also has the
added advantage of providing better aligning of the subsequent masks as
the contact pad area lies at a fixed distance from the proof-mass – beam
area.
71
4. Oxide patterning with BHF in mass-beam area (Mask – 2)
MASK 2
5. Wet thermal oxidation in the mass-beam area for a thickness of
0.75µm
72
6. Oxide etching using BHF in the beam area (Mask 3)
MASK 3
7. Wet thermal oxidation in the beam area for a thickness of 0.15µm
73
8. Oxide etching using BHF in the through etching area (Mask 4)
MASK 4
9. First Phase KOH etching from both sides
KOH concentration : 40%
Temperature : 60oC
Etch depth from one side : 27.5 µm
Total Silicon thickness removed
from through etching area : 55 µ
Etch rate : 44 µm / hr
Time of etch : 37.5 mins
74
Masking material (SiO2) etch rate : 0.08 µm / hr
Thickness of oxide removed from beam area : 0.05 µm
Thickness of oxide remaining in beam area : 0.1 µm
10. Oxide etching using BHF in the beam area
Etch rate of oxide in BHF : 0.1 µm /min
Time of etch : 1 min
75
11. Second phase KOH etching from both sides
KOH concentration : 40%
Temperature : 60oC
Etch depth from one side : 122.5 µm
Total silicon thickness removed
from through etching area : 300 µm
Total silicon thickness removed
from beam area : 245 µm
Etch rate : 44 µm / hr
Time of etch : 167 mins
`
76
Masking material (SiO2) Etch rate : 0.08 µm / hr
Thickness of oxide removed from proof-mass area : 0.25 µm
Thickness of oxide remaining in proof-mass area : 0.5 µm
12. Oxide etching using BHF in the proof-mass area
Etch rate of Oxide in BHF : 0.1 µm /min
Time of etch : 5.0 min
13. Third and final phase KOH etching from both sides
KOH concentration : 40%
Temperature : 60oC
Etch depth from one side : 22 µm
Total silicon thickness removed
from through etching area : 344 µm
77
Total silicon thickness removed
from beam area : 289 µm
Beam width achieved : 344 – 289 = 55 µm
Proof-mass thickness achieved : 344 – 44 = 300 µm
Etch rate : 44 µm / hr
Time of etch : 30 mins
Masking material (SiO2) etch rate : 0.08 µm / hr
Thickness of oxide removed from contact area : 0.04 µm
Thickness of oxide remaining in contact area : 0.86 µm
14. Oxide etching using BHF in the contact area
Etch rate of Oxide in BHF : 0.1 µm /min
Time of etch : 8.6 min
78
Maximum Oxide thickness left in the frame area: 0.2µm (Refer Table 3.1)
15. Evaporate 1500 Ao Al for contact pad (Mask 5)
MASK-5
Al
79
Area
Maximum Thickness of Silicon dioxide (in microns)
remaining after
Oxidation 1st
Phase
KOH Etch
1st
Phase
BHF dip
2nd
Phase
KOH Etch
2nd
Phase
BHF dip
3rd
Phase
KOH Etch
3rd
Phase
BHF dip
Beam 0.15 0.1 0 - - - -
Proof-mass
0.9 0.85 0.75 0.5 0 - -
Contact 1.8 1.75 1.65 1.4 0.9 0.86 0
Frame 2.0 1.95 1.85 1.6 1.1 1.06 0.2
Table 3. 1 Thickness of Silicon dioxide in different regions at different stages of etching
Fig 3.7 Top view of the processed silicon die
80
3.4.2 Top glass wafer processing
1. 100 mm Pyrex 7740 Glass wafer with a thickness of 500µm
2. Evaporate 1500 A0 Al, on one side of the wafer
3. Pattern Al using Mask 6
Glass
Al
81
4. Pre dicing trenches are formed in top glass wafer with depth and
width of 100 µm.
3.4.3 Bottom glass wafer processing
MASK –6
1. 100 mm Pyrex 7740 Glass wafer with a thickness of 500µ
Glass
82
2. Evaporate 1500 Ao Al, on one side of the wafer
3. Pattern Al using Mask 7
4. Wafer edge is also diced for placing electrode on Silicon during top
glass anodic bonding process
5. The three separately processed wafers are anodically bonded together
and diced using mechanical dicing equipment. The exploded view of
Al
MASK –7
83
the diced chip is shown in fig 3.8. The total size of the chip is
9 mm x 8 mm x 1.344 mm
Fig 3.8 Exploded view & assembled view of the accelerometer chip
3.5 Results and discussion
Fig 3.9 shows the Scanning Electron Microscope (SEM) picture of
the proof-mass cross-section. The designed dimensions of the proof-
mass with rectangular cross-section were 2500 µm x 2500 µm x 300 µm.
Due to anisotropic etching, the fabricated proof-mass has hexagonal
cross - section and the dimensions achieved are 2458 µm x 2458 µm x
300 µm. This is fairly good result taking into account the complexity of
fabrication.
Fig 3.10 shows the SEM picture of the beam cross-section. The
designed dimensions of the rectangular cross section of beam were
150 µm x 55 µm and the achieved dimensions are 176 µm x 49 µm.
Here, the thickness of beam is reduced by 6 µm, and width increased by
26 µm, so the moment of inertia of beam reduces by 0.83
84
times compared to the designed rectangular cross-section beam. This is
expected to cause 20% increased deflection & sensitivity.
Fig 3.9 SEM picture of the proof-mass and beam
Fig 3.10 SEM picture of the beam cross section
85
Fig 3.11 Sharp corners realized on proof-mass and L-beams
Fig 3.12 Photograph of the diced sensor chip in its final form
Fig 3.11 shows the clean and sharp corners realized on the corners of the
proof-mass and on L-beams. This validates the corner compensation
design technique used in the thesis. Fig 3.12 shows the diced chip in its
final form. As shown here the top glass is diced in such a way that all the
electrical pads are accessible for further wire bonding.