Chapter 3 - Digital Logic Level• Gates• Basic Digital Logic• Memory

– Storage Hierarchy• CPU

– PII– PicoJava

• Bus– PCI

• Homework:– Chapter 3 # 1, 4, 6, 12, 25, 35, 37, 40 (Due 4/22)

Gates and Boolean Algebra

• X = !A;

Functions _ _ _ M=ABC+ABC+ABC+ABC

M =(!A) && B && C || A &&(!B)&& C || A && B &&(!C) || A && B && C

Completeness of NAND and NOR

Equivalence and Minimization

• XX+YY = X+Y

Identities for formula transform

Transforming formulas

0-60 in 4.2 sec.

Memory

• SR Latch

Clocked latches

• Clocked SR latch

• Clocked D latch

Clocking

D Flip-Flop

4 x 3 (3?)

Simple Bus

Dynamic RAM

CPU chip I

Buses Everywhere!

Bus overview

• P IV (.013 micron)– 36 addr lines– 64 data lines– MANY control lines

Synchronous bus overview

Bus arbitration

P II cpu bus

• 33 ADDR• 64 Data• Bus pipeline

– Arbitration– Request– Error– Snoop– Response– Data

PicoJava

• Built-in ram/PROM bus• Built-in PCI bus support• 16 Built-in I/O lines

A real bus - PCI

PCI - more