chapter #10: finite state machine implementation

10-1

Introduction

Chapter #10: Finite State Machine Implementation

10-2

IntroductionChapter Outline

• FSM Design with Programmable Logic

• FSM Design with Counters

• FSM Design with More Sophisticated Logic Devices

10-3

IntroductionImplementation Strategies

• Discrete Gate Logic

Emphasis so far

• MSI Logic (e.g., Counters)

• Structured Logic (e.g., PLA/PAL, ROM)

• Field Programmable Gate Arrays (FPGAs)

Function can be configured "on the fly" or in the field

Flipflops/Registers plus discrete gates on the same chip

10-4

IntroductionFSM Design with Programmable LogicMapping a State Machine into a ROM Implementation

Block Diagram forSynchronous Mealy Machine

Block Diagram forSynchronous Mealy Machine

ROM-based RealizationROM-based Realization

• Inputs & Current State form the address

• ROM data bits form the Outputs & Next State

Combinational Logic Registers

OutputsOutput Function

Next State Function

Inputs

ROM Registers

OutputsInputsA0

An-1

An

An+m-1 Dk+m-1

D0

Dk-1

Dk

State

State

10-5

IntroductionFSM Design with Programmable Logic

Effect of Design Process

Using programmable logic for FSM- consider state assignment, choice of flip-flops, and state machine partioning- complex when mapping a design onto programmable logic

Use partitioning strategies to map state machine onto as few components as possible

Use D flip-flops or MSI registers for the state- programmable logic component’s outputs are limited

The kind of ROM is the same regardless of the state assignment

PLA/PAL requires a good state assignment to keep manageable the number of terms to implement the next state and output logic

10-6

IntroductionFSM Design with Programmable LogicROM-based Design

Example: BCD to Excess 3 Serial Converter

BCD Excess 3 Code 0000 0011 0001 0100 0010 0101 0011 0110 0100 0111 0101 1000 0110 1001 0111 1010 1000 1011 1001 1100

Conversion Process

Bits are presented in bit serial fashionstarting with the least significant bit

Single input X, single output Z

10-7

IntroductionFSM Design with Programmable LogicBCD to Excess-3 Converter

State Transition Table

Derived State Diagram

Present State S0 S1 S2 S3 S4 S5 S6

Next State OutputX=0 S1 S3 S4 S5 S5 S0 S0

X=1 S2 S4 S4 S5 S6 S0 --

X=0 1 1 0 0 1 0 1

X=1 0 0 1 1 0 1 --

Reset

S00/1 1/0

S1

0/11/0 S2

0/0, 1/1

S30/0, 1/1

S4

1/00/1

S50/0, 1/1

S6

0/1

10-8

IntroductionFSM Design with Programmable LogicBCD to Excess 3 Converter

ROM-based Implementation

Truth Table/ROM I/Os

In ROM-based designs, no need to consider state assignment

X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

D2 0 0 1 1 1 0 0 X 0 1 1 1 1 0 X X

Z 1 1 0 0 1 0 1 X 0 0 1 1 0 1 X X

D1 0 1 0 0 0 0 0 X 1 0 0 0 1 0 X X

D0 1 1 0 1 1 0 0 X 0 0 0 1 0 0 X X

ROM Address ROM Outputs

Z

Circuit Level Realization74175 = 4 x positive edge triggered D FFs

QA QA

QB QB

QC QC

QD QD

CLK

CLR1

converter ROMX Q2 Q1 Q0

Z D2 D1 D0

15 14

10 11

7 6

2 3

D CB A

CLK

13 12

10 \Reset

X10

175

1

9

5 4

10-9

IntroductionFSM Design with Programmable LogicBCD to Excess-3 Converter

Timing Behavior for input strings 0 0 0 0 (0) and 1 1 1 0 (7)

0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1

LSB MSB

LSB LSB

0 0 0 0

1 1 0 0

1 1 1 0

0 1 0 1

10-10


PLA-based Design

State Assignment with NOVA

S0 = 000S1 = 001S2 = 011S3 = 110S4 = 100S5 = 111S6 = 101

NOVA derived state assignment

9 product termimplementation

0 S0 S1 11 S0 S2 00 S1 S3 11 S1 S4 00 S2 S4 01 S2 S4 10 S3 S5 01 S3 S5 10 S4 S5 11 S4 S6 00 S5 S0 01 S5 S0 10 S6 S0 1

NOVA input file

10-11


Espresso Inputs

Espresso Outputs

.i 4

.o 4

.ilb x q2 q1 q0

.ob d2 d1 d0 z

.p 16 0 000 001 11 000 011 00 001 110 11 001 100 00 011 100 01 011 100 10 110 111 01 110 111 10 100 111 11 100 101 00 111 000 01 111 000 10 101 000 11 101 --- -0 010 --- -1 010 --- -.e

.i 4

.o 4

.ilb x q2 q1 q0

.ob d2 d1 d0 z

.p 90001 010010-0 010001-0 01001-1- 0001-0-1 10000-0- 0001-1-0 1000--10 0100---0 0010.e

10-12


D2 = Q2 • Q0 + Q2 • Q0

D1 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0

D0 = Q0

Z = X • Q1 + X • Q1

175X Q2 Q1 Q0

Z D2 D1 D0

converter PLA10

CLK

10

1

\Reset

CLK

13 12

X D C B A

QD QD

QC QCQB QB

QA QACLR

9

1

15 14

10 117 6

2 3

Z

5 4

10-13

IntroductionFSM Design with Programmable LogicBCD to Excess 3 Serial Converter

10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate

D1 = D11 + D12

D11 = X • Q2 • Q1 • Q0 + X • Q2 • Q0

D12 = X • Q2 • Q0 + Q1 • Q0

0. Q2 • Q01. Q2 • Q08. X • Q2 • Q1 • Q09. X • Q2 • Q016. X • Q2 • Q017. Q1 • Q024. D1125. D1232. Q033. not used40. X • Q141. X • Q1

X

Q2

Q1

Q0

D11

D12

D2

D11

D12

D1

D0

Z

0 1 2 3 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31

0 1

8 9

16 17

24 25

32 33

40 41

10-14

IntroductionFSM Design with Programmable LogicBCD to Excess 3 Serial Converter

X

Q2

Q1

Q0

D11

D12

D2

D11

D12

D1

D0

Z

0 1 2 3 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31

0 1

8 9

16 17

24 25

32 33

40 41

PAL10H8

X Q2 Q1 Q0

D2

D1

D0

Z

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

1211

AND Gate Array

10-15


More Advanced PAL Architectures

Registered PAL Architecture

Programmable AND array device with on-chip flip-flops associated with

output pins

Useful for implementing synchronous Mealy machines or Moore machines

Positive edge-triggered D flip-flops latch the OR plane outputs

These are gated to the output pins through tri-state inverting buffers

when the OE signal is asserted low

10-16

IntroductionFSM Design with Programmable LogicMore Advanced PAL Architectures

Registered PAL ArchitectureBuffered Input

or product term

Negative LogicFeedbackD2 = Q2 • Q0 + Q2 • Q0

D1 = X • Q2 • Q1 • Q0 + X • Q2 + X • Q0 + Q2 • Q0 + Q1 • Q0

D0 = Q0

Z = X • Q1 + X • Q1

CLK OE

D2 Q2+

Q2+

Q2 Q2 Q0 Q0

X

D Q

Q

Q2 • Q0

Q2 • Q0

Q2 • Q0 + Q2 • Q0

Q2 • Q0 + Q2 • Q0

Q2+

10-17

IntroductionFSM Design with Programmable LogicMore Advanced PAL Architectures

PLA with Programmable Outputs

Buried Registers: decouple FF from the output pin

CLK OE

D Q

Q

- One of XOR’s inputs can be programmed with a connection to ground- Programmable polarity can help you overcome the limited product term inputs to the OR gate- The complement of function in sum of product form may use fewer terms

10-18

Introduction

A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D

A B C D A B A B

C D C D

A B C D

Advantage of XOR PALs: Parity and Arithmetic Operations

FSM Design with Programmable LogicAdvanced PAL Architectures

XOR PALs

Contain internal XOR gates whose inputs are fed from AND-OR array structures

Well suited for computing certain arithmetic functions that would generate many product terms

10-19


1

040

80120

23D Q

Q

2

160200

240280

22D Q

Q

3

320360

400440

21D Q

Q

4

480520

560600

20D Q

Q

5

640680

720760

19D Q

Q

6

800840

880920

18D Q

Q

7

9601000

10401080

17D Q

Q

8

11201160

12001240

16D Q

Q

9

12801320

13601400

15D Q

Q

10

14401480

15201560

14D Q

Q

11 13

0 4 8 12 16 20 24 28 32 36

0 4 8 12 16 20 24 28 32 36

NOTE: FUSE NUMBER = FIRST FUSE NUMBER + INCREMENT

INCREMENT

FIRST FUSE

NUMBER

INCREMENT

Example of XOR PAL

1

11

0 4 8 12 16 20 24 28

INCREMENT

0

19

2

326496

128160192224

256

18

3

288320352384416448480

D Q

Q

512

17

4

544576608640672704736

D Q

Q

768

16

5

800832864896928960992

D Q

Q

1024

15

6

1056108811201152118412161248

D Q

Q

1280

14

7

1312134413761408144014721504

D Q

Q

1536

13

8

1568160016321664169617281760

D Q

Q

1792

12

9

1824185618881920195219842016

FIRST FUSE NUMBERS

Example of Registered PAL

10-20


Typical registered PALs have several limitations

An output pin is dedicated to the register even if it is used to hold stateinformation that is never provided off-chip

- To have buried registers with outputs decoupled from the registers Output pin carries a different signal

- The outputs may be multiplexed allowing the output pin to be connected to the combinational output from the array or the registered from the flip-flop

10-21

IntroductionFSM Design with Programmable LogicSpecifying PALs with ABEL

module bcd2excess3title 'BCD to Excess 3 Code Converter State Machine'u1 device 'p10h8';

"Input Pins X,Q2,Q1,Q0,D11i,D12i pin 1,2,3,4,5,6; "Output Pins D2,D11o,D12o,D1,D0,Z pin 19,18,17,16,15,14; INSTATE = [Q2, Q1, Q0];S0 = [0, 0, 0];S1 = [0, 0, 1];S2 = [0, 1, 1];S3 = [1, 1, 0];S4 = [1, 0, 0];S5 = [1, 1, 1];S6 = [1, 0, 1]; equations D2 = (!Q2 & Q0) # (Q2 & !Q0); D1 = D11i # D12i; D11o = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0); D12o = (!X & Q2 & !Q0) # (Q1 & !Q0); D0 = !Q0; Z = (X & Q1) # (!X & !Q1);

end bcd2excess3;

P10H8 PAL

Explicit equationsfor partitionedoutput functions

10-22


module bcd2excess3title 'BCD to Excess 3 Code Converter State Machine'u1 device 'p12h6';

"Input Pins X, Q2, Q1, Q0 pin 1, 2, 3, 4; "Output Pins D2, D1, D0, Z pin 17, 18, 16, 15; INSTATE = [Q2, Q1, Q0]; OUTSTATE = [D2, D1, D0];S0in = [0, 0, 0]; S0out = [0, 0, 0];S1in = [0, 0, 1]; S1out = [0, 0, 1];S2in = [0, 1, 1]; S2out = [0, 1, 1];S3in = [1, 1, 0]; S3out = [1, 1, 0];S4in = [1, 0, 0]; S4out = [1, 0, 0];S5in = [1, 1, 1]; S5out = [1, 1, 1];S6in = [1, 0, 1]; S6out = [1, 0, 1]; equations D2 = (!Q2 & Q0) # (Q2 & !Q0); D1 = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0) # (!X & Q2 & !Q0) # (Q1 & !Q0); D0 = !Q0; Z = (X & Q1) # (!X & !Q1); end bcd2excess3;

P12H6 PAL

2 outputs can have4 different productterms

Simpler equations

10-23


module bcd2excess3title 'BCD to Excess 3 Code Converter'u1 device 'p16r4';

"Input Pins Clk, Reset, X, !OE pin 1, 2, 3, 11; "Output Pins D2, D1, D0, Z pin 14, 15, 16, 13; SREG = [D2, D1, D0];S0 = [0, 0, 0];S1 = [0, 0, 1];S2 = [0, 1, 1];S3 = [1, 1, 0];S4 = [1, 0, 0];S5 = [1, 1, 1];S6 = [1, 0, 1];

P16R4 PAL (registered PAL)

state_diagram SREGstate S0: if Reset then S0 else if X then S2 with Z = 0 else S1 with Z = 1state S1: if Reset then S0 else if X then S4 with Z = 0 else S3 with Z = 1state S2: if Reset then S0 else if X then S4 with Z = 1 else S4 with Z = 0state S3: if Reset then S0 else if X then S5 with Z = 1 else S5 with Z = 0state S4: if Reset then S0 else if X then S6 with Z = 0 else S5 with Z = 1state S5: if Reset then S0 else if X then S0 with Z = 1 else S0 with Z = 0state S6: if Reset then S0 else if !X then S0 with Z = 1

end bcd2excess3;

10-24

IntroductionFSM Design with Counters

Synchronous Counters: CLR, LD, CNT

Four kinds of transitions for each state:

(1) to State 0 (CLR)

(2) to next state in sequence (CNT)

(3) to arbitrary next state (LD)

(4) loop in current state

Careful state assignment is needed to reflect basic sequencingof the counter

Careful state assignment is needed to reflect basic sequencingof the counter

0

n

n+1 m

no signals

assertedCLR

CNT LD

10-25

IntroductionFSM Design with Counters

BCD-to-Excess 3 Converter

State Diagram

Note the sequential natureof the state assignments

Reset

0/10

1/0

1

0/11/0

40/0, 1/1

20/0, 1/1

0/1

5

1/0

0/0, 1/1

3 6

0/1

10-26

IntroductionFSM Design with CountersBCD-to-Excess 3 Converter

Transition Table

CLR signal dominates LD which dominates Count

Inputs/Current State

Next State Outputs

X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Q2+ 0 0 0 0 1 0 0 X 1 1 0 0 1 1 X X

Q1+ 0 1 1 0 0 1 0 X 0 0 1 0 0 1 X X

Q0+ 1 0 1 0 1 1 0 X 0 1 1 0 1 0 X X

Z 1 1 0 0 1 11 X 0 0 1 1 0 1 X X

CLR 1 1 1 0 1 1 0 X 1 1 1 0 1 1 X X

LD 1 1 1 X 1 0 X X 0 0 1 X 1 1 X X

EN 1 1 1 X 1 X X X X X 1 X 1 1 X X

C X X X X X 0 X X 1 1 X X X X X X

B X X X X X 1 X X 0 0 X X X X X X

A X X X X X 1 X X 0 1 X X X X X X

10-27


Espresso Input File

Espresso Output File

.i 5

.o 7

.ilb res x q2 q1 q0

.ob z clr ld en c b a

.p 171---- -0-----00000 1111---00001 1111---00010 0111---00011 00-----00100 0111---00101 110-01100110 10-----00111 -------01000 010-10001001 010-10101010 1111---01011 10-----01100 1111---01101 0111---01110 -------01111 -------.e

.i 5

.o 7

.ilb res x q2 q1 q0

.ob z clr ld en c b a

.p 100-001 0101101-0-01 1000000-11-0 10000000-0-0 0101100-000- 1010000-0--0 00100000-10- 0101011--11- 1000000-11-- 0010000-1-1- 1010000.e

10-28


When the state diagram has fewer out-of-sequence jumps, a counterbased implementation can be very effective

Synchronous Output Register

1 01 0

excess 3 PLA

Reset X Q2 Q1 Q0

Z \CLR

\LD EN

C B A

CLK

X

7 10

2

9

1

P T

CLKD C B A

LOAD

CLR

RCO

QD QC QB QA

15

D Q

C Q

Z163

11121314

6543

10-29

IntroductionFSM Design with More Sophisticated PLDs

Programmable Logic Devices = PLD

Field Programmable Gate Arrays = FPGAs

• Altera MAX Family

• Actel Programmable Gate Array

• Xilinx Logical Cell Array

PALs, PLAs = 10 - 100 Gate Equivalents

100 - 1000(s) of Gate Equivalents!

10-30

Introduction

Clk MUX

Output MUXQ

F/B MUX

Invert Control

AND ARRAY

CLK

pad

FSM Design with More Sophisticated PLDs

Altera EPLD (Erasable Programmable Logic Devices)

Historical Perspective: PALs : same technology as programmed once bipolar PROM EPLDs : CMOS erasable programmable ROM (EPROM) erased by UV light

Altera building block = MACROCELL

8 Product TermAND-OR Array

+Programmable

MUX's

Programmable polarity

I/O Pin

Seq. LogicBlock

Programmable feedback

low power, high speed

10-31

IntroductionFSM Design with More Sophisticated PLDsDesign with More Sophisticated PLDs

Altera EPLDs contain 8 to 48 independently programmed macrocells

Personalized by EPROM bits:

Flipflop controlledby global clock signal

local signal computesoutput enable

Flipflop controlledby locally generatedclock signal

+ Seq Logic: could be D, T positive or negative edge triggered+ one product term to implement clear function

Synchronous Mode

Asynchronous Mode

Global CLK

OE/Local CLK

EPROM Cell

1

Global CLK

OE/Local CLK

EPROM Cell

1

Clk MUX

Clk MUX

Q

Q

10-32

Introduction

LAB A LAB H

LAB B LAB G

LAB C LAB F

LAB D LAB E

P I A

FSM Design with More Sophisticated PLDsDesign with More Sophisticated PLDs

AND-OR structures are relatively limited Cannot share signals/product terms among macrocells

Altera solution: Multiple Array Matrix (MAX)

LogicArray

Blocks(LAB)

(similar tomacrocells)

64programmable

I/O pins

Global Routing:ProgrammableInterconnect

Array

8 Fixed Inputs52 I/O Pins8 LABs16 Macrocells/LAB32 Expanders/LAB

EPM5128:

EPM5128:192 macrocells into 12 LAB100 MSI or P2210 PALs

10-33


LAB Architecture

Expander Terms shared among allmacrocells within the LAB

Macrocell ARRAY

I/O Block

Expander Product

Term ARRAY

I NPUTS

P I A

I/O Pad

I/O Pad

Macrocell P-Terms

Expander P-Terms

EPLDs based EPROMs : less expensive packaging can be used crosspoints can be reprogrammed individually

appear like inputs to macrocellscan use expander terms for multilevel structures

10-34

IntroductionFSM Design with More Sophisticated PLDsP22V10 PAL

0ASYNCHRONOUS RESET (TO ALL REGISTERS)

23AR

88132176220264308352396

44

22

2

OUTPUT LOGIC

MACROCELL

P - 5810 R - 5811

528572616660704748792836

484

880

440

21

3

OUTPUT LOGIC

MACROCELL

P - 5812 R - 5813

10561100114411881232127613201364

1012

1408

924

968

1452

20

4

OUTPUT LOGIC

MACROCELL

P - 5814 R - 5815

16721716176018041848189219361980

1628

2024

1496

1584

2068

1540

2112

19

5

OUTPUT LOGIC

MACROCELL

P - 5816 R - 5817

23762420246425082552259626402684

2332

2728

2156

2288

2772

22442200

28162860

1

1

0

0

1

0

0

1

D Q

QSP

10

5808

P

R

5809

10 4 8 12 16 20 24 28 32 36 40

INCREMENT

FIRST FUSE NUMBERS

15

9

OUTPUT LOGIC

MACROCELL

P - 5824 R - 5825

49725016506051045148519252365280

4928

5324

4884

17

7

OUTPUT LOGIC

MACROCELL

P - 5820 R - 5821

38283872391639604004404840924136

3784

4180

3652

3740

4224

3696

4268

16

8

OUTPUT LOGIC

MACROCELL

P - 5822 R - 5823

44444488453245764620466447084752

4400

4796

4312

4356

4840

18

6

OUTPUT LOGIC

MACROCELL

P - 5818 R - 5819

31243168321232563300334433883432

3080

3476

2904

3036

3520

29922948

35643608

14

10

OUTPUT LOGIC

MACROCELL

P - 5826 R - 5827

54125456550055445588563256765720

5368

11

5764

13

SYNCHRONOUS PRESET (TO ALL REGISTERS)

0 4 8 12 16 20 24 28 32 36 40INCREMENT

Supports large number of product terms per outputLatches and muxes associated with output pins

10-35


Actel Programmable Gate Arrays

Rows of programmablelogic building blocks

+

rows of interconnect

Anti-fuse Technology:Program Once

8 input, single output combinational logic blocks

FFs constructed from discrete cross coupled gates

Use Anti-fuses to buildup long wiring runs from

short segments

programmed only once

I/O Buffers, Programming and Test Logic

Logic Module Wiring Tracks

I/O Buffers, Programming and Test Logic

I/O

Bu

ffer

s, P

rog

ram

min

g a

nd

Tes

t L

og

ic I/O B

uffers, P

rog

ramm

ing

and

Test L

og

ic

. . . . . .

. . . . . .

. . . . . .

10-36

IntroductionFSM Design with More Sophisticated PLDsActel Logic Module

Basic Module is aModified 4:1 Multiplexer

Example: Implementation of S-R Latch

2:1 MUXD0

D1

SOA

2:1 MUXD2

D3

SOB

2:1 MUX

S0

Y

S1

2:1 MUX"0"

R

2:1 MUX"1"

S

2:1 MUX Q

"0"

AND : A=D1 B=SOA 0=D0SO=S1=0

Y=SOA DO+SOA+D1=AB

if R=0 then Q=0if R=1 then Q=1 if S=0 Q=Q otherwise

10-37

IntroductionFSM Design with More Sophisticated PLDsActel Interconnect

Interconnection Fabric

Logic Module

Horizontal Track

Vertical Track

Anti-fuse

high voltage

bidirectioninterconnection

between 2 crossingwires

Antifuse are placed whenever a horizontal and a vertical wire cross as well asbetween adjacent horizontal and vertical wire segments

10-38


Actel Routing Example

Jogs cross an anti-fuse

minimize the # of jobs for speed critical circuits

2 - 3 hops for most interconnections

worst may be 4 hops

Logic modules must be carefully placed and thenwired by routing interconnections

Logic Module

Logic ModuleLogic Module Output

Input

Input

10-39

IntroductionFSM Design with More Sophisticated PLDsDesign with More Sophisticated PLDs

Xilinx Logic Cell Arrays

CMOS Static RAM Technology: programmable on the fly!

All personality elements connected into serial shift register

Shift in string of 1's and 0's on power up

General Chip Architecture: • Logic Blocks (CLBs) • IO Blocks (IOBs) • Wiring Channels

IOB IOB IOB IOB

CLB CLB

CLB CLB

IOB

IOB

IOB

IOB

Wiring Channels

10-40


Xilinx LCA Architecture

Inputs: Tri-state enable bit to output input, output clocks

Outputs: input bit

Internal FFs for input & output paths

Fast/Slow outputs 5 ns vs. 30 ns rise

Pull-up used with unused IOBs

D Q

OUT INV

TS INV

OUTPUT SOURCE

SLEW RATE

PASSIVE PULLUP

MUX

R

DQ

R

Vcc

PAD

Output Buffer

TTL or CMOS Input Buffer

Global ResetClocks

Enable Output

Out

Direct In

Registered In

Program Controlled Options

I/O Blockslew rate : slow down the output signal

10-41


output can be registered or direct


Configurable Logic Block: CLB

2 FFs

5 programmablemuxes

Any function of 5 Variables

Global Reset

Clock, Clock Enb

Independent DIN

Combinational Function Generator

D RDQ

CEMux

D RDQ

CE

Mux

Mux

Mux

Mux

A B C D E

Q1

Q2

Reset

DIN

Clock

Clock Enable

F

G

X

Y

10-42



CLB Function Generator

Any function of 5 variables

Two Independent Functionsof 4 variables each

Function of 5

Variables

F

G

Mux

Mux

AB

C

DE

Q1

Q2

Function of 4

VariablesF

Mux

Mux

AB

C

DE

Q1

Q2

Mux

Function of 4

VariablesG

Mux

Mux

AB

C

DE

Q1

Q2

Mux

10-43



CLB Function Generator

Certain LimitedFunctions of 6 Variables

Function of 4

VariablesE

Mux

Mux

AB

C

D

Q1

Q2

Function of 4

Variables

Mux

Mux

AB

C

D

Q1

Q2

Mux

F

G

10-44


Xilinx Application Examples

5-Input Parity Generator

Implemented with 1 CLB:

F = A xor B xor C xor D xor E

2-bit Comparator: A B = C D or A B > C D

Implemented with 1 CLB:

(GT) F = A C + A B D + B C D

(EQ) G = A B C D + A B C D + A B C D + A B C D

(this is a different parity generator than the one in Chapter 8!)

10-45



n-Input Majority Circuit

Assert 1 whenever n/2 or greater inputs are 1

n-input Parity Functions 5 input = 1 CLB, 2 Levels of CLBs yield up to 25 inputs!

CLB

5-input Majority Circuit

CLB

CLB

CLB

7-input Majority Circuit

CLB

CLB

9 Input Parity Logic

10-46



4-bit Binary Adder

CLB

A0 B0 Cin

S0

CLB

A1 B1

S1

CLB

A2 B2

C1S2

CLB

A3 B3

C2S3 C0Cout

S0

S1

C2

A1 B1 CinA0 B0

CLBS2

S3

Cout

A3 B3 A2 B2

CLB

Full Adder, 4 CLB delays tofinal carry out

2 x Two-bit Adders (3 CLBseach) yields 2 CLBs to finalcarry out

tradeoffs betweenresouces and delay

10-47



Interconnect

Direct Connections : fastest, shortest-distance form of interconnect

Global Long Line : used for longer distance conn. or for signals with a moderate fanout(not possible to connect every pins)

Long Line Interconnection : time critical signals that must be distributed to many CLBs with minimal clock skew

Switching Matrix Connections

X

YCLB3

A

D

DIBCKE R

CE

X

YCLB1

A

D

DIBCKE R

CEX

YCLB0

A

D

DIBCKE R

CE

Direct Connections

Horizontal Long Line

Vertical Long Lines

Global Long Line

Switching Matrix

Horizontal Long Line

X

YCLB2

A

D

DIBCKE R

CE

10-48



Implementing the BCD to Excess 3 FSM

Q2+ = Q2 • Q0 + Q2 • Q0

Q1+ = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0

Q0+ = Q0

Z = Z • Q1 + X • Q1

No function more complex than 4 variables 4 FFs implies 2 CLBs

Synchronous Mealy Machine

Global Reset to be used

Place Q2+, Q0+ in once CLB Q1, Z in second CLB maximize use of direct & general purpose interconnections

10-49



Implementing the BCD to Excess 3 FSM

FG

FG

ACEDI

B

C

K

ED RES

X

Y

Q2

Q0

Q2Q0

Q0

FG

FG

ACEDI

B

C

K

ED RES

X

Y

Q1

Z

Q1Q0

Q1X

Q2X

X

CE

Clk Clk

CLB1 CLB2

10-50

IntroductionDesign Case Study

Traffic Light Controller

Decomposition into primitive subsystems

• Controller FSM next state/output functions state register

• Short time/long time interval counter

• Car Sensor

• Output Decoders and Traffic Lights

10-51



Block Diagram

Reset

C (async)

Clk

Car Sensor C (sync)

State Register

2

Next State Output Logic

TS TL

controller fsm

2

Encoded Light

Signals

Light Decoders

F

3

3

H

ST

short time/ long time counter

ResetClk

22

10-52



Subsystem Logic

Car Detector

+

+

D

R

Q

Q

Present

\Present

Cin C

\Reset

CLK

debounce switch

asynchronousinputs Light

Decoders

G

BA

Y1Y0

Y3Y2

139a

0 0 1

G

BA

Y1Y0

Y3Y2

139b

001

14

H0

3F1

2F0567

4

FG FY FR

11109

13H1

15

1

12

HRHYHG

IntervalTimer

QAQBQCQD

163RCO

PT

ABCD

LOAD

CLR

CLK

+

15

3456

107

9

121314

TS

TL

2CLK

11

ST

1CLRReset

10-53



State Assignment : HG=00, HY=10, FG=01, FY=11

.i 5

.o 7

.ilb c tl ts q1 q0

.ob p1 p0 st h1 h0 f1 f0

.p 811-0- 1010000--010 10001000--01 1010000--110 0110100--111 0011001-----0 0000010---01 0101000--011 1101001.e

21 literals8 unique terms

no 5 input gates, 2 4 input gates14 gates total

10-54



Next State Logic

State Assignment: HG = 00, HY = 10, FG = 01, FY = 11

P1 = C TL Q1 + TS Q1 Q0 + C Q1 Q0 + TS Q1 Q0

P0 = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0

ST = C TL Q1 + C Q1 Q0 + TS Q1 Q0 + TS Q1 Q0

HL[1] = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0

HL[0] = TS Q1 Q0 + TS Q1 Q0

FL[1] = Q0

FL[0] = TS Q1 Q0 + TS Q1 Q0

PAL/PLA Implementation: 5 inputs, 7 outputs, 8 product terms PAL 22V10 -- 11 inputs, 10 prog. IOs, 8 to 14 prod terms per OR

ROM Implementation: 32 word by 8-bit ROM (256 bits) Reset may double ROM size

10-55



Next State Logic

Counter-based Implementation HG=00 HY=01 FG=10 FY=11

ST = Count

TTL Implementation with MUX and Counter

Can we reduce package count by using an 8:1 MUX?

2 x 4:1 MUX

HG

HY

FG

FY

TL•C / ST

TS / ST

TL+C / ST

TS / ST

QAQBQCQD

163RCO

PT

ABCD

LOAD

CLR

CLK

B1B2B3

B0

A3A2A1A0

153GA

GB

YA

YB

S1 SO

+

2 15

1\Reset

6543

9

14

14

1211

3

5

TS

9

TL

TLC

\C

13

2

77

10ST4

6

1011

15

1213

1

Q0Q1

10-56



Next State Logic

Counter-based Implementation

Dispense with direct output functions for the traffic lights

Why not simply decode from the current state?

ST is a Synchronous Mealy Output

Light Controllers are Moore Outputs

G

BA

Y1Y0

Y3Y2

139a

0 0 0 0 11

2

HR FRHY

3

7

FY

6

FG

54

1

HG

Q1

Q0

10-57



LCA-Based Implementation

Discrete Gate Method:

None of the functions exceed 5 variables

P1, ST are 5 variable (1 CLB each)

P0, HL1, HL0, FL0 are 3 variable (1/2 CLB each)

FL1 is 1 variable (1/2 CLB)

4 1/2 CLBs total!

10-58



LCA-BasedImplementation

Placement offunctions selectedto maximize theuse of directconnections

Steps1) map functions onto CLBs2) minimize the amount of inter CLB routing

TS

X

Y

A

D

DIBCKE R

CE

X

Y

A

D

DIBCKE R

CEX

Y

A

D

DIBCKE R

CE

X

Y

A

D

DIBCKE R

CE

X

Y

A

D

DIBCKE R

CEX

Y

A

D

DIBCKE R

CE

Q1

F1

Q0F0

ST

H1

H0

TS TS

Q0

Q0

Q0

C

C

CTL

Q1

TL

TS

Q1

Q1 Q0

TS

Q1

TL

TS

10-59



LCA-Based Implementation

Counter/Multiplexer Method:

4:1 MUX, 2 Bit Upcounter

MUX: six variables (4 data, 2 control) but this is the kind of 6 variable function that can be implemented in 1 CLB!

2nd CLB to implement TL • C and TL + C'

But note that ST/Cnt is really a function of TL, C, TS, Q1, Q0 1 CLB to implement this function of 5 variables!

2 Bit Counter: 2 functions of 3 variables (2 bit state + count) Also implemented in one CLB

Traffic light decoders: functions of 2 variables (Q1, Q0) 2 per CLB = 3 CLB for the six lights

Total count = 5 CLBs

10-60

IntroductionChapter Summary

• Optimization and Implementation of FSM

State Reduction Methods: Row Matching, Implication Chart

State Assignment Methods: Heuristics and Computer Tools

• Implementation Issues

Choice of Flipflops

Structured Logic Methods

ROM based

PLA/PAL based

Jump Counter Methods

Sophisticated PLDs: Altera, Actel, Xilinx

chapter #10: finite state machine implementation

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