chapter 06 final

8/17/2019 Chapter 06 Final

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1

Digital Logic Design

Registers & Counters


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Registers and Counters

Outline Registers

Shift registers Counters

Ripple counters Synchrounous counters

Other counters


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Overview

Register Storage elements Group of flip-flops

n-bits (1 per flip-flop) n-bits of binary representation

Counter Follows a preetermine se!uence of binary states Register with a specific function


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Registers

Computer systems use n-bit numbers "oo comple# to worry about ini$iual bits %ata is store in registers'

#ample aition of registers %esigner-frienly abstraction Register transfer le$el (R"*)

+hat functions shoul a register support, Store ata (an states) Getting ata in

n parallel n serial


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Parallel vs. Serial Transfer

Serial communications .ro$ies a binary number as a se!uence of

binary igits/ one after another/ through oneata line

.arallel communications .ro$ies a binary number through multiple

ata lines at the same time

0i#e serialparallel communications


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Parallel Transfer

.arallel transfer from register X to register Y


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Simle Parallel !oad

Register .arallel loa 2ll n bits can be store at the same time

Straightforwar circuit n % flip-flops Share cloc3 Share reset

+hat is the problem with this register, 4ow long is ata store, % flip-flops are set on each cloc3 cycle 5nesire if we want to store ata 5nesire if input re!uires time to stabili6e

Suggeste impro$ement,


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Parallel !oad Register

Register shoul only loawhen specifie

%esign choices

ntercept cloc3 signal 7ot esirable/ because of

ae cloc3 elay Feebac3 flip-flop $alue

Circuit +hen loaing/ input is fe toflip-flop

+hen not loaing/ currentstate is recycle'


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Serial $ata Transfer

+hat are the limitations of a parallel loaregister, Re!uires n ata lines Can be e#pensi$e for 89-bit or :;-bit registers

Serial ata transfer common in igital

systems "ransfer of information one bit at a time


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1%

Serial $ata Transfer

#amples Serial port on .C 5S< (5ni$ersal Serial


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S&ift Registers

Serial transfer loa bits ini$iually 4ow shoul we specify which bit is being loae,

Serial loaing by shifting is simplest %oes not re!uire any control bits One bit per cloc3 tic3


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Serial Transfer' ()amle

Serial transfer from register A to register B

#ample

2ssume A= 1011an B = 0010

+hat are the register$alues at T1 – T4,


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Serial *ddition

2ition is a serial' process 7ee to etermine carry before ne#t significant bit is ae +e can use shift registers to a bits one-by-one Only one-bit aer neee

Serial adder


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Serial *ddition

nitial state *oa bits to a in A an B

Shift control

Controls (stops) aition

4ow can we hanle carry, Feebac3 $ia % flip-flop Carry is sa$e in % flip-flop Q

+here is the result, Register A after n shifts


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Serial *dder using +, -i-o State table

>? @ #y

A? @ # B = B B

S @ #⊕y⊕?


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Serial *dder

Circuit


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/niversal S&ift Register

Shift registers are useful +e want to use it as a basic builing bloc3

5ni$ersal Shift Register Control functions

C*2R reset register to D C*OCA synchroni6es operation S4F"-RG4" shifts right (incl= serial O)

S4F"-*F" shifts left (incl= serial O) .2R2***-*O2% parallel transfer of register $alue .2R2*** O5".5" n ata lines 7O O.R2"O7 state remains unchange


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/niversal S&ift Register


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Counters

2 register that goes through a predetermined se!uence of statesupon application of input pulses 4ow is it ifferent from a generic FS0,

#ample n-bit binary counter Counts from D through 2 n-1

"wo fla$ors Ripple counter Synchronous counter

%ifference 4ow flip-flops are triggere when propagating upates

Count-down counter 2lso counter/ but in re$erse irection


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2%

Counters

+hich flip-flops to use for counters, " flip-flop,

Ees

>A flip-flop Ees

% flip-flop Ees


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Rile Counter

Circuit with " flip-flops 2re flip-flops positi$e or negati$e

ege triggere,

Count signal toggles 2D

*ow-orer flip flop pro$ies triggerfor aacent flip flop

7ot all flops change $aluesimultaneously *ower-orer flops change first


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Rile Counter

#ample Current state 1D11 Count toggles A0, fallin

ege

Falling ge 20 toggles A1 Falling ge A1 toggles A2 Rising ege A2 no

change on A! 7ew state 11DD

Similar with % flip-flops


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Rile Counter' Timing$iagram


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*not&er *s0n&ronous RileCounter Similar to " flop e#ample on pre$ious slie


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inar0 Rile CountdownCounter


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inar0 Rile CountdownCounter 1111 111D 11D1 11DD 1D11 1D1D 1DD1 1DDD D111 D11D D1D1 D1DD

DD11 DD1D DDD1 DDDD 1111

4-bits: A3, A2, A1, A0

A0 LSB changes at each step

A1 changes when A0 goes from 0 to 1



Obser$ations


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C$ Rile Counter

Counting se!uence

1 D D 1


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2"

C$ Rile Counter

State iagram


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2#

C$ Rile Counter

Circuit iagram


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3%

C$ Rile Counter


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*s0n&ronous RileCounters Carry propagates through bits Flip-flops respon one after another in a

rippling effect ach flip-flop output ri$es the C*A input of

the ne#t flip-flop

Flip-flops o not change states in e#actsynchronism with the applie cloc3 pulses "here is dela" between the responses of

successi$e flip-flop 5nesirable because of transition states

#ample %esire DD11 D1DD Real DD11 DD1D DDDD D1DD

Solution Synchronous counter


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S0n&ronous Counter

Synchronous (parallel) counter State switches with common cloc3 2ll flip-flops change at same time +hat is necessary to switch state in one step,

7ee to 3now which bits to toggle Hery simple carry loo3-ahea'

Remember f > @ A @ D/ flip-flop maintains ol $alue f > @ A @ 1/ flip-flop toggles

Circuit 27% gates test which bits will roll o$er


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S0n&ronous inar0 Counter


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/down Counter

4ow can we count own, *east significant bit toggles most

fre!uently +hen transition from D to 1/ then

toggle ne#t Synchronous counter nees to

loo3 ahea for flip-flops that are D Connect loo3-ahea to ?I output

5p-own counter circuit f #p = 1/ then increment f $own = 1/ then ecrement +hat if #p = $own = 1,


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Counter wit& /nused States

n flip-flops 9n binary states 9n is the upper limit 2 counter may not ha$e all states

One solution %o not treat unuse states +hat if the circuit somehow umps into one of these states,

Other solution 4anle unuse states as well in the esign


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#ample Suppose your counter counts in the following se!uence

DDD/ DD1/ D1D/ 1DD/ 1D1/ 11D

< an C repeating DD/ D1/ 1D 2 alternates between D an 1 e$ery three counts

States D11 an 111 are not present here


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3"

Ring Counter

Shift register with one bit set to 1 Halue shifts with e$ery count cycle

"iming iagram


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3#

Ring Counter

2lternati$e implementation Counter has only n states 2t most %o 2 &n' bits shoul be enough

Counter an ecoer


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4%

+o&nson Counter


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+o&nson Counter

.roblem 2n occurrence of unuse cannot be reco$ere

Correction%C @ (2JC)=

chapter 06 final

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