challenges in high voltage ic design for ate applications · • new technology adoption (sic/gan)...
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Challenges In High Voltage IC Design for ATE Applications
Test Technology Symposium 2019Jef Thoné – Mike Wens
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2019 confidential 2
MinDCet : Power Conversion ASIC Design and Production, ISO9001
Turnkey Power ASIC Production
ASIC Design and Layout
Power Module Development
MADMIX/MADCAPInductor/capacitor measurement
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Measurement capabilities
• Recent Investments Q22019: Teradyne ETS-88 ATE for
smooth flow fromcharacterization toproduction testing Chroma FT3110S pick &
place handler for small-volume in-house tri-temp(-40°C-150°C) testing andpre-production testing Available from Q4 2019
MinDCet 2019 confidential 3
In house
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Measurement systems under development
• MADCAP : non-linear large signal capacitormeasurements, expected Q1 2020
• MADTHOR : 200V transistor analysis system(capacitance analysis and transistor curves), Q2 2020
MinDCet 2019 confidential 4
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EU Targets Greenhouse Gas Emission
TTS 2019 confidential 5
https://www.eea.europa.eu/data-and-maps/indicators/transport-emissions-of-greenhouse-gases/transport-emissions-of-greenhouse-gases-11
2017 level, 1100 Megaton
2030 target, 920 Megaton
2050 target, 330 Megaton
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EV and WideBandgap
TTS 2019 confidential 6
X-factor applications
Source : ROHM
ST / Cree SiC FETs
Source : https://cleantechnica.com/2018/05/28/more-tesla-model-3-powertrain-fun-from-carburetors-to-carborundum-youve-come-a-long-way-baby/
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WBG properties
• Adoption of WBG (wide-bandgap) materials (SiC andGaN) improve efficiency of electrical drives Faster switching / less reverse recovery => reduced
switching losses But : specific gate driver / isolator / isolated supplies /
DC bus are needed› 2CV with a Ferrari engine: bad idea
• ATE need to have similar or better specs thansupporting WBG components
TTS 2019 confidential 7
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Ideal interface switch
• Ron = 0• Roff = inf.• L = 0• C = 0• Imax = Inf• Vmax = inf.• Area = 0• Rth = 0
TTS 2019 confidential 8
Luckily for us only in Spice…
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Opposing interface requirements
TTS 2019 confidential 9
Low Rdson
small area Good thermal conduction
Low capacitance
Low charge injection
Low leakage
High voltage capability
High current capability
Low Xtalk
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What is a good compromise?
TTS 2019 confidential 10
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Low Rdson
• Rationale : Conduction losses RC Diode conduction at rated I
• By : Large W/L : Rdson ~ L/W
• Dependencies: Area ~ L*W (cost) Interconnect (metallization
and bonding)
TTS 2019 confidential 11
R.I²
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High current capability
• Rationale: Conduct current within EM
limits• By: Distributed current Custom layout Common sense + FEA
› R3D (Silicon Frontline)› Magwell
• Dependencies: Metallization EM limits Area / aspect ratio Packaging
TTS 2019 confidential 12
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Small Area
• Rationale Multi channel
integration Low C, L and R
• By Architecture Technology (Si,
GaN, SiC, hybrid,…)
• Dependencies Die yield ~ exp^-
Area Thermal
conduction ~ Area
TTS 2019 confidential 13
L
C
1nH/mm
80fF/mm1mm wide PCB trace, 1mm above ground
0.5mOhm/mm1mm wide PCB trace, 35u thick
R
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Good thermal conduction
• Rationale: Keep Tj under control
(lifetime)• By: Area/dimensions material stack Package choice FEA thermal simulation
(transient/static)• Dependencies: Transient power peaks Driver location Thermal interface
materials Tech choice
TTS 2019 confidential 14
Rth Delta T0.017 0.031 Active0.000 0.000 BOX
1.491 2.685 HW
0.370 0.667 Die Attatch
0.125 0.225 Package slugK/W °C
0.200 0.360 Thermal grease
2.00 3.6
1.5 2.7 Heat-sink/ambient
Total 3.7 6.7K/W °C
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Good thermal conduction
• dT @ 2us = 4.5 K• dT @ 2 s = 225 K
TTS 2019 15
E.g. 0.06mm² driver on 4mm² Si die
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Good thermal conduction
TTS 2019 confidential 16
Packaging is key
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High Voltage Capability
• Rationale: Meet the DUT voltage requirements
• By: Technology choice Custom layouts (metal clearances) Custom devices Custom DRC Hybrid technologies (e.g. GaN-on-SOI)
• Dependencies: ~ Area SOA operation Isolation Clearance / creepage beyond package thermal requirements
TTS 2019 confidential 17
Schematic cross-section of GaN-on-SOI structure, featuring buried oxide, oxide filled deep trench, local substrate contact and p-GaNHEMT devices. Picture courtesy IMEC.
Floorplan of the symmetrical GaN-on-SOI 32 mOhm/10A halfbridge
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Low leakage
• Rationale: Loading of Hi-Z DUT Accuracy of VI measurements
• By: Technology choice Architectural choices Leakage cancellation circuits (1st order) Calibration
• Dependencies: ~ Area ~ Exp(Temperature)
TTS 2019 confidential 18
10-10
10-9
10-8
10-7
10-6
10-5
10-4
0 25 50 75 100 125
I d (@
200V
) [A
/mm
]
Temp [°C]
P173735 / X18
A1
GaN on SOI 200V FET Leakage (IMEC)
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Low charge injection
• Rationale: Limit loading of DUT
• Ciss defines gateswitching losses
• Coss defines outputswitching losses
• Crss = Cgd
• All non-linear vs ds/ gsvoltage
TTS 2019 confidential 19
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Definitions of charges
• Qg = Qgs + Qgd + Cgs *(Vgs,pl2 – Vgs, pl3) Qgs,th = Ciss * Vgs,th
Qgs = Ciss * Vgs,pl1
Qgd = Cgs * (Vgs,pl1 – Vgs,pl2)+ ∫𝐶𝐶𝑑𝑑𝑑𝑑 𝑉𝑉 .𝑑𝑑𝑉𝑉𝑑𝑑𝑑𝑑
• Qds = ∫𝐶𝐶𝑑𝑑𝑠𝑠 𝑉𝑉 .𝑑𝑑𝑉𝑉𝑑𝑑𝑑𝑑• Qci = Qgd + Qds
• Dependencies: Area
Technology defined!
Independent of switchingspeed!
TTS 2019 confidential 20
JEDEC standard 24-2
Vgs,pl3
Vgs,pl2
Vgs,pl1Vgs,th
Qgs,th
Qgs QgdQg
CAS300M12BM2
Slope = 1/Cg
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Low capacitance
• Rationale: Limit capacitive loading
on the DUT Limit charge injection
› Routing can contribute upto 300%
• By: Parasitic extraction,
post layout Smart layout strategies
• Dependencies: Process metal stack
TTS 2019 confidential 21
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Low crosstalk
TTS 2019 confidential 22
• Rationale: Limit distortion of adjacent DUT channels Limit loading of high impedance DUT channels
• By: Limit interface capacitance Low impedant return paths Post layout extraction
• Dependencies: Metal stack Routing impedance
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Conclusions
• New technology adoption (SiC/GaN) defines future ATEinterface requirements
• IC Design of VI’s and MUXes for ATE: multi-dimensionaldesign challenge
• If you don’t like to make trade-offs :
• If you need help to make the trade-offs: call MinDCet !
TTS 2019 confidential 23
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What can we do for you?
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MinDCet 2019 confidential 24
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