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C. D. Young: Curriculum Vitae of 32

CHADWIN D. YOUNG Materials Science and Engineering Department

Electrical Engineering Department The Univeristy of Texas at Dallas

800 W. Campbell Rd., RL10, Richardson, TX 75080 [email protected]

Current Position: Assistant Professor

Education Doctor of Philosophy, Electrical Engineering, North Carolina State University, 5/04 Master of Science, Electrical Engineering, North Carolina State University, 5/98 Bachelor of Science, Electrical Engineering, University of Texas at Austin 5/96

Disseration Charge Trapping Characterization Methodology for the Evaluation of Hafnium-based Gate Dielectric Film Systems

Various electrical characterization techniques that quantify trapped charge in the metal-oxide-semiconductor (MOS) system were evaluated on hafnium-based gate dielectric stacks. Results demonstrated that pulsed-based characterization methods provided the best resolution and more accurately represented the amount of trapped charge, and while doing so, allowed for its removal to obtain close-to-intrinsic characteristics (i.e., device performance in the absence of trapped charge).

Committee: Dr. Veena Misra, Co-Chair; Dr. Richard T. Kuehn, Co-Chair; Dr. John Hauser; George Brown; and Dr. Dennis M. Maher. Industrial Experience SEMATECH, Austin, TX, February 2001 – 2008; Albany, NY 2008 to 2012

Ø Senior Member of Technical Staff, 2011 to 2012 Ø Member of Technical Staff, 2008-2011 Ø Engineer, 2004-2008 Ø Post Doc, 2003-2004 Ø Ph.D. Intern, 2001-2003 o Actively measuring and characterizing transistors and capacitors of

experimental gate stacks and device structures (alternative gate electrodes, ultra-thin oxides, oxynitrides, and high-dielectric constant insulators, non-planar devices, high mobility substrates)


o Established the characterization and reliability laboratory (Albany facility) through the oversight of equipment selection and procurement (~$1.5M), tool installation, and “hands-on” set up for final acceptance of equipment.

o Developed and implemented training and test laboratory protocols as a Co-manager of daily operations that trained students (2-year associate degree up to Ph.D. students) and engineers, improved lab efficiency, and reduced consumable costs.

o Implemented and evaluated several charge trapping measurement techniques that have greatly enhanced SEMATECH’s ability to characterize the many high-k gate dielectric samples produced

o Newly developed or implemented measurements included various forms of charge pumping, fast transient analysis techniques such as the ultra-short pulse I-V, intrinsic mobility extraction procedure, and positive constant voltage stress evaluation using a form of charge pumping to detect trap generation in the interfacial layer region of high-k gate stacks

o Implemented and evaluated several reliability techniques such as Bias Temperature Instability, Hot Carriers, and dielectric breakdown for high-k gate stacks

o Implemented the “Smart” TDDB algorithm – Real-time adaptive testing using a decision-making algorithm that determines how to analyze degradation throughout the wear-out phase to hard breakdown.

Graduate Student, North Carolina State University, Raleigh, NC; 1996 to

February 2001: Graduate Research/Summer Internships o August 1996-May 1998 o Worked in a research group involved in the execution, electrical characterization

and documentation of an in-situ gate stack process that fabricates thin gate dielectric capacitors

o Motorola – Austin, TX summer internship: − Enhanced a MS Excel macro to become compatible with the changes made in

yield enhancement in the R&D department, and execution of bitmap overlay was conducted to acquire information on how many electrical defects were caused by physical defects on silicon wafers

− Project provided more efficiency and improved yield analysis for the yield engineers

o Summer 1998 o Four Dimensions, Inc. Internship: acquired knowledge on every facet of the

operation of the CV Map 92A Hg Probe Station in an effort to facilitate tool ownership once the Hg Probe came to North Carolina State University

o August 1998 to January 2001 o Started Ph.D. program o Worked with the same research group to address the potential of extending the C-

V and I-V mapping capabilities of the Hg-probe system to thin silicon oxides and alternative gate dielectrics


Undergraduate Student, University of Texas, Austin, TX; 1990 to 1996: Undergraduate Research/Summer Internships o Spring Semester 1993 o Undergraduate Research: Texas Research Experience (TREX) Program o Design and Construct an apparatus to house four oxidation furnaces used for

annealing purposes o First exposure to a microelectronics cleanroom

o Summer 1994 o Undergraduate Research: Excellence Through Engineering (EXCELL) Program o Conducted research on a negative output resistance voltage source (NORVS) that

demonstrates positive load line characteristics used to examine the hysteresis of I-V curves of double barrier resonant tunneling diodes (DBRTDs)

o Tested the functionality and sensitivity of the NORVS o Acquired some theoretical knowledge on the DBRTD and its quantum mechanical

operation (particle as a wave, Schödinger Equation, etc.)

o Academic year 1994-95 o Texas Research Experience (TREX) Program o Conducted research or acquired knowledge on TEM sample prep, chemical

etching to expose crystal defects in wafers, and Remote Plasma Chemical Vapor Deposition (RPCVD)

o Engaged in modifying a sealed glove box that was used to load wafers into RPCVD apparatus for the purpose of providing hydrogen passivation and wafer loading in a single ultra-clean inert gas environment to eliminate surface contamination improving interface quality and crystal morphology

o Summer 1995 o Research Experience for Undergraduates (REU) Program o Participated in the design, fabrication, and testing of n+/p single crystal

semiconductor solar cells with an individual concentration on metal/semiconductor junctions

o Learned about the design of experiments to minimize variability o Learned how to use a scanning electron microscope to view my metal-

semiconductor junctions o Learning about the theory of contact resistance, ohmic contacts, and movement of

current in a p-n junction

o Academic year 1995-96, Summer 1996 o Minority Access to Energy Related Careers o Designed and implemented a nitrogen-purged glovebox for oxide-free silicon

wafer surfaces for use in Ultra-High Vacuum Scanning Tunneling Microscopy (UHV-STM)

o Conducted summer research at Los Alamos National Laboratory in acoustic resonance spectroscopy (ARS) where imaging of objects in a waste drum was done using ARS


Honors and Awards The format of this section will be: the award in bold, the sponsor, the basis for award, and the date received. Corporate Excellence Award o SEMATECH Selection Committee o SEMATECH’s highest technical honor for pulse-based electrical characterization

techniques for the evaluation of high-k gate dielectrics. o 2004

National Member of the Year o National Society of Black Engineers (NSBE) selection committee o Exemplified the qualities looked for in an outstanding member of an ethnic,

professional engineering society. One national award is chosen annually from the entire student membership (which was approximately 10,000 members at this time).

o March 1996 Friar Society o Friar Society selection committee o Univ. of Texas – Austin’s most distinguished honor society based on significant

contributions to The University of Texas at Austin (Members include: Earl Campbell, U.S. Congressman J. J. Pickle, U. S. Congressman Jack Brooks, Congressman Lloyd Doggett, among others)

o March 1994 Chancellor’s African-American Leadership Award o NC State Chancellor’s Office o Given to the graduate student exhibiting effective leadership within the university

community who is nominated by graduate students, faculty, and administration at N.C. State

o Spring 1999 Presidential Leadership Award o UT Ex-Students Association on behalf of the President of The University o Given to only two seniors, must have demonstrated outstanding leadership

credentials and potential o April 1994

Outstanding Student Award o UT-Austin Cactus Yearbook selection committee o Outstanding contribution to the University, scholarship, leadership, awards and

honors received, participation in campus organizations/activities o February 1994

Student Leadership Award in the College of Engineering o Dean's Office selection committee o Leadership (organizations/activities--offices held and duties involved),

community service, and innovations as a student leader o February 1993


Regional Member of the Year o NSBE Region V Advisory Board selection committee o Exemplified the qualities looked for in an outstanding member of an ethnic,

professional engineering society. One regional award is chosen annually. o February 1996

North Carolina Alliance for Minority Participation (NCAMP) Most Outstanding Student o Program Coordinators o Demonstrated leadership and potential as a researcher through undergraduate

research opportunities provided by The University and the National Science Foundation with a desire to go to graduate school,.

o Fall 1995 Best All-Around Male Award o Texas Pan-Hellenic Council (UT-Austin chapter) o Nominated by a student and then voted on by African-American student body as

the male who most exemplifies the qualities and characteristics of ideal role model.

o April 1995 Eric Bradley Leadership Award o Texas Pan-Hellenic Council (UT-Austin chapter) o Nominated by a student and then voted on by African-American student body as

the person who most exemplifies the qualities and characteristics of ideal leader. o April 1995

Mr. Marquís o Alpha Kappa Alpha Sorority, Inc. (Delta Xi Chapter) o Voted on by the African-American student body as the male who most

exemplifies the qualities and characteristics of the best all-around male. o March 1995

Mr. GHS o Georgetown High School o Nominated by the faculty and then voted on by the student body as the male who

most exemplifies the qualities and characteristics of the best all-around male. o February 1990

Fellowships Graduate Engineering Education Fellowship, National Science Foundation , 1996-

1998 Engineering Research Center Fellowship, Center for Advanced Electronic Materials

Processes, NC State University, 1998-2000 Research Assistantship, Center for Advanced Electronic Materials Processes, NC

State University, 1998-1999 Numerous Undergraduate Scholarships, various sponsors, 1990-1996


Research Interests Electrical Characterization Methodologies Reliability Characterization Methodologies Solid State Device Physics Electrical properties of materials MOS modeling (quantum effects, etc.) Nanotechnology/Novel Nanoscale Device Technology Future Energy Needs (Renewable, low power operation, etc.)

Service – Professional Professional Affiliations o Senior Member, IEEE, since 2006 o Panel Reviewer, National Science Foundation, 2016 o Panel Reviewer, Defense Threat Reduction Agency, 2015 o Steering/Technical Program Committee Member, International Conference on

Microelectronic Test Structures, 2015 o Session Chair, IEEE International Symposium on the Physical and Failure

Analysis of Integrated Circuits (IPFA), 2014 o Technical Program Committee Member, IEEE Nano, 2014 o Technical Program Committee Member, IEEE International Integrated Reliability

Workshop, 2014 o Ex-officio Chair, IEEE Semiconductor Specialist Interface Conference, 2014 o Steering/Technical Program Committee Member, Workshop on Dielectrics in

Microelectronics (WoDiM), 2014 o General Chair, IEEE Semiconductor Specialist Interface Conference, 2013 o Technical Program Sub-Committee Chair (Transistor Sub-Committee), IEEE

International Reliability Physics Symposium, 2013 o High-k Dielectrics Discussion Group Co-Chair, IEEE International Reliability

Physics Symposium, 2013 o Technical Progam Chair, IEEE Semiconductor Specialist Interface Conference,

2012 o Technical Program Committee Member (Characterization/Reliability/Yield Sub-

Committee), IEEE International Electron Devices Meeting, 2012 o Steering/Technical Program Committee Member, Workshop on Dielectrics in

Microelectronics (WoDiM), 2012 o Technical Program Committee Co-Chair (Gate Dielectrics Sub-Committee),

IEEE International Reliability Physics Symposium, 2012 o High-k Dielectrics Discussion Group Co-Chair, IEEE International Reliability

Physics Symposium, 2012


o Technical Program Committee Member (Characterization/Reliability/Yield Sub-Committee), IEEE International Electron Devices Meeting, 2011

o Arrangements Chair, IEEE Semiconductor Specialist Interface Conference, 2011 o Technical Program Committee Member (Transistor Sub-Committee), IEEE

International Reliability Physics Symposium, 2011 o Technical Program Committee Member, IEEE Semiconductor Specialist Interface

Conference, 2010 o General Chair, IEEE International Integrated Reliability Workshop, 2010 o Technical Program Committee Member (Transistor Sub-Committee), IEEE

International Reliability Physics Symposium, 2010 o Technical Program Chair, IEEE International Integrated Reliability Workshop,

2009 o Audio/Visual Vice-Chair, IEEE International Reliability Physics Symposium,

2009 o Technical Program Committee Member, IEEE Semiconductor Specialist Interface

Conference, 2009 o Guest Editor, IEEE Transactions on Device and Materials Reliability, 2008-09 o High-Mobility Substrates II Session Chair, IEEE Semiconductor Specialist

Interface Conference, 2008 o Technical Program Vice-Chair, IEEE International Integrated Reliability

Workshop, 2008 o Technical Program Committee Member, IEEE International Integrated Reliability

Workshop, 2008 o Technical Program Committee Member, IEEE Semiconductor Specialist Interface

Conference, 2008 o Finance Chair, IEEE International Integrated Reliability Workshop, 2007 o Guest Editor, IEEE Transactions on Device and Materials Reliability, 2006-07 o Advanced Materials Session Chair, IEEE International Conference on Integrated

Circuit and Design Technology, 2007 o Technical Program Committee Member, IEEE International Conference on

Integrated Circuit and Design Technology, 2007 o Arrangements Chair, IEEE International Integrated Reliability Workshop, 2007 o Technical Program Committee Member, IEEE International Conference on

Integrated Circuit and Design Technology, 2006 o Arrangements Vice-Chair, IEEE International Integrated Reliability Workshop,

2006 o Audio/Visual Vice-Chair, IEEE International Reliability Physics Symposium,

2006 o Tutorials Vice-Chair, IEEE International Integrated Reliability Workshop, 2005

Reviewer for professional journals


o IEEE Transactions on Electron Devices o IEEE Electron Device Letters o IEEE Transactions on Device and Materials Reliability o Microelectronics Reliability o Microelectronics Engineering o Solid-State Electronics o Applied Physics Letters

Service – Internal to Organization University of Texas at Dallas o Electrical and Computer Engineering Department − Graduate Committee − Graduate Committee (Fall 2012 – Spring 2015) − Digital Systems PhD Qualifier Chair (Spring 2014) − Solid State Devices & Micro Systems Fabrication PhD Qualifier Committee

(Spr/Fall 2013)

o Materials Science and Engineering Department − Graduate Recruiting and Admissions Committee (Fall 2012 – Spring 2014) − Colloquium Committee (2013 – now) − Colloquium Committee Chair (Fall 2014 – Spring 2015) − MSEN Qualifying Exam Committee Chair (Fall 2015 – now) − MSEN Advanced Electrical Characterization Laboratory Director (Fall 2015 -

now)

o Campus-wide − African American Student Success Task Force (Fall 2013-now) − National Society of Black Engineers: Academic/Career Mentor to the UTD

Student Chapter (Fall 2013-now) − Undergraduate Success Scholars Program (2016)

SEMATECH o Technical Vitality Improvement Team − Reported directly to the Corporate Executes − Proposed ways in which SEMATECH stays technically viable to our member

companies and demonstrate technical leadership to the broader community o Change Management Team − Reported directly to the Corporate Executes − Proposed ways to facilitate the transition from Austin to Albany through

evaluation of best practices and developing solutions to ease business and technical issues related to the transition

o Corporate Excellence Award Committee − Evaluated and voted on submitted nominations for the Corporate Excellence

Award where selection criteria was based on exceptional activity that improved the ability of SEMATECH to meet its objectives; innovation or unique achievement that has significantly contributed to the semiconductor


industry; and/or exceptional performance, including performance above and beyond job description or expected complexity.

North Carolina State University o Various Search Committees for Faculty and Administrators

Selected List of Invited Publications/Presentations Invited Papers/Presentations

1. Invited paper: Chadwin D. Young, Dawei Heh, Arnost Neugroschel, Rino Choi, Byoung Hun Lee, and Gennadi Bersuker, “Electrical Characterization and Analysis Techniques for the High-κ Era,” Microelectronics Reliability, vol. 47, pp. 479-488, 2006.

2. Invited paper: C.D. Young, D. Heh, S. Nadkarni, R. Choi, J.J. Peterson, J. Barnett, B.H. Lee, and G. Bersuker, “Electron Trap Generation in High-k Gate Stacks by Constant Voltage Stress,” IEEE TDMR, 6, pp. 123-131, 2006.

3. Invited presentation: C. D. Young, R. Choi, D. Heh, A. Neugroschel, H. Park, C.Y. Kang, G. A. Brown, S.C. Song, B. H. Lee, and G. Bersuker, “Assessment of Process-Induced Damage in High-κ Transistors,” presented at ICICDT, 2006.

4. Invited presentation: Chadwin D. Young, Choi, Rino, Kang, Chang Yong, Bersuker, Gennadi, Heh, Dawei ,Lee, Byoung Hun, “Electrical Characterization Methodologies for the Assessment of High-κ Gate Dielectric Stacks,” Fall ECS, 2007.

5. Invited/Review paper: Chadwin D. Young, Dawei Heh, Rino Choi, Byoung Hun Lee, and Gennadi Bersuker, “Pulsed Id-Vg methodology and Its Application to the Electron Trapping Characterization of High-k Gate Dielectrics,” Journal of Semiconductor Technology and Science, 10, pp. 79-99, 2010.

6. Invited presentation: C. D. Young, K. Akarvardar, G. Bersuker, I. Ok, T. Ngai, K.-W. Ang, C. Hobbs, P. Kirsch, and R. Jammy, “Performance and Reliability Investigation of (110) and (100) Sidewall Oriented MugFETs,” presented at International Semiconductor Device Research Symposium, p. TP5-01, 2011.

7. Invited presentation: C. D. Young, “Applications of Mechanical Engineering in the Semiconductor Industry,” Seminar Lecture at Mississippi State University, 2011.

8. Invited presentation: C. D. Young, “Electrical Characterization of Process Induced Damage,” Invited Talk at International Semiconductor Manufacting Initiative CVD EPF, 2011.

9. Invited paper: C. D. Young, K. Akarvardar, K. Matthews, M. O. Baykan, J. Pater, I. Ok, T. Ngai, K.-W. Ang, M. Minakais, and G. Bersuker, "(Invited) Electrical Characterization and Reliability Assessment of Double-Gate FinFETs," ECS Transactions, vol. 50, pp. 201-206, 2013.

10. Invited presentation: C. D. Young, K. Akarvardar, K. Matthews, M. Baykan, J. Pater, I. Ok, T. Ngai, K. Ang, M. Minakais, G. Bersuker, C. Hobbs, P. Kirsch, and R. Jammy, " Electrical Characterization and Reliability Assessment of


Double-gate FinFETs," PRiME 2012 Fall Meeting of the Electrochemical Society, abst #2597, 2012.

11. Invited presentation: C. D. Young, K. Akarvardar, Z. Wang, A. Neugroschel, K. Matthews, S. Benton, and C. Hobbs, "Assessing the Reliability and Performance Impact on the Three-Dimensional Structure of Multigate Field Effect Transistor (MugFET)," in IEEE International Integrated Reliability Workshop, 2013.

12. Invited presentation: C. D. Young, K. Akarvardar, Z. Wang, J. Fine, T. Lundquist, S. Benton, and C. Hobbs, "The Importance of Advanced Electrical Characterization and Analysis for FinFET Evaluation," in Energy Material Nanotechology East Meeting, Beijing, China, 2013.

13. Invited presentation: C. D. Young, D. Siddharth, G. Gutierrez-Heredia, I. Mejia, S. Benton, and M. Quevedo-Lopez, "Electrical Characterization and Analysis of Threshold Voltage Instability in Zinc Oxide Thin-Film Transistors," presented at the Collaborative Conference on Materials Research (CCMR), Incheon/Seoul, South Korea, 2014.

14. Invited presentation: C. D. Young, A. Neugroschel, K. Majumdar, Z. Wang, K. Matthews, and C. Hobbs, "Bias Temperature Instability Investigation of Double-gate FinFETs," in IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2014.

15. Invited presentation: C. D. Young, "Electrical Characterization of Top-Gated Molybdenum Disulfide Capacitor Structures with High-k Dielectrics," presented at the 24th International Materials Research Congress, Cancun, Mexico, 2015.

16. Invited presentation: C. D. Young, P. Zhao, and P. Barrett-Bolshakov, "Investigating Capacitance-Voltage Measurements of Molybdenum Disulfide Capacitors with High Dielectric Constant Oxides," presented at the 5th Annual World Congress of Nano Science and Technology, Xi'an, China, 2015.

17. Invited Plenary Talk: C. D. Young, "Opportunities and Challenges for Current and Future Nano/Microelectronic Devices," presented at the 37th International Metallurgy and Materials Congress, Saltillo, Mexico, 2015.

Complete Listing of All Presentations/Publications: Peer Reviewed Publications

1. P. M. Zeitzoff, C. D. Young, G.A. Brown, and Y. Kim, “Correcting Effective Mobility Measurements for the Presence of Significant Gate Leakage Current” IEEE Electron Device Letters, Vol. 24, No. 4, pp. 275-277, 2003.

2. H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C.D. Young, P.M. Zeitzoff, J. Gutt, P. Lysaght, M. I. Gardner and R.W. Murto, “High-k Gate Stacks for Planar, Scaled CMOS Integrated Circuits,” Microelectronic Engineering, Vol. 69, No. 2-4, pp. 152-167 2003.

3. Yuegang Zhao, Chadwin D. Young, and George A. Brown, “How to Electrically Qualify High-k Gates,” Semiconductor International, vol. 26, No. 11, pp. 51-58, 2003.


4. Gennadi Bersuker, J. Barnett, N. Moumen, S. Stemmer, M. Agustin, B. Foran, C. D. Young, P. Lysaght, B. H. Lee, Peter M. Zeitzoff, and H. R. Huff, “Interfacial Layer-Induced Mobility Degradation in High-k Transistors,” Jap. J. of Applied Physics, 43, pp. 7899-7902, 2004.

5. Rino Choi, Byoung Hun Lee, Chadwin D. Young, Jang Hoan Sim, and Gennadi Bersuker, “Temperature effect of constant bias stress on MOSFET with HfSiON gate dielectric,” Jap. J. of Applied Physics, 44, pp. 2201-2204, 2005.

6. Jang Hoan Sim, Rino Choi, Byoung Hun Lee, Chadwin Young, and Gennadi Bersuker, “Trapping/de-trapping gate bias dependence of Hf-silicate dielectrics with poly and TiN gate electrode,” Jap. J. of Applied Physics, 44, pp.2420-2423, 2005.

7. Byoung Hun Lee, Chadwin Young, Rino Choi, JangHwan Sim, Gennadi Bersuker, “Transient Charging and Relaxation in High-k Gate Dielectrics and its Implications,” Jap. J. of Applied Physics, 44, pp.2415-2419, 2005.

8. C.D. Young, Y. Zhao, M. Pendley, B.H. Lee, K. Matthews, J.H. Sim, R. Choi, G.A. Brown, R.W. Murto, and G. Bersuker, ““Ultra-Short Pulse I-V Characterization of the Intrinsic Behavior of High-k Devices,” Jap. J. of Applied Physics, 44, pp.2437-2440, 2005.

9. Chadwin D. Young, Gennadi Bersuker, Yuegang Zhao, Jeff J. Peterson, Joel Barnett, George A. Brown, Jang H. Sim, Rino Choi, Byoung Hun Lee, and Peter Zeitzoff, “Probing Stress Effects in HfO2 Gate Stacks with Time Dependent Measurements,” Microelectronics Reliability, 45, pp. 806-810, 2005.

10. Patrick S. Lysaght, Jeff J. Peterson, Brendan Foran, Chadwin Young, Gennadi Bersuker and Howard R. Huff, “Physical and Electrical Characterization of Polysilicon vs. TiN Gate Electrodes for HfO2 Transistors,” MatSci in SemiProc, Vol 7, 2005.

11. H. Park, M. S. Rahman, C. Man, B. H. Lee, R. Choi, C. D. Young, and H. Hwang, "Improved interface quality and charge-trapping characteristics of MOSFETs with high-κ gate dielectric," IEEE Electron Device Letters, vol. 26, pp. 725-727, 2005.

12. J. H. Sim, S.C. Song, P.D. Kirsch, C. D. Young, R. Choi, G. Bersuker, D. L. Kwong and B. H. Lee, “ALD HfO2 thickness dependence on charge trapping characteristics in mobility enhancement,” Microelectronics Engineering, 80, pp. 218-221, 2005.

13. C.D. Young, P. Zeitzoff, G.A. Brown, G. Bersuker, B.H. Lee, and J.R. Hauser, “Intrinsic Mobility Evaluation of High-k Gate Dielectric Transistors Using Pulsed Id-Vg,” IEEE Electron Device Letters, 26, pp. 586-589, 2005.

14. H. R. Harris, R. Choi, J.H. Sim, C. Young, P. Majhi, B. H. Lee, G. Bersuker, “Electrical Observation of Deep Traps in High-k/Metal Gate Stack Transistors,” IEEE Electron Device Letters, 26, pp. 839-841, 2005.

15. Rino Choi, S. C. Song, C. D. Young, Gennadi Bersuker, and Byoung Hun Lee, “Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique,” Appl. Phys. Lett., 87, p122901 (2005)


16. G. Bersuker, P. Zeitzoff, J. H. Sim, B. H. Lee, R. Choi, G. Brown, and C. D. Young, "Mobility evaluation in transistors with charge-trapping gate dielectrics," Applied Physics Letters, vol. 87, pp. 042905, 2005.

17. Chadwin D. Young, Dawei Heh, Arnost Neugroschel, Rino Choi, Byoung Hun Lee, and Gennadi Bersuker, “Electrical Characterization and Analysis Techniques for the High-k Era,” Microelectronics Reliability, vol. 47, pp. 479-488, 2006.

18. D.Heh, E.Vogel, J.B.Berstein, C.D.Young, G.A.Brown, P.Y.Hung, A.Diebold, and G.Bersuker, “Electrical characterization of spatial distribution of trapping centers in HfO2/SiO2 gate stack,” IEEE Transactions on Electron Devices, 54, pp. 1322-1329, 2006.

19. G. Bersuker, P. S. Lysaght, C. S. Park, J. Barnett, C. D. Young, P. D. Kirsch, R. Choi, B. H. Lee, B. Foran, K. van Benthem, S. J. Pennycook, P. M. Lenahan and J. T. Ryan, “The effect of interfacial layer properties on the performance of Hf-based gate stack devices,” Journal of Applied Physics, 100, p. 094108, 2006.

20. H.K. Park, R. Choi, B.H. Lee, S.C. Song, M. Chang, C.D. Young, G. Bersuker, J.C. Lee and H. Hwang, “Decoupling of cold carrier effects in hot carrier reliability assessment of HfO2 gated nMOSFETs,” IEEE Electron Device Letters, 27, pp. 662-664, 2006.

21. H.-C. Wen, H. R. Harris, C. Young, H.Luan, H. Alshareef, K. Choi, D.-L. Kwong, P. Majhi, Gennadi Bersuker, and B. H. Lee, “On Oxygen Deficiency and Fast Transient Charge-Trapping Effects in High-k Dielectrics,” IEEE Electron Device Letters, 27, pp. 984-987, 2006.

22. D. Heh, C. Rino, C. D. Young, L. Byoung Hun, and G. Bersuker, "A Novel Bias Temperature Instability Characterization Methodology for High-k nMOSFETs," IEEE Electron Device Letters, 27, pp. 849-851, 2006.

23. C.D. Young, D. Heh, S. Nadkarni, R. Choi, J.J. Peterson, J. Barnett, B.H. Lee, and G. Bersuker, “Electron Trap Generation in High-k Gate Stacks by Constant Voltage Stress,” IEEE Transactions on Device and Materials Reliability, vol. 6, pp. 123-131, 2006.

24. R. Choi, C. D. Young, G. Bersuker, B. Hun Lee, and Y. Zhao, "Characterization and reliability measurement issues in devices with novel gate stack devices," Thin Solid Films, vol. 504, pp. 223-226, 2006

25. James Ehrstein, Curt Richter, Deane Chandler-Horowitz, Eric Vogel, Chadwin Young, Shweta Shah, Dennis Maher, Brendan Foran, P. Y. Hung, and Alain Diebold, “A Comparison of Thickness Values for Very Thin SiO2 Films by Using Ellipsometric, Capacitance-Voltage, and HRTEM Measurements,” Journal of the Electrochemical Society, vol. 153, pp.F12-F19, 2006.

26. C. Y. Kang, R. Choi, S. H. Bae, S. C. Song, M. M. Hussain, C. Young, D. Heh, G. Bersuker and B. H. Lee, “Transient bicarrier response in high-k dielectrics and its impact on transient charge effects in high-k complementary metal oxide semiconductor devices,” Applied Physics Letters, vol. 88, pp. 162905, 2006.

27. B. H. Lee, C. Y. Kang, P. Kirsch, D. Heh, C. D. Young, H. Park, J. Yang, G. Bersuker, S. Krishnan, R. Choi, and H.-D. Lee, "Electric-field-driven dielectric breakdown of metal-insulator-metal hafnium silicate," Applied Physics Letters, vol. 91, p. 243514, 2007.


28. M. Negara, C. Young, P. Majhi, W. Tsai, P. Hurley, “The influence of HfO2 film thickness on the interface state density and low field mobility of n channel HfO2/TiN gate MOSFETs,” Microelectronic Engineering, 84, pp. 1874-1877, 2007.

29. N. A. Chowdhury, D. Misra, G. Bersuker, C. Young, and R. Choi, "Role of Interfacial Layer on Breakdown of TiN/High-kappa Gate Stacks," Journal of The Electrochemical Society, vol. 154, pp. G298-G306, 2007.

30. D. Heh, C. D. Young, C. Rino, and G. Bersuker, "Extraction of the Threshold-Voltage Shift by the Single-Pulse Technique," IEEE Electron Device Letters, vol. 28, pp. 734-736, 2007.

31. D. Heh, C. D. Young, and G. Bersuker, "Experimental Evidence of the Fast and Slow Charge Trapping/Detrapping Processes in High- k Dielectrics Subjected to PBTI Stress," IEEE Electron Device Letters, vol. 29, No. 2, pp. 180-182, 2008.

32. C. D. Young, G. Bersuker, J. Tun, R. Choi, D. Heh, and B.H. Lee, “ “Smart” TDDB Algorithm for Investigating Degradation in High-k Gate Dielectric Stacks under Constant Voltage Stress,” Microelectronic Engineering, pp. 287-290, 2008.

33. N. A. Chowdhury, G. Bersuker, C. Young, R. Choi, S. Krishnan, and D. Misra, "Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks," Microelectronic Engineering, vol. 85, pp. 27-35, 2008.

34. P. D. Kirsch, P. Sivasubramani, J. Huang, C. D. Young, M. A. Quevedo-Lopez, H. C. Wen, H. Alshareef, K. Choi, C. S. Park, K. Freeman, M. M. Hussain, G. Bersuker, H. R. Harris, P. Majhi, R. Choi, P. Lysaght, B. H. Lee, H. H. Tseng, R. Jammy, T. S. Boscke, D. J. Lichtenwalner, J. S. Jur, and A. I. Kingon, "Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning," Applied Physics Letters, vol. 92, p. 092901, 2008.

35. S.-H. Lee, P. Majhi, J. Oh, B. Sassman, C. Young, A. Bowonder, W.-Y. Loh, K.-J. Choi, B.-J. Cho, H.-D. Lee, P. Kirsch, H. R. Harris, W. Tsai, S. Datta, T. Hsing-Huang, S. K. Banerjee, and R. Jammy, "Demonstration of Lg ~ 55 nm pMOSFETs With Si/Si0.25Ge0.75/Si Channels, High Ion/Ioff (> 5 × 104), and Controlled Short Channel Effects (SCEs)," IEEE Electron Device Letters, vol. 29, pp. 1017-1020, 2008.

36. N. A. Chowdhury, X. Wang, G. Bersuker, C. Young, N. Rahim, and D. Misra, "Temperature dependent time-to-breakdown (TBD) of TiN/HfO2 n-channel MOS devices in inversion," Microelectronics Reliability, vol. 49, pp. 495-498, 2009.

37. Chadwin D. Young, Ji-Woon Yang, Kenneth Matthews, Sagar Suthram, Muhammad Mustafa Hussain, Gennadi Bersuker, Casey Smith, Rusty Harris, Rino Choi, Byoung Hun Lee, and Hsing-Huang Tseng, “Hot carrier degradation in HfSiON/TiN fin shaped field effect transistor with different substrate orientations,” J. Vac. Sci. Technol. B, 27, No. 1, pp. 468-471, 2009.

38. M. A. Negara, K. Cherkaoui, P. K. Hurley, C. D. Young, P. Majhi, W. Tsai, D. Bauza, and G. Ghibaudo, "Analysis of electron mobility in HfO2/TiN gate metal-oxide-semiconductor field effect transistors: The influence of HfO2 thickness, temperature, and oxide charge," Journal of Applied Physics, vol. 105, p. 024510, 2009.


39. C. D. Young, G. Bersuker, J. Tun, R. Choi, D. Heh, and B. H. Lee, "“Smart” TDDB algorithm for investigating degradation in high-κ gate dielectric stacks under constant voltage stress," Microelectronic Engineering, vol. 86, pp. 287-290, 2009.

40. C. D. Young, Y. Zhao, D. Heh, R. Choi, B. H. Lee, and G. Bersuker, "Pulsed Id - Vg Methodology and Its Application to Electron-Trapping Characterization and Defect Density Profiling," IEEE Transactions on Electron Devices, vol. 56, no. 6, pp. 1322-1329, 2009.

41. C. D. Young, A. Neugroschel, K. Matthews, C. Smith, D. Heh, H. Park, M. M. Hussein, and G. Bersuker, “Gated Diode Investigation of Bias Temperature Instability in High-k FinFETs,” IEEE Electron Device Letters, vol. 31, pp. 653-665, 2010.

42. C. D. Young, D. Veksler, S. Rumyantsev, J. Huang, H. Park, W. Taylor, M. Shur, and G. Bersuker, "Evaluation of the N- and La-induced defects in the high-κ gate stack using low frequency noise characterization," Microelectronic Engineering, vol. 88, pp. 1255-1258, 2011.

43. J.T. Ryan, R.G. Southwick, J.P. Campbell, K.P. Cheung, C.D. Young, and J.S. Suehle, “Experimentally Based Methodology for Charge Pumping Bulk Defect Trapping Correction,” 2011 IEEE International Integrated Reliability Workshop Final Report, 2011.

44. J.T. Ryan, R.G. Southwick, J.P. Campbell, K.P. Cheung, C.D. Young, and J.S. Suehle, “On the ‘U-Shaped’ Continuum of Band Edge States at the Si/SiO2 Interface,” Applied Physics Letters, 99, 223516, 2011.

45. C. D. Young, K. Akarvardar, M. O. Baykan, K. Matthews, I. Ok, T. Ngai, K. W. Ang, J. Pater, C. E. Smith, M. M. Hussain, P. Majhi, and C. Hobbs, "(110) and (100) Sidewall-oriented FinFETs: A performance and reliability investigation," Solid-State Electronics, vol. 78, pp. 2-10, 2012

46. M. O. Baykan, C. D. Young, K. Akarvardar, P. Majhi, C. Hobbs, P. Kirsch, R. Jammy, S. E. Thompson, and T. Nishida, "Physical insights on comparable electron transport in (100) and (110) double-gate fin field-effect transistors," Applied Physics Letters, vol. 100, p. 123502, 2012

47. K. Akarvardar, C. D. Young, M. O. Baykan, I. Ok, T. Ngai, K. W. Ang, M. P. Rodgers, S. Gausepohl, P. Majhi, C. Hobbs, P. D. Kirsch, and R. Jammy, "Impact of fin doping and gate stack on FinFET (110) and (100) electron and hole mobilities," IEEE Electron Device Letters, vol. 33, pp. 351-353, 2012

48. C. D. Young, K. Akarvardar, K. Matthews, M. O. Baykan, J. Pater, I. Ok, T. Ngai, K.-W. Ang, M. Minakais, and G. Bersuker, "(Invited) Electrical Characterization and Reliability Assessment of Double-Gate FinFETs," ECS Transactions, vol. 50, pp. 201-206, 2013.

49. J. P. Rojas, M. T. Ghoneim, C. D. Young, and M. M. Hussain, "Flexible High-κ/Metal Gate Metal/Insulator/Metal Capacitors on Silicon (100) Fabric," IEEE Transactions on Electron Devices, vol. 60, pp. 3305-3309, 2013.

50. M. E. Ramón, T. Akyol, D. Shahrjerdi, C. D. Young, J. Cheng, L. F. Register, and S. K. Banerjee, "Fast and slow transient charging in various III-V field-effect transistors with atomic-layer-deposited-Al 2 O 3 gate dielectric," Applied Physics Letters, vol. 102, pp. 022104-022104-5, 2013.


51. D.-H. Kim, T.-W. Kim, R. J. Hill, C. D. Young, C. Y. Kang, C. Hobbs, P. Kirsch, J. A. del Alamo, and R. Jammy, "High-Speed E-Mode InAs QW MOSFETs With Insulator for Future RF Applications," IEEE Electron Device Letters, vol. 34, pp. 196-198, 2013.

52. Y. Gao, D. Ang, G. Bersuker, and C. Young, "Electron Trap Transformation Under Positive-Bias Temperature Stressing," IEEE Electron Device Letters, vol. 34, pp. 351-353, 2013.

53. J. Conde, I. Mejia, F. Aguirre-Tostado, C. Young, and M. Quevedo-Lopez, "Design considerations for II–VI multi-gate transistors: the case of cadmium sulfide," Semiconductor Science and Technology, vol. 29, p. 045006, 2014.

54. G. X. Duan, C. X. Zhang, E. X. Zhang, J. Hachtel, D. M. Fleetwood, R. D. Schrimpf, et al., "Bias Dependence of Total Ionizing Dose Effects in SiGe-SiO2/ HfO2 pMOS FinFETs," IEEE Transactions on Nuclear Science, vol. 61, pp. 2834-2838, 2014.

55. G. Jiao, J. Lu, J. Campbell, J. Ryan, K. P. Cheung, C. Young, et al., "Device-Level Experimental Observations of NBTI-Induced Random Timing Jitter," IEEE Transactions on Device and Materials Reliability, vol. 14, pp. 972-977, 2014.

56. J. Lu, G. Jiao, C. Vaz, J. P. Campbell, J. T. Ryan, K. P. Cheung, et al., "PBTI-Induced Random Timing Jitter in Circuit-Speed Random Logic," Electron Devices, IEEE Transactions on, vol. 61, pp. 3613-3618, 2014.

57. M. T. Ghoneim, J. P. Rojas, C. D. Young, G. Bersuker, and M. M. Hussain, "Electrical Analysis of High Dielectric Constant Insulator and Metal Gate Metal Oxide Semiconductor Capacitors on Flexible Bulk Mono-Crystalline Silicon," IEEE Transactions on Reliability, vol. 64, pp. 579-585, 2015.

58. C. D. Young, A. Neugroschel, K. Majumdar, K. Matthews, Z. Wang, and C. Hobbs, "Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors," Journal of Applied Physics, vol. 117, p. 034501, 2015.

59. P. Zhao, P. Vyas, S. McDonnell, P. Bolshakov-Barrett, A. Azcatl, C. Hinkle, P. Hurley, R. Wallace, and C.D. Young, "Electrical characterization of top-gated molybdenum disulfide metal–oxide–semiconductor capacitors with high-k dielectrics," Microelectronic Engineering, vol. 147, pp. 151-154, 2015.

60. C. Young, "Channel Mobility," in High Permittivity Gate Dielectric Materials, ed: Springer Berlin Heidelberg, 2013, pp. 283-308.

61. K. Akarvardar, C. D. Young, M. O. Baykan, and C. C. Hobbs, "Understanding the FinFET Mobility by Systematic Experiments," in Toward Quantum FinFET, ed: Springer International Publishing, 2013, pp. 55-79.

62. C. D. Young and G. Bersuker, "PBTI in High-k Oxides," in Bias Temperature Instability for Devices and Circuits, ed: Springer New York, 2014, pp. 585-596.

Peer Reviewed Conferences/Publications

1. C. Young, B. Barnes, S. Castro, E. Condon, K. Koh, M. Schrader, S. Shah, K. Williamson, M. Xu, R. Kuehn, D. Maher, D. Venables, A. Oberhofer, G. Wang,


and J. Chen, “University and Small Firm Collaboration for Process Development of Advanced Gate Dielectrics,” Proceedings of 13th Biennial University/Government/Industry Microelectronics Symposium, pp. 64-72, 1999.

2. A. Oberhofer, J. Chen, K. Koh, M. Schrader, S. Shah, R. Venables, C. Young, M. Xu, R. Kuehn, D. Maher and D. Venables, “Process Definition for Obtaining Ultra-thin Silicon Oxides Using Full-wafer Electrical and Optical Measurements,” MRS Symposium Proceedings on Ultra-thin SiO2 Materials and High-K Dielectrics, (edited by H. Huff, C. Richter, M. Green, G. Lucovsky and H. Hattori) Volume 567, pp. 573-578 ,1999.

3. Zhigang Wang, Dexter W. Hodge, Shengqiang Wang, Wenmei Li, Chad Young, Robert T. Croswell, John R. Hauser, “Characterization of Ultrathin Oxide Interfaces (Tox < 1 nm) in Oxide-Nitride Stack Formed by Remote Plasma Enhanced Chemical Vapor Deposition,” 4th International Symposium: Physics and Chemistry of SiO2 and the Si-SiO2 Interface at the 197th Meeting of the Electrochemical Society, (edited by H. Z. Massoud, I. Baumvol, M. Hirose, E. H. Poindexter), pp. 209-216, 2000.

4. Chadwin Young, George A. Brown and Howard R. Huff, “Revisiting Electrical Characterization Concerns for Sub-2 nm EOT Gate Dielectrics on Silicon,” MRS International Workshop on Device Technology: Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, p. 7, 2001.

5. Avinash K. Agarwal, Chan Lim, Craig Metzner, Shreyas Kher, George A. Brown, Chadwin Young, Robert Murto, and Howard Huff, “Growth of Sub-1 nm EOT Gate Quality ZrO2 and HfO2 Films by MOCVD Using TDEAZ and TDEAH Precursors,” MRS International Workshop on Device Technology: Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, p. 12, 2001.

6. H.R. Huff, A. Agarwal, Y. Kim, L. Perrymore, D. Riley, J. Barnett, C. Sparks, M. Freiler, G. Gebara, B. Bowers, P.J. Chen, P. Lysaght, B. Nguyen, J.E. Lim, S. Lim, G. Bersuker, P. Zeitzoff, G.A. Brown, C. Young, B. Foran, F. Shaapur, A. Hou, C. Lim, H. Alshareef, S. Borthakur, D.J. Derro, R. Bergmann, L.A. Larson, M.I. Gardner, J. Gutt, R.W. Murto, K. Torres, and M.D. Jackson, “Integration of High-k Gate Stack Systems into Planar CMOS Process Flows,” International Workshop on Gate Insulator Program, pp. 1-10, 2001.

7. Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J.E. Lim, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G.A. Brown, C.D. Young, S. Borthakur, H. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. Murto, A. Hou, H.R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, “Conventional n-channel MOSFET Devices Using Single Layer HfO2 and ZrO2 as High-k Gate Dielectrics with Polysilicon Gate Electrode,” IEEE International Electron Devices Meeting (IEDM), pp. 20.2.1-4, 2001.

8. H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C.D. Young, P. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner, and R.W. Murto, “High-k Gate Stacks for Planar, Scaled CMOS Integrated Circuits,” Nano and Giga Challenges in Microelectronics, 2002.

9. Chan Lim, Yudong Kim, Alex Hou, Jim Gutt, Steven Marcus, Christophe Pomarede, Gennadi Bersurker, Joel Barnett, Chadwin Young, Peter Zeitzoff,


George A. Brown, Mark Gardner, Robert W. Murto, and Howard Huff, “Characteristics of ALCVDTM HfO2 grown using a modified Deposition Sequence for High-k Gate Stacks,” ALCVD™ Conference, 2002.

10. Chan Lim, Yudong Kim, Alex Hou, Jim Gutt, Steven Marcus, Christophe Pomarede, Eric Shero, Henk de Waard, Chris Werkhoven, Lee Chen, Jihane Tamim, Nirmal Chaudhary, Gennadi Bersurker, Joel Barnett, Chadwin Young, Peter Zeitzoff, George A. Brown, Mark Gardner, Robert W. Murto, and Howard Huff, “Effects of Deposition Sequence and Plasma Treatment on ALCVDTM HfO2 n-MOSFET Properties,” ECS Physics and Technology of High-k Gate Dielectrics I, PV 2002--28, pp. 83-92, 2002.

11. Pui Yee Hung, George A. Brown, Michelle Zhang, Joe Bennett, Husam N. Al-Shareef, Chadwin Young, Chris Oroshiba, and Alain Diebold, “Metrology Study of Sub 20Å Oxynitride by Corona-Oxide-Silicon (COS) and Conventional C – V Approaches,” MRS Spring Meeting, Vol. 716, B2.12, pp. 119-124, 2002.

12. Y. Kim, C. Lim, C.D. Young, K Matthews, J. Barnett, B. Foran, A. Agarwal, G.A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R.W. Murto, L. Larson, C. Metzner, S. Kher, and H.R. Huff, “Conventional Poly-Si Gate MOS-Transistors With a Novel, Ultra-Thin Hf-Oxide Layer,” Symposium on VLSI Technology, Session 12A-5, 2003.

13. C. D. Young, A. Kerber, T. H. Hou, E. Cartier, G. A. Brown, G. Bersuker, Y. Kim, C. Lim, J. Gutt, P. Lysaght, J. Bennett, C. H. Lee, S. Gopalan, M. Gardner, P. Zeitzoff, G. Groeseneken, R. W. Murto, and H. R. Huff, “Charge Trapping and Mobility Degradation in MOCVD Hafnium Silicate Gate Dielectric Stack Structures,” 203rd Fall Meeting of the Electrochemical Society, Physics and Technology of High-K Gate Dielectrics - II, October 12-16, 2003, Orlando, FL, PV 2003- 22, The Electrochemical Society Proceedings Series, Pennington, NJ (2003).

14. Chadwin D. Young, Gennadi Bersuker, George A. Brown, Chan Lim, Pat Lysaght, Peter Zeitzoff, Robert W. Murto, and Howard R. Huff, “Charge Trapping in MOCVD Hafnium-based Gate Dielectric Stack Structures and the Impact on Device Performance,” IEEE International Integrated Reliability Workshop Final Report, pp. 28-35, 2003.

15. Patrick S. Lysaght, Jeff J. Peterson, Brendan Foran, Chadwin Young, Gennadi Bersuker and Howard R. Huff, “Physical and Electrical Characterization of Polysilicon vs. TiN Gate Electrodes for HfO2 Transistors,” European Material Research Society Conference, 2004.

16. Chadwin D. Young, Gennadi Bersuker, George A. Brown, Patrick Lysaght, Peter Zeitzoff, Robert W. Murto, and Howard R. Huff, “Charge Trapping and Device Performance Degradation in MOCVD Hafnium-based Gate Dielectric Stack Structures,” IEEE International Reliability Physics Symposium (IRPS), pp. 597-598, 2004.

17. G. Bersuker, J. Gutt, N. Chaudhary, N. Moumen, B.H. Lee, J. Barnett, S. Gopalan, J. Peterson, H.-J. Li, P. M. Zeitzoff, G.A. Brown, Y. Kim, C. D. Young, J. H. Sim, P. Lysaght, M. Gardner, R. W. Murto, and H. R. Huff, “Integration Issues of High-K Gate Stack: Process-Induced Charging,” IEEE International Reliability Physics Symposium (IRPS), pp. 479-484, 2004.


18. Gennadi Bersuker, Peter M. Zeitzoff , Joel Barnett, Naim Moumen, Susanne Stemmer, Melody Agustin, Brendan Foran, Chadwin D. Young, Jeff Peterson, and Patrick Lysaght, “Interface-Induced Mobility Degradation in High-k Transistors,” IWDTF, 2004.

19. G. Bersuker, J.H. Sim, C. Young, R. Choi, P. Zeizoff, G. Brown, B.H. Lee, and R.A.Murto, “Effect of pre-existing defects on reliability assessment of high-k gate dielectrics,” ESREF, 2004.

20. G. Bersuker, J. Sim, C. Young, B.H. Lee, J. Barnett, N.Moumen, B. Foran, P.Lysaght, P.M. Zeitzoff and H.R. Huff, “High-k Gate Stack Interface Properties and Device Performance,” Nano and Giga Challenges in Microelectronics Conference, Krakow, Poland, 2004

21. P. Majhi, C. Young, G. Bersuker, H.C. Wen, G. Brown, B. Foran, R. Choi, P Zeitzoff, H. Huff, “Influence of Metal Gate Materials and it’s Processing on CMOS Device,” ESSDERC, 2004.

22. Chadwin D. Young, Gennadi Bersuker, Yuegang Zhao, Jeff J. Peterson, Joel Barnett, George A. Brown, Jang H. Sim, Rino Choi, Byoung Hun Lee, and Peter Zeitzoff, “Probing Stress Effects in HfO2 Gate Stacks with Time Dependent Measurements,” Workshop on Dielectrics in Microelectronics, 2004.

23. Joel Barnett, Chadwin D. Young, Naim Moumen, Gennadi Bersuker, Jeff J. Peterson, George A. Brown, Byoung Hun Lee, and Howard Huff, “Enhanced Surface Preparation Techniques for the Si/High-k Interface,” UCPSS, 2004.

24. Joel Barnett, N. Moumen, J. Gutt, M. Gardner, C. Huffman, P. Majhi, J.J. Peterson, S. Gopalan, B. Foran, H.-J. Li, B.H. Lee, G. Bersuker, P. M. Zeitzoff, G.A. Brown, P. Lysaght, C. Young, R.W. Murto, and H. R. Huff, “Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface,” Spring Meeting of the Electrochemical Society, vol. 811, p. E1.4, 2004.

25. Gennadi Bersuker, J. H. Sim, C. D. Young, R. Choi, B. H. Lee, P. Lysaght, G. A. Brown, P. M. Zeitzoff, M. Gardner, R. W. Murto and H. R. Huff, “Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance,” Spring Meeting of the Electrochemical Society, vol. 811, p. D2.6, 2004.

26. Byoung Hun Lee, Chadwin Young, Rino Choi, JangHwan Sim, George Brown, Gennadi Bersuker, “Transient charging in high-k gate dielectrics and its implications,” International Conference on Solid State Devices and Materials (SSDM), 2004.

27. Rino Choi, Byoung Hun Lee, Chadwin D. Young, Jang Hoan Sim, and Gennadi Bersuker, “Temperature effect of constant bias stress on MOSFET with HfSiON gate dielectric,” International Conference on Solid State Devices and Materials (SSDM), 2004.

28. Chadwin D. Young, Yuegang Zhao, Michael Pendley, Byoung Hun Lee, Kenneth Matthews, Jang Hoan Sim, Rino Choi, Gennadi Bersuker, and George A. Brown, “Ultra-Short Pulse I-V Characterization of the Intrinsic Behavior of High-k Devices,” International Conference on Solid State Devices and Materials (SSDM), 2004.

29. Jang Hoan Sim, Rino Choi, Byoung Hun Lee, Chadwin Young and Gennadi Bersuker, “Trapping/de-trapping gate bias dependence of Hf-silicate dielectrics


with poly and TiN gate electrode,” International Conference on Solid State Devices and Materials (SSDM), 2004.

30. Chadwin D. Young, Gennadi Bersuker, Huang-Chun Wen, George A. Brown and Prashant Majhi, “Charge Trapping Characteristics of Hafnium Based High-k Dielectrics with Various Metal Electrodes,” International Conference on Solid State Devices and Materials (SSDM), 2004.

31. James Gutt, George Brown, Chadwin Young, S.G. Park, and Yoshi Senzaki, “Low EOT Transistors Featuring ALD High-k Films from Hf-Based, Metal-Organic Precursors,” ALD Conference, 2004.

32. J.H. Sim, C. Young, G. Bersuker, B. H. Lee, R. Choi, G. A. Brown, K. Matthews and P. Tsui, “Electrical Evaluation for Advanced Gate Stack,” ISSM, 2004.

33. Jeff J. Peterson, George A. Brown, Ken Matthews, Jim Gutt, Sundar Gopalan, Hong-Jyh Li, Joel Barnett, Naim MoumenPrashant Majhi, Nirmal Chaudhary, Chadwin D. Young, Barry Sassman, Byoung-Hun Lee, Gennadi Bersuker, Peter M. Zeitzoff, Pat Lysaght, Mark Gardner and Howard R. Huff, “Towards 0.5 nm EOT Scaling of HfO2 / Metal Electrode Gate Stacks,” Spring Meeting of the Materials Research Society, 2004.

34. Yuegang Zhao, Chadwin D. Young, Michael Pendley, Kenneth Matthews, Byoung Hun Lee and George A. Brown, “Effective Minimization of Charge-trapping in High-k gate Dielectrics with an Ultra-short Pulse Technique,” ICSICT, 2004.

35. Rino Choi, B. H. Lee, C. D. Young, J. H. Sim, K. Mathews, G. Bersuker, P. Zeitzoff, “Effects of drain to gate stress on NMOSFET with polysilicon/Hf-silicate gate stack,” IEEE International Integrated Reliability Workshop Final Report, pp. 128-131, 2004.

36. H. Rusty Harris, Rino Choi, B. H. Lee, C. D. Young, J. H. Sim, K. Mathews, P. Zeitzoff, P. Majhi, and G. Bersuker, “Recovery of NBTI degradation in HfSiOx/Metal Gate Transistors,” IEEE International Integrated Reliability Workshop Final Report, pp. 132-135, 2004.

37. J. H. Sim, B. H. Lee, R. Choi, C. D. Young and G. Bersuker, “Hot carrier stress study in Hf-silciate NMOS transistors,” IEEE International Integrated Reliability Workshop Final Report, pp. 136-140, 2004.

38. Gennadi Bersuker, P. Zeitzoff, J. Sim, B. H. Lee, R. Choi, G. Brown, and C. Young, “Mobility Evaluation in High-K Devices,” IEEE International Integrated Reliability Workshop Final Report, pp. 141-143, 2004.

39. Jeff J. Peterson, Joel Barnett, Chadwin D. Young, George A. Brown, Jim Gutt, Sundar Gopalan, Paul D. Kirsch, Hong-Jyh Li, Naim Moumen, Byoung-Hun Lee, Pat Lysaght, Gennadi Bersuker, Peter M. Zeitzoff , Mark I. Gardner, Robert W. Murto, and Howard R. Huff, “Screening Oxide Effects in HfO2 High-k Gate Stacks,” Fall Meeting of the Materials Research Society, 2004.

40. B.H. Lee, C.D. Young, R. Choi, J.H. Sim, G. Bersuker, C.Y. Kang, H.R. Harris, G.A. Brown, K. Matthews, S.C. Song, N. Moumen, J. Barnett, P. Lysaght, K.S. Choi, H.C. Wen, C. Huffman, H. Alshareef, P. Majhi, S. Gopalan, J. Peterson, P. Kirsh, H.-J. Li, J. Gutt, M. Gardner, H.R. Huff, P. Zeitzoff, R.W. Murto, L. Larson, and C. Ramiller, “Intrinsic characteristics of high-k devices and


implications of transient charging effects,” IEEE International Electron Devices Meeting (IEDM), pp. 859-862, 2004.

41. Chang Yong Kang, R. Choi, J. H. Sim, C. Young, B. H. Lee, G. Bersuker and Jack C. Lee, “Charge Trapping Effects in HfSiON dielectrics on the Ring Oscillator Circuit and the Single Stage Inverter Operation,” IEEE International Electron Devices Meeting (IEDM), pp. 485-488, 2004.

42. C.D. Young, R. Choi, B.H. Lee, G. Bersuker, P. Zeitzoff, J.H. Sim, H.R. Harris, and G.A. Brown, “Characterizing Hf-Based Bulk Film Properties Using Ultra-short Pulse I-V Measurements,” IEEE Semiconductor Interface Specialist Conference, 2004.

43. Rino Choi, Rusty Harris, Byoung Hun Lee, K. Matthews, Mike Pendley, Chadwin Young, J. H. Sim, and G. Bersuker, “The frequency dependence of AC stress induced charging and it’s relaxation in TiN/Hf-Silicate NMOSFETs,” IEEE Semiconductor Interface Specialist Conference, 2004.

44. Jeff J. Peterson, Siddarth A. Krishnan, Chadwin D. Young, Byoung-Hun Lee, Joel Barnett, George A. Brown, Jim Gutt, Sundar Gopalan, Paul D. Kirscha, Hong-Jyh Li, Naim Moumena, Pat Lysaght, Gennadi Bersuker, Peter M. Zeitzoff , Mark I. Gardner, and Howard R. Huff, “The Role of Interfacial Oxides in Mobility Improvement in HfO2 Gate Stacks,” IEEE Semiconductor Interface Specialist Conference, 2004.

45. H. Park, M. S. Rahman, M. Chang, B. H. Lee, M. Gardner, C. D. Young and H. Hwang, “Effect of high pressure deuterium annealing on electrical and reliability characteristics of MOSFETs with high-k gate dielectric,” IEEE International Reliability Physics Symposium (IRPS), pp. 646-647, 2005.

46. Siddarth A. Krishnan, Jeff J. Peterson, Chadwin Young, George Brown, Rino Choi, Rusty Harris, Johnny Sim, Byoung Hun Lee, Peter Zeitzoff, Paul Kirsch, Jim Gutt, Hong Jyh Li, Ken Matthews, Jack C. Lee, and Gennadi Bersuker, “Dominant SILC Mechanisms in HfO2/TiN Gate nMOS and pMOS Transistors,” IEEE International Reliability Physics Symposium (IRPS), pp. 642-643, 2005.

47. H. Rusty Harris, Rino Choi, B. H. Lee, C. D. Young, J. H. Sim, K. Mathews, P. Zeitzoff, P. Majhi, and G. Bersuker, “Comparison of NMOS and PMOS stress for determining the source of NBTI in TiN/HfSiON devices,” IEEE International Reliability Physics Symposium (IRPS), pp. 80-83, 2005.

48. C.D. Young, R. Choi, J.H. Sim, B.H. Lee, P. Zeitzoff, Y. Zhao, K. Matthews, G.A. Brown, and G. Bersuker, “Interfacial Layer Dependence of HfSixOy Gate Stacks on Vt Instability and Charge Trapping Using Ultra-Short Pulse I-V Characterization,” IEEE International Reliability Physics Symposium (IRPS), pp. 75-79, 2005.

49. Rino Choi, R. Harris, B. H. Lee, C.D. Young, J.H. Sim, K. Matthews, M. Pendley and G. Bersuker, “Threshold Voltage Instability of HfSiO Dielectric MOSFET under AC Pulsed Stress,” IEEE International Reliability Physics Symposium (IRPS), pp. 634-635, 2005.

50. Rino Choi, B. H. Lee, C. D. Young, J. H. Sim, K. Mathews, G. Bersuker, P. Zeitzoff, “Implication of polarity dependence degradation on NMOSFET with polysilicon/Hf-silicate gate stack,” IEEE International Reliability Physics Symposium (IRPS), pp. 636-637, 2005.


51. J. H. Sim, B. H. Lee, S. C. Song, C. D. Young, R. Choi, H. Rusty Harris and G. Bersuker, “Hot carrier and cold carrier studies during stress in Hf-silciate NMOS transistors with Poly and TiN gate stack,” IEEE International Reliability Physics Symposium (IRPS), pp. 638-639, 2005.

52. Patrick S. Lysaght, Jeff J. Peterson, Brendan Foran, Chadwin Young, Gennadi Bersuker and Howard R. Huff, “Physical and Electrical Characterization of Polysilicon vs. TiN Gate Electrodes for HfO2 Transistors,” MatSci in SemiProc, Vol 7, 2005.

53. Jeff J. Peterson, Paul Kirsch, Gennadi Bersuker, Siddarth Krishnan, Prashant Majhi, Pat Lysaght, Manuel Quevedo-Lopez, Hong-Jyh Li, Yoshi Senzaki, Rusty Harris, Chadwin D. Young, Rino Choi, Johnny Sim, Joel Barnett, Naim Moumen, Craig Huffman, Mark I. Gardner, George A. Brown, Peter M. Zeitzoff, Byoung-Hun Lee, Chuck Ramiller, and Howard R. Huff, “TECHNOLOGY AND RELIABILITY CHALLENGES OF SUB-nm EOT HIGH-k / METAL GATE ELECTRODE TRANSISTORS,” Spring Meeting of the Electrochemical Society, 2005.

54. B.H. Lee, S. C. Song, C. Young, P. Kirsch, R.Choi, P.Lysaght, P.Majhi, G.Bersuker and C.Ramiller, “Challenges in the High-k Dielectric Implementation for 45nm Technology Node,” International Conference on Integrated Circuit Design and Technology, 2005.

55. J.H. Sim, S.C. Song, R. Choi, C.D. Young, G. Bersuker, S.H. Bae, D.L. Kwong and B. H. Lee, “Cold and Hot Carrier effects on HfO2 and HfSiO NMOSFETS with TiN gate electrode,” Device Research Conference (DRC), 2005.

56. P.D. Kirsch, J.H.Sim, S.C.Song, S. Krishnan, J.Gutt, J. Peterson, H.-J Li, M. Quevedo-Lopez, C.D.Young, R.Choi, J.Barnett, N.Moumen, K.Choi, C.Huffman, P.Majhi, Q. Wang, J. G. Ekerdt, M.Gardner, G.Brown, G.Bersuker and B.H.Lee, “Mobility Enhancement of High-k Gate Stacks Through Reduced Transient Charging,” European Solid-State Device Research Conference, 2005.

57. RINO CHOI, CHADWIN D. YOUNG, GENNADI BERSUKER, BYOUNG HUN LEE, “Characterization and Reliability Measurement Issues in Novel Gate Stack Devices,” ICMAT, 2005.

58. H.R. Harris, H.C. Wen, K. Choi, H. Alshareef, H. Luan, Y. Senzaki, C.D. Young, S.C. Song, Z. Zhang, G. Bersuker, P. Majhi and B.H. Lee, “Demonstration of High Performance Transistors with PVD Metal Gate,” European Solid-State Device Research Conference (ESSDERC), 2005.

59. M. Shahriar Rahman, Hokyung Park, Man Chang, Byoung Hun Lee,a, Rino Choi, Chadwin Young and Hyunsang Hwang, “Effect of high pressure H2-annealing followed by N2-annealing on reliability and performance of high-k MOSFET,” Device Research Conference, 2005.

60. B.H.Lee, R.Choi, C.Young, J.Sim and G.Bersuker, “Transient charging effects and its implication to the reliability of high-k dielectrics,” NATO Workshop, 2005.

61. S.A. Krishnan, M. Quevedo, R. Harris, P. D. Kirsch, R. Choi, B.H. Lee, G. Bersuker, J. Peterson, H-J. Li, C. Young, and J.C. Lee, “NBTI Dependence on Dielectric Thickness in Ultra-scaled HfSiO Dielectric/ ALD-TiN Gate Stacks,” International Conference on Solid State Devices and Materials (SSDM), 2005.


62. R. Choi, B. H. Lee, H. K. Park, C.D. Young, J.H. Sim, S.C. Song and G. Bersuker, “A novel inversion pulse measurement technique to investigate transient charging characteristics in high-k NMOS transistors,” International Conference on Solid State Devices and Materials (SSDM), 2005.

63. B. H. Lee, R. Choi, S.C. Song, J. Sim, C.D. Young, G. Bersuker, and H.K. Park and H. Hwang, “Physical origin of transient charge trapping in Hf based gate dielectrics,” International Conference on Solid State Devices and Materials (SSDM), 2005.

64. Hokyung Park, Rino Choi, Byung Hun Lee, Chadwin D. Young, Man Chang, Jack C. Lee and Hyunsang Hwang, “Stress voltage polarity dependent threshold voltage shift behavior of ultrathin Hafnium oxide gated pMOSFET with TiN electrode,” International Conference on Solid State Devices and Materials (SSDM), 2005.

65. G. Bersuker, J. Sim, C. Young, R. Choi, H. R. Harris, G. Brown, P. Zeitzoff, B. H. Lee, H. R. Huff, “Charge trapping effects in high-k transistors,” Fall Meeting of the Electrochemical Society, 2005.

66. C.D. Young, D. Heh, S. Nadkarni, R. Choi, J.J. Peterson, H.R. Harris, J.H. Sim, S.A. Krishnan, J. Barnett, E. Vogel, B.H. Lee, P. Zeitzoff, G.A. Brown, and G. Bersuker, “Trap Generation in High-k Gate Stacks,” IEEE International Integrated Reliability Workshop Final Report, pp. 79-83, 2005.

67. S.A. Krishnan, M.A. Q-Lopez, R. Choi, P. Kirsch, C. Young, R. Harris, J. Peterson, H.-J. Li, B.H. Lee and J.C. Lee, “Thickness Dependence of Charge Trapping in ultra-thin ALD-HfSiON/TiN Gate Stacks,” IEEE International Integrated Reliability Workshop Final Report, pp. 89-90, 2005.

68. R. Choi, B. H. Lee, K. Mathur, C.D. Young, G. Bersuker, Y. Zhao, “Fast relaxation behavior and its implication on the measurement in high-k gate dielectric,” IEEE Semiconductor Interface Specialist Conference, 2005.

69. S. A. Krishnan, M. Quevedo-Lopez, L. Hong-Jyh, P. Kirsch, R. Choi, C. Young, J. J. Peterson, L. Byoung Hun, G. Bersuker, and J. C. Lee, "Impact of Nitrogen on PBTI Characteristics of HfSiON/TiN Gate Stacks," in IEEE International Reliability Physics Symposium (IRPS), pp. 325-328, 2006.

70. C.D. Young, D. Heh, S. Nadkarni, H.R. Harris, R. Choi, J.J. Peterson, J.H. Sim, S.A. Krishnan, J. Barnett, E. Vogel, B.H. Lee, P. Zeitzoff, G.A. Brown, and G. Bersuker, “Detection of Electron Trap Generation Due to Constant Voltage Stress on High-κ Gate Stacks,” IEEE International Reliability Physics Symposium (IRPS), pp. 169-173, 2006.

71. G. Bersuker, J. Sim, C. S. Park, C. Young, S. Nadkarni, R. Choi, B. H. Lee, “Intrinsic Threshold Voltage Instability of the HfO2 Gate Stack NMOS Transistors,” IEEE International Reliability Physics Symposium (IRPS), pp. 179-183, 2006.

72. H. Park, R. Choi, S. C. Song, M. Chang, C. D. Young, G. Bersuker, B.H. Lee, J.C. Lee and H. Hwang, “Decoupling of cold carrier effects in hot carrier reliability of HfO2 gated nMOSFETs,” IEEE International Reliability Physics Symposium (IRPS), pp. 200-203, 2006.

73. C. Y. Kang, R. Choi, S. C. Song, C. D. Young, G. Bersuker, B. H. Lee, and J. C. Lee, “Carrier Recombination in High-k Dielectrics and its Impact on Transient


Charge Effects in High-k Devices,” IEEE International Reliability Physics Symposium (IRPS), pp. 657-658, 2006.

74. F. Palumbo,R. Pagano,S. Lombardo, S.A. Krishnan, C. Young, R. Choi, G. Bersuker, P. Kirsch,J. H. Stathis, “Evidence of progressive breakdown in high-k metal gate nFETs,” International Symposium on Advanced Gate Stack Technology, 2006.

75. G.Bersuker, A.Neugroschel, R.Choi, C.Cochrane, P.Lenahan, D.Heh, C.Young, C.Y.Kang, B.H.Lee and R.Jammy, “NBTI analysis methodology for high-k gate stacks,” IEEE Semiconductor Interface Specialist Conference, 2006.

76. C. Y. Kang, R. Choi, S. C. Song, K. Choi, B. S. Ju, M. M. Hussain, B. H. Lee, G. Bersuker, C. Young, D. Heh, P. Kirsch, J. Barnet, J-W. Yang, P. Zeitzoff, H-H Tseng, R. Jammy, “A novel electrode induced strain engineering for High performance SOI finFET utilizing Si(110) channel for both nMOS and pMOS,” IEEE International Electron Devices Meeting (IEDM), 2006.

77. A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C.Y. Kang, B.H. Lee, R. Jammy, “An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks,” IEEE International Electron Devices Meeting (IEDM), 2006.

78. S.A. Krishnan, R. Harris, P.D. Kirsch, C. Krug, M. Quevedo, C. Young, B.H. Lee, R. Choi, N. Chowdhury, S. Thomson, G. Bersuker, and R. Jammy, “Performance Enhancement of pMOSFETs with Optimized HfO2/TiN Gate Stack on Si(110) Substrates,” IEEE International Electron Devices Meeting (IEDM), 2006.

79. C. Y. Kang, R. Choi, S. H. Bae, S. C. Song, M. M. Hussain, C. Young, D. Heh, G. Bersuker and B. H. Lee, “Effects of Optimization of Gate Edge Profile on sub-45nm Metal Gate High-k Dielectric Metal-Oxide-Semiconductor Field Effect Transistors Characteristics,” International Conference on Solid State Devices and Materials (SSDM), 2006.

80. R. Choi, C.Y. Kang, S. Krishnan, G. Bersuker, C. Young, D. Heh, P. Kirsch, and B.H. Lee, “Process dependent transient charge trapping behaviors in HfSiO dielectric devices,” ALD Conference, 2006.

81. D.Heh, G.i Bersuker, R.Choi, C.D. Young, and B.H. Lee, “A Novel Bias Temperature Instability Characterization Methodology for High-k MOSFETs,” European Solid-State Device Research Conference (ESSDERC), 2006.

82. Invited: C. D. Young, R. Choi, D. Heh, A. Neugroschel, H. Park, C.Y. Kang, G. A. Brown, S.C. Song, B. H. Lee, and G. Bersuker, “Assessment of Process-Induced Damage in High-κ Transistors,” International Conference on Integrated Circuit Design and Technology, 2006.

83. D. Heh, R. Choi, C. D. Young, and G. Bersuker, "Fast and slow charge trapping/detrapping processes in high-k nMOSFETs," in IEEE International Integrated Reliability Workshop Final Report, pp. 120-124, 2006.

84. Dawei Heh, Paul D. Kirsch, Chadwin D. Young, Chang Yong Kang and Gennadi Bersuker, “Observation of Hole Trap Generation during PBTI Stress in nMOS High-k Devices,” IEEE International Integrated Reliability Workshop Final Report, pp. 103-106, 2007.


85. K. Choi, T. Lee, S. Kwon, C. D. Young, H. R. Harris, H.C. Wen, M. Q. Lopez, H. Park, N. Hiro, C. S. Park, R. Choi, S.C. Song, B.H. Lee, and R. Jammy, “Impact of the bottom interfacial layer on the threshold voltage and device reliability of fluorine incorporated PMOSFET with high-k/metal electrode,” IEEE International Reliability Physics Symposium (IRPS), pp. 374-377, 2007.

86. G. Bersuker, N. Chowdhury, C. Young, D. Heh, D. Misra, and R. Choi, "Progressive Breakdown Characteristics of High-K/Metal Gate Stacks," in IEEE International Reliability Physics Symposium (IRPS), pp. 49-54, 2007.

87. C. D. Young, G. Bersuker, F. Zhu, K. Matthews, R. Choi, S. C. Song, H. K. Park, J. C. Lee, and B. H. Lee, "Comparison of Plasma-Induced Damage in SiO2/TIN and HfO2/TIN Gate Stacks," in IEEE International Reliability Physics Symposium (IRPS), pp. 67-70, 2007.

88. P. Sivasubramani, T. S. Böscke, J. Huang, C. D. Young, P. D. Kirsch, S. A. Krishnan, M. A. Quevedo-Lopez, S. Govindarajan, B. S. Ju, H. R. Harris, D. J. Lichtenwalner, J. S. Jur, A. I. Kingon, J. Kim, B. E. Gnade, R. M. Wallace, G. Bersuker, B. H. Lee, and R. Jammy, “Dipole Moment Model Explaining nFET Vt Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics,” Symposium on VLSI Technology (VLSIT), pp. 2007.

89. R.Choi, “Reliability Assessment on Highly Manufacturable MOSFETs with Metal gate and Hf based gate dielectrics,” International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007.

90. Chadwin D. Young, Choi, Rino, Kang, Chang Yong, Bersuker, Gennadi, Heh, Dawei ,Lee, Byoung Hun, “Electrical Characterization Methodologies for the Assessment of High-k Gate Dielectric Stacks,” Fall Meeting of the Electrochemical Society, 2007.

91. Chadwin D. Young, Kenneth Matthews, Sagar Suthram, Muhammad Mustafa Hussain, Casey Smith, Rusty Harris, Rino Choi, and Hsing-Huang Tseng, “Hot Carrier Injection Study on Sidewall Surfaces of HfSiON/TiN FinFETs,” IEEE Semiconductor Interface Specialist Conference, 2007.

92. Pankaj Kalra, Prashant Majhi, Dawei Heh, Gennadi Bersuker, Chadwin Young, Nikhil Vora, Rusty Harris, Paul Kirsch, Rino Choi, Man Chang, Joonmyoung Lee, Hyunsang Hwang, Hsing-Huang Tseng, Rajarao Jammy, and Tsu-Jae King Liu, “Impact of Flash Annealing on the Performance and Reliability of High-κ/ Metal-Gate MOSFETs for sub-45 nm Technology,” IEEE International Electron Devices Meeting (IEDM), pp. 353-356, 2007.

93. P. Sivasubramani, P. Kirsch, J. Huang, C. Park, Y. Tan, D. Gilmer, C. Young, K. Freeman, M. Hussain, and R. Harris, "Aggressively scaled high-k gate dielectric with excellent performance and high temperature stability for 32nm and beyond," in IEEE International Electron Devices Meeting, IEDM 2007., pp. 543-546, 2007.

94. J. Huang, P. D. Kirsch, M. Hussain, D. Heh, P. Sivasubramani, C. Young, D. C. Gilmer, C. S. Park, Y. N. Tan, C. Park, H. R. Harris, P. Majhi, G. Bersuker, B. H. Lee, H. H. Tseng, and R. Jammy, "Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs," in International Symposium on VLSI Technology, Systems and Applications, pp. 152-153, 2008.


95. S. Suthram, H. R. Harris, M. M. Hussain, C. Smith, C. D. Young, J. W. Yang, K. Mathews, K. Freeman, P. Majhi, H. H. H. Tseng, R. Jammy, and S. E. Thompson, "Understanding Strain Effects on Double-Gate FinFET Drive-Current Enhancement, Hot-Carrier Reliability and Ring-Oscillator Delay Performance via Uniaxial Wafer Bending Experiments," in International Symposium on VLSI Technology, Systems and Applications, pp. 163-164, 2008.

96. Y. N. Tan, H. C. Wen, C. Park, D. C. Gilmer, C. D. Young, D. Heh, P. Sivasubramani, J. Huang, P. Majhi, P. D. Kirsch, B. H. Lee, H. H. Tseng, and R. Jammy, "Tunnel Oxide Dipole Engineering in TANOS Flash Memory for Fast Programming with Good Retention and Endurance," in International Symposium on VLSI Technology, Systems and Applications, pp. 54-55, 2008.

97. K. S. Min, C. Y. Kang, O. S. Yoo, B. J. Park, S. W. Kim, C. D. Young, D. Heh, G. Bersuker, B. H. Lee, and G. Y. Yeom, "Plasma induced damage of aggressively scaled gate dielectric (EOT < 1.0nm) in metal gate/high-k dielectric CMOSFETs," in IEEE International Reliability Physics Symposium (IRPS), pp. 723-724, 2008.

98. Kyong Taek Lee, Chang Yong Kang, Ook Sang Yoo, Chadwin D. Young, Gennadi Bersuker, Byoung Hun Lee, Hi-Deok Lee and Yoon-Ha Jeong, “A Comparative Study of Reliability and Performance of Strain Engineering Using CESL Stressor and Mechanical Strain,” IEEE International Reliability Physics Symposium (IRPS), pp. 306-309, 2008.

99. J. W. Yang, H. R. Harris, C. Y. Kang, C. D. Young, K. T. Lee, H. D. Lee, G. Bersuker, B. H. Lee, H. H. Tseng, and R. Jammy, "New hot-carrier degradation phenomenon in nano-scale floating body MOSFETS," in IEEE International Reliability Physics Symposium (IRPS), pp. 739-740, 2008.

100. Dawei Heh, Paul D. Kirsch, Chadwin D. Young, Chang Yong Kang and Gennadi Bersuker, “A new dielectric degradation phenomenon in nMOS high-k devices under positive bias stress,” IEEE International Reliability Physics Symposium (IRPS), pp. 347-351, 2008.

101. C. Y. Kang, C. S. Park, D. Heh, C. Young, P. Kirsch, H. B. Park, G, Bersuker, J.-W. Yang, B. H. Lee , J. Lichtenwalner J. S. Jur A. I. Kingon and R. Jammy, “Device Characteristics and Dielectric Reliability Characteristics of La-doped Hf-Silicate for Metal Gate/High-k nMOSFETs,” IEEE International Reliability Physics Symposium (IRPS), pp. 663-664, 2008.

102. J. Huang, P. D. Kirsch, J. Oh, S. H. Lee, J. Price, P. Majhi, H. R. Harris, D. C. Gilmer, D. Q. Kelly, P. Sivasubramani, G. Bersuker, D. Heh, C. Young, C. S. Park, Y. N. Tan, N. Goel, C. Park, P. Y. Hung, P. Lysaght, K. J. Choi, B. J. Cho, H. H. Tseng, B. H. Lee, and R. Jammy, "Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT," in Symposium on VLSI Technology, pp. 82-83, 2008.

103. W. Y. Loh, P. Majhi, S. H. Lee, J. W. Oh, B. Sassman, C. Young, G. Bersuker, B. J. Cho, C. S. Park, C. Y. Kang, P. Kirsch, B. H. Lee, H. R. Harris, H. H. Tseng, and R. Jammy, "The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Si1-xGex/Si p-MOSFETs with high-K/metal gate," in Symposium on VLSI Technology, pp. 56-57, 2008.


104. M. M. Hussain, K. Rader, C. Smith, C. Young, S. Suthram, C. Park, M. Cruz, P. D. Kirsch, and R. Jammy, “Additive Process Induced Strain (APIS) Technology for Lg = 30nm Band-Edge High-k/Metal Gate nMOSFET,” in International Conference on Solid State Devices and Materials (SSDM), 2008.

105. H. Park, G. Bersuker, C. Y. Kang, C. Young, H.-H. Tseng, and R. Jammy, "Effect of substrate hot carrier stress on high-k gate stack," in IEEE Integrated Reliability Workshop Final Report, pp. 44-47, 2008.

106. G. Bersuker, D. Heh, C. Young, H. Park, P. Khanal, L. Larcher, A. Padovani, P. Lenahan, J. Ryan, B. H. Lee, H. Tseng, and R. Jammy, "Breakdown in the metal/high-k gate stack: Identifying the"weak link" in the multilayer dielectric," in IEEE International Electron Devices Meeting (IEDM), pp. 791-794, 2008.

107. J. Huang, P. D. Kirsch, D. Heh, C. Y. Kang, G. Bersuker, M. Hussain, P. Majhi, P. Sivasubramani, D. C. Gilmer, N. Goel, M. A. Quevedo-Lopez, C. Young, C. S. Park, C. Park, P. Y. Hung, J. Price, H. R. Harris, B. H. Lee, H. H. Tseng, and R. Jammy, "Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application," in IEEE International Electron Devices Meeting (IEDM), pp. 45-48, 2008.

108. C. Y. Kang, C. D. Young, J. Huang, P. Kirsch, D. Heh, P. Sivasubramani, H. K. Park, G. Bersuker, B. H. Lee, H. S. Choi, K. T. Lee, Y. H. Jeong, J. Lichtenwalner, A. I. Kingon, H. H. Tseng, and R. Jammy, "The impact of La-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various gate stress conditions," in IEEE International Electron Devices Meeting (IEDM), pp. 115-118, 2008.

109. C.D. Young, G. Bersuker, J. Huang, D. Heh, C. Y. Kang, P. Sivasubramani, H. K. Park, P. Kirsch, and H.-H. Tseng, “Impact of La Incorporation on the Breakdown Characteristics of Hf-Based Gate Stacks,” IEEE Semiconductor Interface Specialists Conference, 2008.

110. M. E. Ramón, D. Shahrjerdi, C. D. Young, D. I. Garcia-Gutierrez, T. Akyol, and S. K. Banerjee, “Ultra-Short Pulsed I-V Characterization of GaAs Field-Effect Transistors with Al2O3 Gate Dielectric,” IEEE Semiconductor Interface Specialists Conference, 2008.

111. M.A. Negara, K. Cherkaoui, C.D. Young, P. Majhi, W. Tsai, D. Bauza, G. Ghibaudo, and P.K. Hurley, “Analysis of Electron Mobility in HfO2/TiN Gate MOSFETs: The Influence of HfO2 Thickness, Temperature, and Oxide Charge,” IEEE Semiconductor Interface Specialists Conference, 2008.

112. C. D. Young, G. Bersuker, P. Khanal, C. Y. Kang, J. Huang, C. S. Park, P. Kirsch, H. H. Tseng, and R. Jammy, "Reliability assessment of low |Vt| metal high-k gate stacks for high performance applications," in International Symposium on VLSI Technology, Systems, and Applications, 2009, pp. 65-66.

113. J. Huang, D. Heh, P. Sivasubramani, P. D. Kirsch, G. Bersuker, D. C. Gilmer, M. A. Quevedo-Lopez, M. M. Hussain, P. Majhi, P. Lysaght, H. Park, N. Goel, C. Young, C. S. Park, C. Park, M. Cruz, V. Diaz, P. Y. Hung, J. Price, H. H. Tseng, and R. Jammy, "Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application," in Symposium on VLSI Technology, pp. 34-35, 2009.


114. C. S. Park, M. M. Hussain, J. Huang, C. Park, K. Tateiwa, C. Young, H. K. Park, M. Cruz, D. Gilmer, K. Rader, J. Price, P. Lysaght, D. Heh, G. Bersuker, P. D. Kirsch, H. H. Tseng, and R. Jammy, "A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications," in Symposium on VLSI Technology, pp. 208-209, 2009.

115. S. Rumyantsev, C. Young, G. Bersuker, and M. Shur, “Low frequency noise in high-k dielectric MOSFETs: How far from the channel are we probing the traps?,” 20th International Conference on Noise and Fluctuations, ICNF 2009, June 14th-19th, 2009 Pisa, Italy, AIP Conf. proceedings, p.255, 2009.

116. G. Bersuker, D. Veksler, C.D. Young, H. Park, L.Morassi, A. Padovani, L. Larcher, W. Taylor, P. Kirsch and R. Jammy, “Connecting electrical and structural dielectric characteristics,” WOFE, 2009

117. D. Veksler, G. Bersuker, H. Park, C. Young, K. Y. Lim, W. Taylor, S. Lee, and H. Shin, “The critical role of the defect structural relaxation for interpretation of noise measurements in MOSFETs,” IEEE Integrated Reliability Workshop Final Report, pp. 102-105, 2009.

118. C. E. Smith, H. Adhikari, S. H. Lee, B. Coss, S. Parthasarathy, C. Young, B. Sassman, M. Cruz, C. Hobbs, P. Majhi, P. D. Kirsch, and R. Jammy, "Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node," in IEEE International Electron Devices Meeting (IEDM), pp. 1-4, 2009.

119. D. Veksler, G. Bersuker, S. Roumiantsev, H. Park, C. Young, K. Y. Lim, W. Taylor, M. Shur, and R. Jammy, “Understanding noise measurements in mosfets: the role of traps structural relaxation,” IEEE International Reliability Physics Symposium (IRPS), pp. 73-79, 2010.

120. G. Bersuker, D. Heh, C. D. Young, L. Morassi, A. Padovani, L. Larcher, K. S. Yew, Y. C. Ong, D. S. Ang, K. L. Pey, and W. Taylor, "Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer," IEEE International Reliability Physics Symposium (IRPS), pp. 373-378, 2010.

121. C. D. Young, A. Neugroschel, K. Matthews, C. Smith, H. Park, M. M. Hussain, P. Majhi, and G. Bersuker, “Improved interface characterization technique for high-k/metal gated MugFETs utilizing a gated diode structure,” in International Symposium on VLSI Technology, Systems, and Applications, pp. 68-69, 2010.

122. H. Park, G. Bersuker, M. Jo, D. Veksler, K. Y. Lim, D. Gilmer, N. Goel, C. Y. Kang, C. Young, M. Chang, H. Hwang, H. Tseng, P. D. Kirsch, and R. Jammy, “Tunnel oxide degradation in TANOS devices and its origin,” in International Symposium on VLSI Technology, Systems, and Applications, pp. 50-51, 2010.

123. I. Ok, C. D. Young, W. Y. Loh, T. Ngai, S. Lian, J. Oh, M. P. Rodgers, S. Bennett, H. O. Stamper, D. L. Franca, S. Lin, K. Akarvardar, C. Smith, C. Hobbs, P. Kirsch, and R. Jammy, "Enhanced performance in SOI FinFETs with low series resistance by aluminum implant as a solution beyond 22nm node," in 2010 Symposium on VLSI Technology (VLSIT), pp. 17-18, 2010.

124. I. Ok, K. Akarvardar, S. Lin, M. Baykan, C. D. Young, P. Y. Hung, M. P. Rodgers, S. Bennett, H. O. Stamper, D. L. Franca, J. Yum, J. P. Nadeau, C. Hobbs, P. Kirsch, P. Majhi, and R. Jammy, "Strained SiGe and Si FinFETs for high performance logic with SiGe/Si stack on SOI," in IEEE International Electron Devices Meeting (IEDM), pp. 34.2.1-34.2.4, 2010.


125. C. Hobbs, C. E. Smith, H. Adhikari, S. Lin, I. Ok, K. Akarvardar, S-H. Lee, B. Coss, C. D. Young, M. Cruz, P. Majhi and R. Jammy, “High Mobility SiGe Channel Non-Planar Devices,” 217th Spring Meeting of the Electrochemical Society, 2010.

126. D. Veksler, G. Bersuker, A. Koudymov, C. D. Young, M. Liehr, and B. Taylor, "Comprehensive analysis of charge pumping data for trap identification," in IEEE International Reliability Physics Symposium (IRPS), pp. GD.4.1-GD.4.5, 2011.

127. I. Ok, W. Y. Loh, K. W. Ang, C. D. Young, P. Y. Hung, T. Ngai, K. Akarvardar, C. Hobbs, and R. Jammy, "Parasitic resistance reduction technology," in 11th International Workshop on Junction Technology (IWJT), pp. 50-54, 2011.

128. C. D. Young, M. O. Baykan, A. Agrawal, H. Madan, K. Akarvardar, C. Hobbs, I. Ok, W. Taylor, C. E. Smith, M. M. Hussain, T. Nishida, S. Thompson, P. Majhi, P. Kirsch, S. Datta, and R. Jammy, "Critical discussion on (100) and (110) orientation dependent transport: nMOS planar and FinFET," in Symposium on VLSI Technology (VLSIT), pp. 18-19, 2011.

129. J.T. Ryan, R.G. Southwick, J.P. Campbell, K.P. Cheung, C.D. Young, and J.S. Suehle, “Experimentally Based Methodology for Charge Pumping Bulk Defect Trapping Correction,” In Press, 2011 IEEE International Integrated Reliability Workshop Final Report, 2011.

130. C. D. Young, K. Akarvardar, G. Bersuker, I. Ok, T. Ngai, K.-W. Ang, C. Hobbs, P. Kirsch, and R. Jammy, “Performance and Reliability Investigation of (110) and (100) Sidewall Oriented MugFETs,” presented at International Semiconductor Device Research Symposium, p. TP5-01, 2011.

131. C. D. Young, G. Bersuker, M. Jo, K. Matthews, J. Huang, S. Deora, K. W. Ang, T. Ngai, C. Hobbs, P. D. Kirsch, A. Padovani, and L. Larcher, "New insights into SILC-based life time extraction," in IEEE International Reliability Physics Symposium, 2012, pp. 5D.3.1-5D.3.5

132. D. Veksler, G. Bersuker, H. Madan, L. Vandelli, M. Minakais, K. Matthews, C. D. Young, S. Datta, C. Hobbs, and P. D. Kirsch, "Multi-technique study of defect generation in high-k gate stacks," in IEEE International Reliability Physics Symposium, 2012, pp. 5D.2.1-5D.2.5.

133. J. T. Ryan, R. G. Southwick, J. P. Campbell, K. P. Cheung, C. D. Young, and J. S. Suehle, "Spectroscopic charge pumping in the presence of high densities of bulk dielectric traps," in IEEE International Reliability Physics Symposium, 2012, pp. XT.1.1-XT.1.4.

134. T. Ngai, C. Hobbs, D. Veksler, K. Matthews, I. Ok, K. Akarvardar, K. W. Ang, J. Huang, M. P. Rodgers, S. Vivekanand, H. Li, C. Young, P. Majhi, S. C. Gausepohl, P. Kirsch, and R. Jammy, "Simple FinFET gate doping technique for dipole-engineered Vt tuning and CET scaling," in International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), 2012.

135. P. D. Kirsch, R. J. W. Hill, J. Huang, W. Y. Loh, T. W. Kim, M. H. Wong, B. G. Min, C. Huffman, D. Veksler, C. D. Young, K. W. Ang, I. Ali, R. T. P. Lee, T. Ngai, A. Wang, W. E. Wang, T. H. Cunningham, Y. T. Chen, P. Y. Hung, E. Bersch, B. Sassman, M. Cruz, S. Trammell, R. Droopad, S. Oktybrysky, J. C. Lee, G. Bersuker, C. Hobbs, and R. Jammy, "Challenges of III-V materials in


advanced CMOS logic," in International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), 2012.

136. T. W. Kim, R. J. W. Hill, C. D. Young, D. Veksler, L. Morassi, S. Oktybrshky, J. Oh, C. Y. Kang, D. H. Kim, J. A. Del Alamo, C. Hobbs, P. D. Kirsch, and R. Jammy, "InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax," in Symposium on VLSI Technology (VLSIT), pp. 179-180, 2012

137. S. Deora, G. Bersuker, C. D. Young, J. Huang, K. Matthews, K. W. Ang, T. Nagi, C. Hobbs, P. D. Kirsch, and R. Jammy, "PBTI improvement in gate last HfO2 gate dielectric nMOSFET due to Zr incorporation," in International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), 2012

138. K. Akarvardar, C. D. Young, D. Veksler, K. W. Ang, I. Ok, M. Rodgers, V. Kaushik, S. Novak, J. Nadeau, M. Baykan, H. Madan, P. Y. Hung, T. Ngai, H. Stamper, S. Bennett, D. Franca, M. Rao, S. Gausepohl, P. Majhi, C. Hobbs, P. Kirsch, and R. Jammy, "Performance and variability in multi-V T FinFETs using fin doping," in International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), 2012

139. I. Mejia, G. Gutierrez-Heredia, N. Hernandez-Como, C. D. Young, and M. A. Quevedo-Lopez, "Threshold Voltage Instability and Mobility Variation in Low Temperature ZnO-TFTs," in IEEE International Integrated Reliability Workshop, 2013.

140. C. D. Young, I. Mejia, M. T. Ghoneim, J. P. Rojas, M. Quevedo-Lopez, and M. M. Hussain, "(Invited) Reliability Investigation of Viable Device Structures for Future Flexible Electronic Applications," in International Semiconductor Device Research Symposium, 2013.

141. J. Fine, C. D. Young, T. Lundquist, and C.-C. Tsao, "Optical Probing of FinFETs," in IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2013.

142. C. Young, R. Hill, K. Matthews, W. Wang, C. Hinkle, R. Wallace, W. Loh, C. Hobbs, P. Kirsch, and R. Jammy, "Effect of ALD oxidant and channel doping on positive bias stress characteristics of surface channel In 0.53 Ga 0.47 As nMOSFETs," in VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on, 2013, pp. 1-2.

143. C. D. Young, K. Akarvardar, Z. Wang, A. Neugroschel, K. Matthews, S. Benton, and C. Hobbs, "(Invited) Assessing the Reliability and Performance Impact on the Three-Dimensional Structure of Multigate Field Effect Transistor (MugFET)," in IEEE International Integrated Reliability Workshop, 2013.

144. C. D. Young, K. Akarvardar, Z. Wang, J. Fine, T. Lundquist, S. Benton, and C. Hobbs, "(Invited) The Importance of Advanced Electrical Characterization and Analysis for FinFET Evaluation," in Energy Material Nanotechology East Meeting, Beijing, China, 2013.

145. G. Jiao, J. Lu, J. Campbell, J. Ryan, K. Cheung, C. Young, and G. Bersuker, "Circuit speed timing jitter increase in random logic operation after NBTI stress," in Reliability Physics Symposium, 2014 IEEE International, pp. 6B. 1.1-6B. 1.4, 2014.

146. J. W. Lu, C. Vaz, J. P. Campbell, J. T. Ryan, K. P. Cheung, G. F. Jiao, G. Bersuker, C.D. Young, "Device-Level PBTI-induced Timing Jitter Increase in


Circuit-Speed Random Logic Operation," in Dig. Tech. Papers 2014 Symp. VLSI Technol.,Honolulu, HI, Jun. 9-13, 2014, pp. T12.2.1-T12.2.2

147. D. Siddharth, G. Gutierrez-Heredia, I. Mejia, S. Benton, M. Quevedo-Lopez, and C. D. Young, "Investigation of Vt Instability in ZnO TFTs with an HfO2 Dielectric," presented at the Workshop on Dielectrics in Microelectronics, Cork, Ireland, 2014.

148. C. D. Young, D. Siddharth, G. Gutierrez-Heredia, I. Mejia, S. Benton, and M. Quevedo-Lopez, "(Invited) Electrical Characterization and Analysis of Threshold Voltage Instability in Zinc Oxide Thin-Film Transistors," presented at the Collaborative Conference on Materials Research (CCMR), Incheon/Seoul, South Korea, 2014.

149. C. D. Young, A. Neugroschel, K. Majumdar, Z. Wang, K. Matthews, and C. Hobbs, "(Invited) Bias Temperature Instability Investigation of Double-gate FinFETs," in IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2014.

150. G. X. Duan, C. X. Zhang, E. X. Zhang, J. Hatchtel, D. M. Fleetwood, R. D. Schrimpf, R. A. Reed, M. L. Alles, S. T. Pantelides, G. Bersuker, and C. D. Young, "Bias dependence of total ionizing dose effects in SiGe-SiO2/HfO2 pMOS FinFETs," oral presentation, IEEE NSREC, Paris, France, Jul. 2014.

151. D. Siddharth, P. Zhao, I. Mejia, S. Benton, M. Quevedo-Lopez, and C. D. Young, "Threshold Voltage Instabilities in Zinc Oxide Thin Film Transistors with High-k Dielectrics," presented at the International Integrated Reliability Workshop, 2014.

152. C. D. Young, "(Invited) Electrical Characterization of Top-Gated Molybdenum Disulfide Capacitor Structures with High-k Dielectrics," presented at the 24th International Materials Research Congress, Cancun, Mexico, 2015.

153. C. D. Young, P. Zhao, and P. Barrett-Bolshakov, "(Invited) Investigating Capacitance-Voltage Measurements of Molybdenum Disulfide Capacitors with High Dielectric Constant Oxides," presented at the 5th Annual World Congress of Nano Science and Technology, Xi'an, China, 2015.

154. C. D. Young, "(Invited Plenary Talk) Opportunities and Challenges for Current and Future Nano/Microelectronic Devices," presented at the 37th International Metallurgy and Materials Congress, Saltillo, Mexico, 2015.

155. J. A. Avila-Avendano, I. Mejia, C. D. Young, and M. A. Quevedo-Lopez, "Impact of Sulfur Diffusion in the Performance of CdTe-based Solar Cells Deposited by PLD," presented at the 24th International Materials Research Congress, Cancun, Mexico, 2015.

156. R. A. Rodriguez-Davila, I. Mejia, C. D. Young, and M. A. Quevedo-Lopez, "High Yield and Geometry-independent ZnO TFTs for Flexible Electronic Applications," presented at the 24th International Materials Research Congress, Cancun, Mexico, 2015.

157. P. Zhao, P. B. Vyas, S. McDonnell, P. Bolshakov-Barrett, A. Azcatl, C. Hinkle, R. M. Wallace, and C. D. Young, "Electrical Characterization of Top-Gated Molybdenum Disulfide Metal-Oxide-Semiconductor Capacitors With High-k Dielectrics," presented at the Insulating Films on Semiconductors (INFOS), Università degli Studi di Udine, 2015.


158. C. D. Young, R. Campbell, S. Daasa, S. Benton, R. Rodriguez-Davila, I. Mejia, and M. A. Quevedo-Lopez, "Effect of Dielectric Thickness and Annealing on Threshold Voltage Instability of Low Temperature Deposited High-k Oxides on ZnO TFTs," presented at the International Integrated Reliability Workshop, Fallen Leaf Lake, CA, 2015.

159. P. Zhao, A. Azcatl, P. Bolshakov-Barrett, P. K. Hurley, R. M. Wallace, and C. D. Young, "Top-Gated, Few-Layer MoS2 Field Effect Transistors with In-situ UV-Ozone Surface Functionalization and Sub-10nm HfO2 Dielectric," presented at the IEEE Semiconductor Interface Specialists Conference, Arlington, VA, 2015.

Presentations

1. Kwame N. Eason, Xiafang Zhang, Bao Vu, Michael Schrader, Chadwin Young, Shweta Shah, Kwangok Koh, Brian Taff, StephanieBogle, Dennis Maher, Alain Diebold, and Clive Hayzelden, “Ultra-thin Gate-thickness In line Monitoring: Correlation of Thickness Values Extracted from Quantox COS and MOS Capacitor Characteristics,” SEMI Technology Symposium (STS) Critical Technologies Conference, Gate Stack Engineering, SEMICON Southwest, pp. 69-76, 2001.

2. Chadwin D. Young, Gennadi Bersuker, and George A. Brown, “Charge Trapping Measurements and Their Application to High-k Gate Stack Evaluation,” Semiconductor Research Corporation’s Topical Research Conference on Reliability, October, 2003.

3. C.D. Young, R. Choi, B.H. Lee, P. Zeitzoff, J.H. Sim, G.A. Brown, and G. Bersuker, “Evaluation of intrinsic hafnium-based gate stack performance using ultra-short pulse I-V,” IEEE Electron Device Society Chapter Meeting, 2005.

4. C. D. Young, G. Bersuker, J. Tun, R. Choi, D. Heh, and B.H. Lee, “ “Smart” TDDB Algorithm for Investigating Degradation in High-k Gate Dielectric Stacks under Constant Voltage Stress,” 4th International Symposium on Advanced Gate Stack and Technology, 2008.

5. C.D. Young, “Tutorial: Measurement Issues for High-k Technology including NBTI,” IEEE Integrated Reliability Workshop, 2008.

6. D. Veksler, G. Bersuker, H. Park, C. Young, K. Y. Lim, W. Taylor, S. Lee, and H. Shin, “A comprehensive analysis of noise measurements in MOSFETs: the role of trap relaxation,” Invited Talk at the National Institute of Standards and Technology, 2009.

7. C. D. Young, “Applications of Mechanical Engineering in the Semiconductor Industry,” Invited Seminar Lecture at Mississippi State University, 2011.

8. C. D. Young, “Electrical Characterization of Process Induced Damage,” Invited Talk at International Semiconductor Manufacting Initiative CVD EPF, 2011.

9. C. D. Young, “Electrical Characterization of Process Induced Damage,” Invited Talk at the SEMATECH Taiwan Symposium, 2011.

10. C.D. Young, H. Barkat, S. Aman, and Z. Wang, “(Invited) Key Findings of Devices for Implementation Below the 22 nm Node,” Texas AVS Chapter Summer Conference, 2013.


11. Chadwin D. Young, Israel Mejia, Mohamed T. Ghoneim, Jhonathan P. Rojas, Manuel Quevedo-Lopez, and Muhammad M. Hussain, “Viable Device Structures for Future Flexible Electronic Applications: Initial Reliability Study,” National Institute of Standards and Technology, 2013.

12. R. Campbell, S. Daasa, S. Benton, R. R. Davila, I. Mejia, M. A. Quevedo-Lopez, and C. D. Young, "Effects of Annealing on Vt instability in Thin Film Transistors with Hafnium Oxide Gate Dielectrics," presented at the AVS Texas Chapter Summer Meeting, Richardson, TX, 2015.

13. C. D. Young, "Tutorial: Test Structure Considerations for Evaluating Future Materials and Devices Necessary for the Flexible Electronics Era," presented at the 28th IEEE International Conference on Microelectronic Test Structures, Tempe, AZ, 2015.

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