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Register Transfer & µ-operations

REGISTER TRANSFER AND MICROOPERATIONS

• Register Transfer Language

• Register Transfer

• Bus and Memory Transfers

• Arithmetic Microoperations

• Logic Microoperations

• Shift Microoperations

• Arithmetic Logic Shift Unit

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MICROOPERATION

An elementary operation performed during one clock pulse, on the information stored in one or more registers

R ← f (R, R)

f: shift, count, clear, load, add,...

ALU(f)

Registers(R)

1 clock cycle

Register Transfer Language

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REGISTER TRANSFER LANGUAGE (RTL)

The (internal) organization of a computer is defined by:

Register transfer language (RTL):

Any function of the computer can be described by a sequence of microoperations using RTL

Register Transfer Language

• Set of registers and their functions• Set of microoperations :

– Set of allowable microoperations provided by the organization of the computer

• Control signals that initiate the sequence of microoperations

• A symbolic language • A convenient tool for describing the internal organization of digital

computers• It is used to facilitate the design process of digital systems

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REGISTER TRANSFER

R1Register

Numbering of bits

Showing individual bits

SubfieldsPC(H) PC(L)

15 8 7 0

- a register- portion of a register- a bit of a register

Common ways of drawing the block diagram of a register

7 6 5 4 3 2 1 0

R215 0

Designation of a register

A simultaneous transfer of all bits from the source register to the destination register, during one clock pulse

R2 ← R1Representation of a (parallel) register transfer

A binary condition (P=1) which determines when the transfer is to occur If (P=1) then (R2 ← R1)

P: R2 ← R1Representation of a controlled (or conditional) register transfer

Register Transfer

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HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERSRegister Transfer

Implementation of controlled register transferP: R2 ← R1

Block diagramClockR2

R1

Control Circuit

LoadP

n

Timing diagram

Transfer occurs here

Clock

Load

t t+1

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BASIC SYMBOLS FOR REGISTER TRANSFERS

Capital letters Denotes a register MAR, R2and numerals

Parentheses ( ) Denotes a portion of a register R2(0-7), R2(L)

Arrow ← Denotes transfer of information R2 ← R1

Colon : Denotes termination of control function P:

Comma , Separates two micro-operations A ← B, B ← A

Symbols Description Meaning

Register Transfer

T: R2 ← R1, R1 ← R2Example:

ClockR2

R1

LoadTn

n

Load

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BUS AND MEMORY TRANSFER

The Bus is a data path (or a group of wires), over which information is transferred, from any of several sources to any of several destinations

From a register to the bus: BUS R

Register A Register B Register C Register D

Bus lines

Bus and Memory Transfers

x y Source Register Selected

0 0 A

0 1 B

1 0 C

1 1 DSource Selection

Register A Register B Register C Register D

4x1MUX

xy

0 1 2 3

0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3

A B C D1 1 1 B C D2 2 2 B C D3 3 3

4-line bus

4x1MUX

0 1 2 34x1MUX

0 1 2 34x1MUX

0 1 2 3

A A1 2 3

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BUS SYSTEM - ExampleRegister Transfer

Problem 4-6: A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers.a. How many selection inputs are there in each multiplexer?

b. What size of multiplexers are needed?

c. How many multiplexers are there in the bus?

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TRANSFER FROM BUS TO A DESTINATION REGISTERBus and Memory Transfers

2 x 4Decoder

Load

D0 D1 D2 D3zw

DestinationSelection E (enable)

Reg. R0 Reg. R1 Reg. R2 Reg. R3

Bus lines

From bus to a register: R BUS

E w z Destination Register Selected

0 x x None (no register is loaded)

1 0 0 R0

1 0 1 R1

1 1 0 R2

1 1 1 R3

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THREE-STATE BUS BUFFERS

Three-State Buffer


Bus line with three-state buffers

SourceSelection

Enable

0123

xy

A0B0C0D0

Bus line for bit 0

2x4 Dec

E

If C=1, then Y=A If C=0, then Y=High-impedance

Normal input AControl input C

Y

E x y Source Register Selected

0 x x None (Bus is disconnected)

1 0 0 A

1 0 1 B

1 1 0 C

1 1 1 D

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MEMORY UNIT

Logical Organization

Random Access Memory (RAM)- Each word has a unique address- Access to a word requires the same time

independent of the location of the word

Memory Components

2k Words(n bits/word)

n data input lines

n data output lines

k address lines

Read

Write

words(byte, or n bytes)

0

N - 1

- Organization

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MEMORY TRANSFERS

AR Memoryunit

Read

Write

DR

Memory read micro-op: DR ← M ( Read: DR ← M[AR] )

Memory write micro-op: M ← DR ( Write: M[AR] ← DR )


Address Register

Data Register

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SUMMARY OF REGISTER TRANSFER MICROOPERATIONS

A ← B Transfer the contents of register B into register A

AR ← DR(AD) Transfer the contents of AD portion of register DR into register AR

A ← constant Transfer a binary constant into register A

ABUS ← R1, Transfer the contents of R1 into bus A and, at the same time, R2 ← ABUS transfer the contents of bus A into R2

AR Address register

DR Data register

M[R] Memory word specified by register R

M Equivalent to M[AR]

DR ← M Memory read operation: transfers the contents of the memory word specified by AR into DR

M ← DR Memory write operation: transfers the contents of DR into the memory word specified by AR


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REGISTER TRANSFER MICROOPERATIONS - ExampleRegister Transfer

Problem 4-3: Represent the following conditional control statement by two register transfer statements with control functions.

If (P = 1) then (R1 ← R2) else if (Q = 1) then (R1 ← R3)

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TYPES OF MICROOPERATIONS

Four types of microoperations

- Register transfer microoperations- Arithmetic microoperations- Logic microoperations- Shift microoperations

Arithmetic Microoperations

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ARITHMETIC MICROOPERATIONSArithmetic Microoperations

R3 ← R1 + R2 Contents of R1 plus R2 transferred to R3R3 ← R1 - R2 Contents of R1 minus R2 transferred to R3R2 ← R2’ Complement the contents of R2 (1’s complement)R2 ← R2’ + 1 2's complement the contents of R2 (negate)R3 ← R1 + R2’ + 1 R1 plus the 2’s complement of R2 (subtraction)R1 ← R1 + 1 Increment the contents of R1 by oneR1 ← R1 - 1 Decrement the contents of R1 by one

P: R3 ← R1 + R2Example:

Clock

R3R1

Load

P

R2

n-bitAdder

n

n

n

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ARITHMETIC MICROOPERATIONS - ExampleRegister Transfer

Problem 4-10: Consider the following register transfer statements for two 4-bit registers R1 ands R2.

xT: R1 ← R1 + R2x’T: R1 ← R2

Draw a block diagram showing the hardware implementation of the two statements.

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BINARY ADDERArithmetic Microoperations

Binary AdderS = A + B

FA

B0 A0

S0

0FA

B1 A1

S1

C1FA

B2 A2

S2

C2FA

B3 A3

S3

C3

C4

Binary IncrementerS = A + 1 FA

0 A0

S0

1FA

0 A1

S1

C1FA

0 A2

S2

C2FA

0 A3

S3

C3

C4

Binary DecrementerS = A - 1

FA

1 A0

S0

0FA

1 A1

S1

C1FA

1 A2

S2

C2FA

1 A3

S3

C3

C4

Binary SubtractorS = A - B FA

B0 A0

S0

1FA

B1 A1

S1

C1FA

B2 A2

S2

C2FA

B3 A3

S3

C3

C4

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BINARY ADDER

Binary Incrementer

HAx y

C S

A0 1

S0

HAx y

C S

A1

S1

HAx y

C S

A2

S2

HAx y

C S

A3

S3C4

FA

B0 A0

S0

C0FA

B1 A1

S1

C1FA

B2 A2

S2

C2FA

B3 A3

S3

C3

C4

Binary Adder


Binary Adder-Subtractor

FA

B0 A0

S0

C0C1FA

B1 A1

S1

C2FA

B2 A2

S2

C3FA

B3 A3

S3C4

M

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ARITHMETIC CIRCUIT

S1 S0 Cin Y Output Microoperation0 0 0 B D = A + B Add0 0 1 B D = A + B + 1 Add with carry0 1 0 B’ D = A + B’ Subtract with borrow0 1 1 B’ D = A + B’+ 1 Subtract1 0 0 0 D = A Transfer A 1 0 1 0 D = A + 1 Increment A1 1 0 1 D = A - 1 Decrement A1 1 1 1 D = A Transfer A


S1S00123

4x1MUX

X1

Y1

C1

C2

D1FA

S1S00123

4x1MUX

X2

Y2

C2

C3

D2FA

S1S00123

4x1MUX

X3

Y3

C3

C4

D3FA

Cout

A1

B1

A2

B2

A3

B3

0 1

S1S00123

4x1MUX

X0

Y0

C0

C1

D0FA

A0

B0

S0S1Cin

01

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ARITHMETIC CIRCUIT - ExampleRegister Transfer

Problem 4-15: Design an arithmetic circuit with one selectionvariable S and two n-bit data inputs A and B. The circuit generatesthe following four arithmetic operations in conjunction with the inputcarry Cin. Draw the logic diagram for the first two stages.

S Cin = 0 Cin = 10 D = A + B D = A + 11 D = A – 1 D = A + B’ + 1

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LOGIC MICROOPERATIONS

Specify binary operations on the strings of bits in registers.

- useful for bit manipulations on binary data - useful for making logical decisions based on the bit value- Basic logic microoperations:

- AND: ∧ - OR: ∨ - XOR: ⊕ - complement

Logic Microoperations

P: R1 ← R1 ⊕ R2

1010 Content of R11100 Content of R20110 Content of R1 after P=1

P + Q: R1 ← R2 + R3, R4 ← R5 ∨ R6

OR operation

add microoperation

OR microoperation

R1

R2

ClockLoadP i

i

bit i in R1

bit i in R2

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LIST OF LOGIC MICROOPERATIONS

BooleanFunction

Micro-Operations Namex 0 0 1 1

y 0 1 0 1

Logic Microoperations

0 0 0 0 F0 = 0 F ← 0 Clear0 0 0 1 F1 = xy F ← A ∧ B AND0 0 1 0 F2 = xy' F ← A ∧ B’0 0 1 1 F3 = x F ← A Transfer A0 1 0 0 F4 = x'y F ← A’∧ B0 1 0 1 F5 = y F ← B Transfer B0 1 1 0 F6 = x ⊕ y F ← A ⊕ B Exclusive-OR0 1 1 1 F7 = x + y F ← A ∨ B OR1 0 0 0 F8 = (x + y)' F ← (A ∨ B)’ NOR1 0 0 1 F9 = (x ⊕ y)' F ← (A ⊕ B)’ Exclusive-NOR1 0 1 0 F10 = y' F ← B’ Complement B1 0 1 1 F11 = x + y' F ← A ∨ B’1 1 0 0 F12 = x' F ← A’ Complement A1 1 0 1 F13 = x' + y F ← A’∨ B1 1 1 0 F14 = (xy)' F ← (A ∧ B)’ NAND1 1 1 1 F15 = 1 F ← all 1's Set to all 1's

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HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONSLogic Microoperations

BA

SS

F

10

i

ii 0

1

2

3

4 X 1MUX

Select

0 0 F = A ∧ B AND0 1 F = A ∨ B OR1 0 F = A ⊕ B XOR1 1 F = A’ Complement

S1 S0 Output µ-operationFunction table

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APPLICATIONS OF LOGIC MICROOPERATIONSLogic Microoperations

- Selective-set

1010 A1100 B1110 A ← A ∨ B

- Selective-complement

1010 A1100 B0110 A ← A ⊕ B

- Selective-clear

1010 A1100 B0010 A ← A ∧ B

- Mask

1010 A1100 B1000 A ← A ∧ B

- Clear (produce 0 if A=B)

1010 A1010 B0000 A ← A ⊕ B

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- Insert: (Mask then OR)

APPLICATIONS OF LOGIC MICROOPERATIONSLogic Microoperations

1. Mask0110 1010 A before0000 1111 B (mask)

0000 1010 A after masking (A ← A ∧ B)

2. OR0000 1010 A before1001 0000 B (insert)

1001 1010 A after insertion (A ← A ∨ B)

Example: Register A contains eight bits (0110 1010), replace the four leftmost bits by 1001.

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SHIFT MICROOPERATIONSShift Microoperations

Shift Right

R0R1R2R3Rn-1Serial Input

R0R1R2R3Rn-1

Shift Left

Serial Output

- Logical shift : transfers 0 through the serial input- Circular shift : circulates the bits of the register around the two ends- Arithmetic shift : shifts a signed number (shift with sign extension)

Left shift multiplied by 2Right shift divided by 2

Shifts

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SHIFT MICROOPERATIONS

Logical Shift Right: R ← shr R

R0R1R2R3Rn-10

Logical Shift Left: R ← shl R

R0R1R2R3Rn-1 0

Shift Microoperations

Circular Shift Right: R ← cir R

R0R1R2R3Rn-1

Circular Shift Left: R ← cil R

R0R1R2R3Rn-1

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SHIFT MICROOPERATIONSShift Microoperations

Arithmetic Shift Right: R ← ashr R

R0R1R2R3Rn-1

- Arithmetic shift-left Overflow: Rn-1 ≠ Rn-2

Shift MicrooperationsSymbol DescriptionR ← shl R Shift-left register RR ← shr R Shift-right register RR ← cil R Circular shift-left register RR ← cir R Circular right-shift register RR ← ashl R Arithmetic shift-left register RR ← ashr R Arithmetic shift-right register R

Rn-2

Arithmetic Shift Left: R ← ashl R

R0R1R2R3Rn-1 0Rn-2

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SHIFT MICROOPERATIONS - EXAMPLE

• R1 ← shl R11100111010011100

R1 beforeR1 after

• R1 ← shr R11100111001100111

R1 beforeR1 after

• R1 ← cil R11100111010011101

R1 beforeR1 after

• R1 ← cir R11100111001100111

R1 beforeR1 after

• R1 ← ashl R11100111010011100

R1 beforeR1 after

• R1 ← ashr R1 11001110 11100111

R1 beforeR1 after

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HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONSShift Microoperations

Shifter

S01

H0MUX

S01

H1MUX

S01

H2MUX

S01

H3MUX

Select 0 for shift right (down) 1 for shift left (up)Serial

input (IR)

A0

A1

A2

A3

Serialinput (IL)

Select OutputS H0 H1 H2 H3

0 IR A0 A1 A2

1 A1 A2 A3 IL

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HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONSShift Microoperations

S01

MUX

S01

MUX

S01

MUX

S01

MUX

Select = 0IR = 0

A0

A1

A2

A3

IL

A ← shr A

Register A

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ARITHMETIC LOGIC SHIFT UNIT

S3 S2 S1 S0 Cin Operation Function0 0 0 0 0 F = A Transfer A0 0 0 0 1 F = A + 1 Increment A0 0 0 1 0 F = A + B Addition0 0 0 1 1 F = A + B + 1 Add with carry0 0 1 0 0 F = A + B’ Subtract with borrow0 0 1 0 1 F = A + B’+ 1 Subtraction0 0 1 1 0 F = A - 1 Decrement A0 0 1 1 1 F = A Transfer A0 1 0 0 X F = A ∧ B AND0 1 0 1 X F = A ∨ B OR0 1 1 0 X F = A ⊕ B XOR0 1 1 1 X F = A’ Complement A1 0 X X X F = shr A Shift right A into F1 1 X X X F = shl A Shift left A into F

Arithmetic Logic Shift Unit

ArithmeticCircuit

LogicCircuit

C

C 4 x 1MUX

Select

0123

F

S3S2S1S0

BA

i

A

D

A

E

shrshl

i+1 i

ii

i+1i-1

i

i

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register ar

register portion

register meaningmar

drdata register memory

contents of register

register common ways

transfer of information

memory transfers transfer