ch3 - al machine organization

CSC159: Computer Organization Prepared by: Pn. Siti Fatimah Nor Binti Ab Wahab 1

ASSEMBLY LANGUAGE MACHINE ORGANIZATION

CHAPTER 3


Sub-topicsThe topic will cover: Microprocessor architecture CPU processing methods

Pipelining Superscalar RISC vs CISC Multiprocessing

Instruction Cycle Instruction Sets and Types


MICROPROCESSOR ARCHITECTURE


Microprocessor (CPU) ArchitectureThis topic focuses on the components in the microprocessor

related to the machine instruction cycle namely the : Control Unit, Arithmetic Logic Unit, Registers, and Clock.


Microprocessor (CPU) Architecture


Microprocessor (CPU)Microprocessor (CPU) The microprocessor (central processing unit) is similar to the human

brain. The heart of a computer is the CPU. It interprets and carries out the basic instructions that operate a

computer. Most processor chips manufacturers now offer multi-core processors

single chip with more than one separate processor cores. These cores are viewed by the OS as separate processors. Currently

there are dual-core processors and quad-core processors.


Microprocessor (CPU)The processors contains three main components which work

together to perform processing operations. CU ALU Registers


Microprocessor (CPU): 3 main components


Microprocessor (CPU): System Block Diagram


Microprocessor (CPU) Machine CycleCPU Functions: Fetch:

Obtain program instruction or data item from the main memory Decode :

Translate the program instruction into the commands that computer can process

Execute: Carry out the commands one after another

Store: Store the result into main memory


Microprocessor (CPU) Machine Cycle


Control Unit (CU) According to IEEE the control unit is

the parts that effect the retrieval of instruction in proper sequence, the interpretation of each instruction, and the application of the proper signals to the arithmetic unit and other parts in

accordance with the interpretation.

CU is the brain of the microprocessor. CU contains the microprogram (the entire instruction set).

It coordinates and directs most of the operations in the computer.


Control Unit (CU)CU controls and interprets the execution of

instructions, by following a sequence of actions that corresponds to fetch-execute instruction cycle (retrieve instructions from memory then movement of data or address from one part of the CPU to another).


Control Unit (CU) To determine which instruction to be executed, CU reads the contents of

the program counter (PC)/ instruction pointer (IP). The instructions are then decoded by the Instruction Decoder in the

CU. Instructions are executed sequentially CU has a Memory Management Unit to supervise the fetching of

instructions and data from memory. The I/O interface is also part of the control unit.


Control Unit (CU) Instruction Decoder

Is properly part of the CU. But the decoding of instructions is a separate and distinct phase of microprocessor

operations. The microprocessor knows how to add, but does not know when to add and what

to add. When an instruction is fetched from the memory, the instruction is then sent

to the instruction decoder to be decoded or interpreted. Control signals will then be issued to perform the necessary operation.

The interpretation process is called instruction decoding.


Arithmetic Logic Unit (ALU) ALU is the heart of the microprocessor. ALU performs arithmetic and logical operations on input data. It

performs these operations as directed by the CU. Structure: Comparator

compares the magnitude of two numbers placed in buffer registers. Thecomparator, used in conjunction with Status Register, will output the results ofthe comparison.

Logic Registers Performs such logic operations as AND, OR, XOR, etc.


Arithmetic Logic Unit (ALU) Control of the ALU

operation of ALU must be controlled. Accomplished through control leads thatprovides input path for control signals and facilitate the sequencing andoperation of each individual block of circuits.

Shifter A special function register. It will move the contents of a register one or more

positions left or right. Can also perform a unique operation called rotate whenused with status register.


RegistersA single, permanent storage location within the CPU used for

particular defined purpose.Used to hold binary value temporarily for Storage, Manipulation, and/or Simple calculations.

The basic working components of the CPU.


RegistersA register may hold: data being processed an instruction being executed a memory or I/O address to accessed keeps track of the status of the computer or conditions of calculations.


RegistersFour primary operations by registers: Can be loaded with values from other locations (from other registers

or memory location). Data can be added or subtracted. Data can be shifted or rotated right or left by one or more bits. Value of data in register can be tested for certain conditions (zeros,

negative, etc)


RegistersInstruction Register (IR) Holds the current instruction being executed.

Program Counter Both a counter and a register. The address in the program counter register is always the address of

the next instruction to be executed. When the current instruction is finished, the program counter

generates an address and places it on the address bus. It then increments, that is, adds 1 to the address it just generated and

puts the number in the counter register.


RegistersProgram Counter (cont) Again, when the current instruction is finished, it places the new

address on the address bus and again adds 1 to the register. Therefore, the program counter continually generates sequential

address.

Memory Address Register (MAR) Holds the address of a memory location.


RegistersMemory Data Register (MDR) Also known as Memory Buffer Register (MBR). Holds data value that is being stored to or retrieved from the memory

location currently addressed by the memory address register.


RegistersStatus Register (Flags) Allow computers to keep track of special condition such as:

Arithmetic carry and overflow Power failure, and Internal computer error.

The Status register contains individual flags (1 bit for each flag)

The control unit set (1) or reset (0) flags as a result of conditions that arise during the execution of instructions.


System ClockThe system clock is a device that emits periodic sequence of

pulses to control the timing of all computer operations. These pulses define machine cycles.During each machine cycle, some activity occurs, such as the

execution of a microinstruction. The interval between corresponding edges of two consecutive

pulses is called the clock cycle time.


System ClockThe pace of the clock or the clock speed is measured by the

number of ticks per second. Pulse frequencies are currently in the gigahertz range which

corresponds to billions of ticks per second. Therefore the faster the clock speed, the more instructions the

processor can execute per second.


Englander: Mind Map..Microprocessor: Chapter 7: Page 198 Chapter 8: Page 240

System clock: Chapter 8 Chapter 15


Oct 2012: Part B Q 2


CPU PROCESSING METHODS


CPU Processing MethodsIn this topic, you will be introduced to the different and

interrelated CPU processing methods. The common goal is to increase the performance of the

CPU. Among the methods are: Pipelining Superscalar CISC and RISC Multiprocessing


CPU Processing MethodsPerformance number of instructions executed in a

given amount of time.To increase computer performance, these techniques

are used: Separating the fetch unit / execute unit Overlapping the instruction cycle of instructions. Executing more than one instruction in a clock cycle.


CPU Processing MethodsSeparating the fetch unit/ execute unit Previously instruction cycles are executed one by one. A

new instruction enters the instruction cycle after the previous instruction has completed execution.

In the instruction cycle, two phases are involved fetchphase and execute phase.

To increase performance, it is possible to separate the two phase and perform them concurrently.


CPU Processing MethodsFetch unit - retrieves and decodes the instructions Fetches the instructions in parallel Holds them in a buffer until it can be decoded and executed. How many instructions in a buffer?

Size of instruction Width of memory bus Size of buffer


CPU Processing MethodsExecute unit performs actual instruction execution Contains ALU and a portion of CU Identifies and controls the steps that comprise the execution

part of the instruction.


CPU Processing Methods

Instruction Decode Unit

Instruction Execution Unit

ALURegisters

Instruction Fetch Unit

Bus Interface

Memory Addressing Unit


PipeliningA Pipelining is an implementation technique where

multiple instructions are overlapped in execution.Used in advanced microprocessors where the

microprocessor begins executing a second instructionbefore the first has been completed.


Pipelining Computer processors can handle millions of instructions each

second. Once one instruction is processed, the next one in line is processed, and so on.

A pipeline allows multiple instructions to be processed at the same time. While one stage of an instruction is being processed, other instructions may be undergoing processing at a different stage.

Without a pipeline, each instruction would have to wait for the previous one to finish before it could even be accessed.

Refer to Figure 8.5 Page 252


PipeliningThe computer pipeline is divided in stages. Each stage completes a part of an instruction in parallel. That is, several instructions are in the pipeline

simultaneously, each at a different processing stage.The stages are connected one to the next to form a pipe

instructions enter at one end, progress through the stages, and exit at the other end.


Pipelining

Instruction 1

Instruction 2

Instruction 3

Instruction 4


PipeliningIt is not useful to pipe different types of instructions

through a single pipeline different execution units are created based on general types of instructions: Load/store unit Integer arithmetic unit Floating point arithmetic unit Branch unit


PipeliningPipeline hazards Situations that prevent the next instruction in the instruction

stream from executing during its designated clock cycle. The instruction is said to be stalled. Effect stall following instructions too. No new instructions

are fetched during the stall.


PipeliningTypes of hazards: Structural hazard Control Hazard Data hazard


PipeliningStructural hazard attempt to use the same resource

two different ways at a time. Eg: use the register for multiplication and division operation

at the same time.


PipeliningData hazard attempt to use data before it is ready Eg: the following instruction depends on the result of prior

instruction in the pipeline.

Control hazard attempt to make a decision before a condition is evaluated Eg: branch instructions


Pipelining Advances: super-pipelining & superscalar

There are two typical approaches today, in order to improve performance:1. Super pipelining = longer pipes Increases in pipe stages (up to 10 or more) The more stages the more throughput

2. Superscalar = multiple pipes More than one instruction started each cycle (multiple issue) Requires more hardware More complex dependency detection Sometimes different types of pipes: ALU, FPU, branch, etc.


PipeliningHow to overcome hazards? Instruction reordering separate dependent

instructions so they are not executed one right after the other. Prediction, superscalar processing.


SuperscalarIt means processing multiple instructions at a time because of

its multiple pipeline. It is a standard feature in modern computer systems. Superscalar processing can increase the throughput by double

or more.Separate fetch and execute cycles as much as possibleBuffers for fetch and decode phasesParallel execution units


Scalar VS SuperscalarScalar: A CPU that performs computations on one number or set of

data at a time. Most computers have scalar CPUs. A scalar processor is known as a "single instruction stream

single data stream


Scalar VS Superscalar


Superscalar Technical Issues

Out-of-order processing Branch instruction processingConflict of resources


Out of Order ProcessingHazard / dependency later instruction depend on the result of earlier instruction.

Data dependency later instruction completes ahead of the earlier one.

Implication wrong order.

Solution provide reservation station.


Out of Order Processing (cont.)

Another solution search ahead for instructions.For instance, Intel x86: can search 20 30

instructions ahead if necessary.


Branch Instruction Processing

Flow / branch dependencies conditional branch instructions.

Solution can be broken into 2 parts: optimize correct branch selection methods to prevent errors


Branch Instruction Processing (cont.)Speculative execution (prevent errors): separate bank of registers used to hold results from later

instructions until previous instructions are complete. result transferred into actual register and memory

locations.


Branch Instruction Processing (cont.)Optimization: maintain more than two pipelines predict the correct path based on program usage and

performance branch history table


Conflict of ResourcesConflict bet instructions that use the same registers

Solution use the same bank of registers

Bank of registers hold the results of speculative instructions until instruction

completeConcept rename register / logical registers / register alias tables


Superscalar CPU Block Diagram


CPU ArchitectureCISC Complex Instruction Set ComputerRISC Reduced Instruction Set Computer


CISC ArchitectureExamples Intel x86, IBM Z-Series Mainframes, older CPU

architecturesCharacteristics Few general purpose registers Many addressing modes Large number of specialized, complex instructions Instructions are of varying sizes


Limitations of CISC ArchitectureComplex instructions are infrequently used by programmers

and compilersMemory references, loads and stores, are slow and account for

a significant fraction of all instructionsProcedure and function calls are a major bottleneck Passing arguments Storing and retrieving values in registers


RISC (Reduced Instruction Set Computer)Attempts to produce more CPU power by eliminating

major bottlenecks to instruction execution speed:Reducing number of data memory access by using

registers more effectively.Simplifying the instruction set.


RISC (Reduced Instruction Set Computer)Features: Examples:

Power PC, Sun Sparc, Motorola 68000 Limited and simple instruction set. Fixed length, fixed format instruction words

Enable pipelining, parallel fetches and executions


RISC (Reduced Instruction Set Computer)Features: (cont.) Limited addressing modes.

Reduce complicated hardware Register-oriented instruction set

Reduce memory accesses Large bank of registers

Reduce memory accesses Efficient procedure calls


CISC vs. RISC Processing


CISC vs. RISC Performance Comparison RISC Simpler instructions

more bus traffic increase cache memory misses

CISC more instructions more memory accesses

More registers would improve CISC performance but no space available for them

Modern CISC and RISC architectures are becoming similar


MultiprocessingThe use of more than 1 CPU to process instructions.Reasons for using multiprocessing: Increase the processing power of a system. Enables parallel processing programs can be divided into

independent pieces and the different parts executed simultaneously on multiple processors.


Multiprocessing


MultiprocessingSince the execution speed of a CPU is directly related to the

clock speed, equivalent processing power can be achieved at much lower clock speeds, reducing power consumption, heat and stress within the various computer components.

Adding more CPUs is relatively inexpensive.If a CPU encounters a problem, other CPUs can continue

instruction execution, increasing overall throughput.


MultiprocessingTwo types:

a) tightly coupled systemb) loosely coupled system


Tightly Coupled SystemIdentical access to programs, data, shared memory,

I/O, etc.Easily extends multi-tasking, and redundant program

executionTwo ways to configure Master-slave multiprocessing Symmetrical multiprocessing (SMP)


MultiprocessingTypical multiprocessing system configuration


Multiprocessing - Master-slave Multiprocessing

Master CPU Manages the system Controls all resources and scheduling Assigns tasks to slave CPUs


Multiprocessing - Master-slave Multiprocessing

Advantages Simplicity Protection of system and data

Disadvantages Master CPU becomes a bottleneck Reliability issues if master CPU fails entire system fails

Applications Game, Finance, Economics, Biology, Physics


Multiprocessing Symmetrical Multiprocessing

Each CPU has equal access to resourcesEach CPU determines what to run using a standard

algorithm


Multiprocessing Symmetrical Multiprocessing

Disadvantages Resource conflicts memory, i/o, etc. Complex implementation

Advantages High reliability Fault tolerant support is straightforward Balanced workload


Englander: Mind Map..CPU processing methods Pipelining : Chapter Superscalar : Chapter RISC vs CISC : Chapter Multiprocessing : Chapter


INSTRUCTION CYCLE


Instruction CycleThe microprocessors main task is to execute

instructions. The instruction cycle is therefore at the heart of

understanding the function and operation of the microprocessor.

The time begins when the address for retrieving an instruction from memory is placed on the address bus for a fetch, and ending when the execution phase is completed.


Instruction CycleThe instruction cycle is composed of two main cycles,

because both instructions and data are in memory. Fetch cycle

Find and Decode instruction, load from memory into register and signal ALU

Execute cycle. Performs operation that instruction requires Move/transform data


Instruction CycleGenerally, a microprocessor carries out instructions in

a three-step (or phase) process. It simply repeats the three-step operation with almost

no variation, as long as power is applied to it. These three steps are called Fetch Decode Execute


Instruction Cycle Phase 1: Fetch Fetching, in a microprocessor, is the term used to

indicate that the microprocessor is retrieving an instruction from memory.

The microprocessor fetches the instructions from memory one at a time, and brings them into the instruction decoder register to be decoded.


Instruction Cycle Phase 2: DecodeThe decode phase of the cycle begins as soon as the instruction, in

the form of an 8-bit byte, appears in the instruction decoder register.

The decoding is done via PLA (Programmable Logic Array).The array will output the control signals necessary to carry out the instruction.

The PLA is designed with microcode to recognize only those bit patterns contained in the instruction set. Upon recognition of a bit pattern the PLA or microcode then generates the internal and external control signals necessary to carry out the given instruction.


Instruction Cycle - Phase 3: ExecuteThe execution phase begins as soon as the microcode outputs

the control signal necessary to carry out the instruction. The length of time needed to complete the execution phase

varies considerably with the type of instruction involved. Some instructions are several bytes long. Each byte is fetched and decoded one at a time. After each byte is decoded, the necessary control signals are

executed.


Fetch-Execute Instruction CycleBasis for every capability of a computerUltimately the operation of a computer as a whole is defined

by the primary operations that can be performed with registers to move data between registers to add or subtract data to a register to shift data within a register to test the value in a register for certain conditions such as negative,

positive or zero.


Fetch-Execute Instruction Cycle Basically, the registers involved are:

1. General purpose (GP) registers or accumulator (A) : used to hold data values between instructions

2. Program counter (PC) : hold the address of the current instruction

3. Instruction register (IR) : hold the current instruction while it is being executed

4. Memory address register and memory data register (MAR & MDR) : used for accessing memory


Fetch-Execute Instruction Cycle To execute an instruction, 2 phases involve :

1. Fetched the instruction from memory address of the current instruction to be executed identified by the value in PC

register this value transferred into MAR so that the computer can retrieve the

instruction located at that addressSTEP 1 : PC MAR

this will result in the instruction being transferred from the specified memory location to MDR

that instruction is transferred to IRSTEP 2 : MDR IR


Instruction Cycle Fetch Cycle


Instruction Cycle Execute CycleThis cycle is instruction dependent. The instructions

can be categorized into the following four groups: CPU - Memory: Data may be transferred from memory to the

CPU or from the CPU to memory. CPU - I/O: Data may be transferred from an I/O module to

the CPU or from the CPU to an I/O module.


Instruction Cycle Execute Cycle Data Processing: The CPU may perform some arithmetic or

logic operation on data via the arithmetic-logic unit (ALU). Control: An instruction may specify that the sequence of

operation may be altered. For example, the program counter (PC) may be updated with a new memory address to reflect that the next instruction fetched, should be read from this new location.


Instruction Cycle Execute Cycle Remaining steps : to complete a LOAD instruction

2. Interpret the instruction and perform the action Address portion of the instruction is loaded in MAR

STEP 3: IR[address] MAR Actual data is copied into the accumulator

STEP 4: MDR A Program Counter incremented

STEP 5: PC + 1 PC


LMC vs. CPU: Fetch and Execute Cycle


1. PC -> MAR Transfer the address from the PC to the MAR

2. MDR -> IR Transfer the instruction to the IR

3. IR(address) -> MAR Address portion of the instruction is loaded in MAR

4. MDR -> A Actual data is copied into the accumulator

5. PC + 1 -> PC Program Counter is incremented

Fetch-Execute Cycle: LOAD





4. A + MDR -> A Contents of MDR are added to contents of accumulator and the result is stored back into accumulator


Fetch-Execute Cycle: ADD





4. A -> MDR* Accumulator copies data into MDR


*Notice how Step #4 differs for LOAD and STORE

Fetch-Execute Cycle: STORE


LMC Fetch-ExecuteSUBTRACT

PC MARMDR IRIR[addr] MARA MDR APC + 1 PC

IN

PC MARMDR IRIOR APC + 1 PC

OUT

PC MARMDR IRA IORPC + 1 PC

HALT

PC MARMDR IR

BRANCH

PC MARMDR IRIR[addr] PC

BRANCH on Condition

PC MARMDR IRIf condition false: PC + 1 PCIf condition true: IR[addr] PC


Fetch-Execute Cycle ExampleProgram Counter = 65Value in Mem Location 65: 590 (LOAD 90)Value in Mem Location 66: 192 (ADD 92)Value in Mem Location 67: 390 (STORE 90)Value in Mem Location 90: 111Value in Mem Location 92: 222


Explanation 1st Instruction LOAD 90PC -> MAR MAR now has 65MDR -> IR IR contains the instruction: 590------------------------ end of fetchIR [address] -> MAR MAR now has 90, the location of

the dataMDR -> A Move the value 111 from MDR to APC + 1 -> PC PC now points to 66


Explanation 2nd Instruction ADD 92PC -> MAR MAR now has 66MDR -> IR IR contains the instruction: 192------------------------ end of fetchIR [address] -> MAR MAR now has 92, the location of

the dataA + MDR -> A 111 in Accumulator + 222 in MDR

= 333 into AccumulatorPC + 1 -> PC PC now points to 67


Explanation 3rd Instruction STORE 90PC -> MAR MAR now has 67MDR -> IR IR contains the instruction: 390------------------------ end of fetchIR [address] -> MAR MAR now holds 90A -> MDR The value in A, 333 moves to

memory location 90PC + 1 -> PC PC now points to 68------------------------ ready for next instruction


INSTRUCTION SETS AND TYPES


Instruction Sets and TypesInstruction set is a complete collection of instructions

that are understood by a CPU. The instruction set is ultimately represented in binary

machine code also referred to as object code. The sets are represented by assembly codes to human

programmer.


Instruction Sets and TypesElements of an instruction Operation Code (opcode)

Usually 8 bits, used to indicate what to do. Source Operand Reference(s)

Do the operation to the value at this address. Result Operand Reference(s)

Put the answer here Next Instruction Reference


Instruction Sets and TypesOperands are used to specify which register, which

memory location, or which I/O device. Well need some addressing scheme for each.

In machine code, each instruction has a unique bit pattern.

For human consumption a symbolic representation is used called mnemonic. Examples of mnemonic are ADD, SUB etc.


Instruction Sets and TypesThe instruction set categories: Data Movement (load, store)

Most common, greatest flexibility Involve memory and registers

Arithmetic Operators + - / * ^ Integers and floating point


Instruction Sets and Types Boolean Logic

Often includes at least AND, XOR, and NOT Single operand manipulation instructions

Negating, decrementing, incrementing, set to 0 Bit manipulation instructions

Flags to test for conditions


Instruction Sets and Types Shift and rotate

Logical shift zeros are shifted in to replace the bit spaces that have been vacated.

Arithmetic shift multiply or divide by a power of 2. Program control

Jumps, branch, CALL, RETURN Stack instructions

Push, pop


Instruction Sets and Types Multiple data instructions

Performs single operations on multiple pieces of data simultaneously.

Multimedia apps I/O and machine control

Privileged instructions.

Assembly Language MACHINE organizationSub-topicsMicroprocessor ArchitectureMicroprocessor (CPU) ArchitectureMicroprocessor (CPU) ArchitectureMicroprocessor (CPU)Microprocessor (CPU)Microprocessor (CPU): 3 main componentsMicroprocessor (CPU): System Block DiagramMicroprocessor (CPU) Machine CycleMicroprocessor (CPU) Machine CycleControl Unit (CU)Control Unit (CU)Control Unit (CU)Control Unit (CU)Arithmetic Logic Unit (ALU)Arithmetic Logic Unit (ALU)RegistersRegistersRegistersRegistersRegistersRegistersRegistersSystem ClockSystem ClockEnglander: Mind Map..Oct 2012: Part B Q 2CPU processing methodsCPU Processing MethodsCPU Processing MethodsCPU Processing MethodsCPU Processing MethodsCPU Processing MethodsCPU Processing MethodsPipeliningPipeliningPipeliningPipeliningPipeliningPipeliningPipeliningPipeliningPipeliningPipelining Advances: super-pipelining & superscalarPipeliningSuperscalarScalar VS SuperscalarScalar VS SuperscalarSuperscalar Technical IssuesOut of Order ProcessingOut of Order Processing (cont.)Branch Instruction ProcessingBranch Instruction Processing (cont.)Branch Instruction Processing (cont.)Conflict of ResourcesSuperscalar CPU Block DiagramCPU ArchitectureCISC ArchitectureLimitations of CISC ArchitectureRISC (Reduced Instruction Set Computer)RISC (Reduced Instruction Set Computer)RISC (Reduced Instruction Set Computer)CISC vs. RISC ProcessingCISC vs. RISC Performance ComparisonMultiprocessingMultiprocessingMultiprocessingMultiprocessingTightly Coupled SystemMultiprocessingMultiprocessing - Master-slave MultiprocessingMultiprocessing - Master-slave MultiprocessingMultiprocessing Symmetrical MultiprocessingMultiprocessing Symmetrical MultiprocessingEnglander: Mind Map..INSTRUCTION CycleInstruction CycleInstruction CycleInstruction CycleInstruction Cycle Phase 1: FetchInstruction Cycle Phase 2: DecodeInstruction Cycle - Phase 3: ExecuteFetch-Execute Instruction CycleFetch-Execute Instruction CycleFetch-Execute Instruction CycleInstruction Cycle Fetch CycleInstruction Cycle Execute CycleInstruction Cycle Execute CycleInstruction Cycle Execute CycleLMC vs. CPU: Fetch and Execute CycleFetch-Execute Cycle: LOADFetch-Execute Cycle: ADDFetch-Execute Cycle: STORELMC Fetch-ExecuteFetch-Execute Cycle ExampleExplanation 1st Instruction LOAD 90Explanation 2nd Instruction ADD 92Explanation 3rd Instruction STORE 90Instruction Sets and TypesInstruction Sets and TypesInstruction Sets and TypesInstruction Sets and TypesInstruction Sets and TypesInstruction Sets and TypesInstruction Sets and TypesInstruction Sets and Types

ch3 - al machine organization

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