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EEN1036 Digital LogicDesign

Chapter 3 part II

Combinational Logic Circuit

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Objective

Implement circuit from Booleanexpressions

Describing logic circuits algebraically

From truth table to logic circuit Evaluating logic circuit outputs

Implement logic circuits using only NAND

and NOR gates

Deriving output waveform for a given

timing diagram

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3

IntroductionThe relationship between Boolean expression, truth table and

logic circuit is as shown below:

Boolean

expression

Truth table Logic circuit

SOP/

POS

Boolean expression can be derived as minterm or

maxterm Boolean expression from truth table and vice-versa

Logic circuit can be drawn from Boolean expression and

vice versa

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From Boolean expression to Logic Circuits

If a logic function is defined by a Boolean expression, itscircuit diagram can be implemented directly from the

expression

In general, there are three type of Boolean expression

i. Sum-of-products (SOP) expression

ii. Product-of-sums (POS) expression

iii. Miscellaneous (a mixture of basic logic functions)

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Drawing Logic Circuit from Boolean expression

B CA

BCACBAY )(

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AND-OR Networks

These networks are directly drawn from sum-of-products(SOP) expressions

Consider the example below:

Given CACABCBAY

A B C

Y

CBA

CAB

CA

Variables are inverted

Variables are ANDed together to form product terms

Product terms are ORed together

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OR-AND Networks

They are drawn directly from POS expressions

Consider the following example

Given )()()( CACBACBAY

Variables are inverted

Variables are ORed together to form sum terms

Sum terms are ANDed together

A B C

Y

CBA

CBA

CA

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Other Types of Networks Consist of a mixture of various logic gates, such as

NOT, AND, OR, NAND, NOR, XOR, XNOR Example:

)()( ABBACCBCBAY

A B C

Y

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Continue ... Consider another example:

)())(( CACABADCBCBAY

A B C

Y

D

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Describing Logic Circuit Algebraically

Similarly, if a logic circuit is given, we can derive its

Boolean expression by observing and combining theoutputs of each logic gates

Consider the AND-OR network below:

A B C

ABC

CBA

CBA

CBACBAABCY

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Continue ... Consider the following OR-AND network:

A B C

Consider the following logic circuit:A B C

BA

BA

CB

))()(( CBBABAY

CA

BC

CABC

ACABCY )(

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Continue ...

Consider yet another circuit:A B C D

DB

CB

CA

DA

CBDB

CACBDB

DACACBDBY

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From Truth Table to Logic Circuit

We can construct the logic circuit from its truth table

This can be done by first obtaining the minterm/maxtermBoolean expression from truth table

Consider the following example:

A B C Y

1

01

0

1

0

1

0

1

1

1

1

00

0

0

1

1

1

1

00

0

0

0

0

1

0

1

0

1

0

CBA

CBA

CAB

CABCBACBAY

A B C

Y

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Continue ...

Consider obtaining the maxterm Boolean expressionfrom the truth table below:

A B C Y

1

0

1

0

1

0

1

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

1

1

0

A B C

Y

CBA

CBA

))(( CBACBAY

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Evaluating Logic Circuit Output

We can determine the output of a particular logic circuit

if its Boolean expression is known This can be done by first obtaining the Boolean

expression of the logic circuit and convert it to SOP form

A B C

Y

BA

BC

CBA

)( BABC

CBAABC

CBABABCY

)(

A B C Y

1

01

0

1

0

1

0

1

1

1

1

00

0

0

1

1

1

1

00

0

0

0

0

0

1

1

0

0

0

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Continue ... Consider obtaining the truth table for the logic circuit below:

A B C

Y

BA

CB

CA

CBBA

CACBCAAB

CACBBA

CACBBA

CACBBAY

))((

A B C Y

1

0

1

0

1

0

1

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

0

1

1

1

0

1

0

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Continue ...

A B C

Y

Consider another logic circuit as shown below:

BA

CA

CBA

CBA

))((

)()(

CBACBA

CBACBA

CBACBAY

A B C Y

1

0

1

0

10

1

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

01

1

1

1

1

1

0

0

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Continue ... Consider yet another logic circuit as shown below:

A B C D

Y

A B C D Y

0

1

01

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

000

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

00

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

1

0

0

1

0

0

1

0

1

0

0

1

0

1

ABDDCBDB

ADDCBDB

ADDCBDB

ADDCBDBY

)(

DB

DC

AD

ADDC

ADDCB

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Universality of NAND & NOR Gates All Boolean expressions consists of various

combinations of OR, AND and NOT Both NAND and NOR gates can be used to perform OR,

AND and NOT

Thus, it is possible to implement any logic circuit by

using only NAND or NOR gates

A

A

A

A

A

A

B

B

B

B

AAAX

ABX AB

A

BBABAX

Inverter

AND

OR

1

1

2

2

3

(a)

(b)

(c)

A

A

A

A

A

A

B

B

B

B

AAAX

BAX BA

A

BABBAX

Inverter

AND

OR

1

1

2

2

3

(a)

(b)

(c)

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Implementing AND-OR network with NAND gates only

AND-OR network can be directly implemented using

only NAND gates

The procedures to convert AND-OR network to pureNAND gates implementation is based on DeMorgans

Theorem

Consider implementing the AND-OR network below by

using NAND gates onlyA B C

Y

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Continue ...A B C

Y

P

Q

PQRRQP

A B C

Y

R

Implement inverter using NAND gates

Place a bubble at the output of each AND gates

Place a bubble at the input of the OR gate

If an input to OR gate is directly connected to input line,

place an inverter between them

Redraw the logic circuit by using NAND gates only

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A B C

Y

Continue... Another solution ..

BCAAB

BCAAB

BCAABY

Derive the Y output

Use De-Morgan to convert SOP to a form of all product

Redraw the logic circuit by using NAND gates onlybased on the derived equation

A B C

Y

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Implementing OR-AND network with NOR gates only

Similarly, OR-AND networks can be implemented by

using NOR gates only

Consider implementing the OR-AND network below by

using NOR gates only

A B C

Y

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Continue ...

A B C

Y

P

QRQPRQP

A B C

Y

R

Implement inverter using NOR gates

Place a bubble at the output of each OR gates

Place a bubble at the input of the AND gate If an input to AND gate is directly connected to input

line, place an inverter between them

Redraw the logic circuit by using Nor gates only

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Continue... Another solution ..

CCBBA

CCBBA

CCBBAY

)()(

)()(

)()(

Derive the Y output

Use De-Morgan to convert POS to a form of all sum

Redraw the logic circuit by using NOR gates only basedon the derived equation

A B C

Y

A B C

Y

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Continue ...

The preceding 2 methods can only be applied to AND-

OR networks and OR-AND networks, respectively

It is advisable to construct logic circuit using NAND or

NOR gates only by properly manipulating the Boolean

expression of the original logic circuit and application of

DeMorgans theorems

Consider implement the following logic circuit usingNAND gates only:

A B C

CAB

CAB

CABY

A B C

AB

CABY

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Continue ...

Consider implement the following logic circuit by using

NOR gates only:A B C

Y

CBBA

CBBA

CBBA

CBBAY

)(

)(

BA

CB

A B C

CB

BACBY

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Continue ...

Example:

i. Implement the following Boolean expression by using

NAND gates only:

CBBAY

Solution:

CBBA

CBBA

CBBA

CBBAY

A B C

BA

CBBAY CB

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Continue ...

ii. Implement the following logic function by using

NOR gates only:

BCDABY

DCBBA

BCDBA

BCDABY

Solution:A B C

BA

D

BA

DCB

DCBBA

Y

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Input and Output Waveforms

We can plot the output waveform of a logic circuit with

respect to its inputs by referring to the truth table

The procedures to derive the output waveform are:

i. Obtain the Boolean expression for the logic circuit

ii. Convert the Boolean expression to SOP form

iii. Based on the SOP expression, construct the truth tableiv. Referring to the truth table, draw the output waveform

corresponds to each input condition

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Continue ...

Example:

Determine the output waveform if the inputs are varyingaccording to the timing diagram below:

A B C

X

Y

Z

10 1 1 1 1

1 1 1 1

1 1

0 0

0 0 0 0

0 0 00 0 0

a b c d e f g h

a b c d e f g h

A

B

C

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Continue ... Solution:

A B C

AB

CABX

BA

)( BACY

AB

CABZ

CAB

CAB

CABZ

BCAC

BACY

CABX

)(

A B C X

1

01

0

1

0

1

0

1

1

1

1

00

0

0

1

1

1

1

00

0

0

Y Z

10 1 1 1 1

1 1 1 1

1 1

0 0

0 0 0 0

0 0 00 0 0

a b c d e f g h

a b c d e f g h

A

B

C

X

Y

Z

a b c d e f g h

a b c d e f g h

10 1 1 1

1

0 00

0 0 0 0 0 0 0

10 0 0 1 0 0 0

0

00

0

0

0

0

1

0

1

0

1

00

0

1

0

1

1

1

01

0

1

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Continue ... Example:

Determine the output waveform if the inputs are varying

according to the timing diagram below:A B C D

Y

0 0 1 1 0 0 1 1

1 1 1 0 0 1 0 0

1 0 0 1 0 1 0 0

0 0 1 0 1 1 1 0

a b c d e f g h

a b c d e f g h

a b c d e f g h

A

B

C

D

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Continue ...A B C D

Y

DB

CA

BA

DC

DCA

DCA

)( CADB

DCBA

))(( DCADCA

DCBACADB )(

))(( DCADCAB

))(()( DCADCABDCBACADBY

C i

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DCBADCBADCBDBCDCADCACDBADCBA

DCADCABDCDCBACDBADCBA

DCADCABDCBACACADB

DCADCABDCBACADBY

)())((

)(

))(()(Continue ...

A B C D Y

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0 0 1 1 0 0 1 1

1 1 1 0 0 1 0 0

1 0 0 1 0 1 0 0

0 0 1 0 1 1 1 0

a b c d e f g h

a b c d e f g h

a b c d e f g h

A

B

C

D

Y

1 0 1 0 1 0 1 0

1

1

1

1

0

1

1

0

0

1

00

0

1

1

0

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Electronic Gates

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Faults

Internal

shorted inputs or outputs to ground or supply

open circuited

short between pins

External

open signal lines

shorted signal lines

faulty power supply output loading

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Propagation Delay

Various physical phenomena, such as resistance andcapacitance, substantially reduce the speed at which

signal can travel in physical circuit

If there is a change at the inputs, the output of a logic gate

will not change instantaneously.

All the delays occur in a logic gate can be grouped into a

single average or nominal value, known as the

propagation delay

Propagation delay is denoted as tpd

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Continue ... Consider the NAND gate below:

A

B

X

0

0

0

1

1

1

AB

X

For ideal case, there is no propagation delay and the

output responds instantly to the changes of inputs

A B (A.B)'

0 0 1

0 1 1

1 0 1

1 1 0

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Continue ... If there is a propagation delay, the waveforms will become:

The changes in output with respond to the change of

input is delayed, by tpd

The output waveforms for both cases are the same, butshifted to the right by tpd

tpd

tpd

tpd

A

B

X 1

0

0

0

1

1

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