Lecture 1 Deep Submicron Digital IC Design

Lecture 1Design HierarchyChapter 1Digital System Design FlowRegister-Transfer Levl (RTL)e.g. VHDL/VerilogGate Level DesignCircuit Level DesignPhysical LayoutVerilogInclude a set of 26 predefined functional models of common combinational logic gates called primitives. PrimitivesThe most basic functional objects that can be used to compose a designAre built into the language by means of internal truth tablesExamples: and, nand, or, nor, xor, xnorMore on Primitives3-input nand primitiveInput signal a, b, and cOutput signal yEach primitive has ports (corresponding to hardware pins and terminals)The output port(s) of a primitive must be first in the list, followed by the primitives input ports.

Instantiated PrimitivesInstantiated Primitives (nor, and,nand) are connected by wires.A wire is a data-type which is used to establish connectivity in a design, just as a physical wire establishes connectivity between gates.

Example: a Full AdderBinary AdditionGate-Level SynthesisVerilog RepresentationBinary Addition (1)

Binary Addition (2)

Derivation of Question: What primitive best implements ? Inputs: A, BOutputs: xor (, A, B)

BA000101011110Derivation of Carry OutQuestion: What primitive best implements Co? Inputs: A, BOutputs: and (Co, A, B)

BACo000100010111A Half AdderA half adder is useful for adding LSB.

Limitation of a Half Adder

A half-adder does not account for carry-in.Truth Table of of a Full Adder CinBA00000011010101101001101011001111

Identical to of a Half AdderCin+B+A=Cin+HA=Cin XOR HATruth Table of Co of a Full Adder CinBACo00000010010001111000101111011111

Identical to of a Half AdderUse a Half Adderwith Cin and HA to generate Co Schematic of a Full Adder

A 3 bit parallel adder

Gate Level vs. Verilog Model of a Full Adder

ExplanationThe keywords module and endmodule encapsulate the text that describes the moduleThe module name is Add_fullModule Ports areInput a, b, c_inOutput c_out, sumModule instances: Add_half, or

Nested ModuleAdd_half is a child module of Add_full

Gate Level DesignBasic GatesAND, NAND,OR, NOR, XOR, XNOR,NOTUniversal GatesNAND GatesNOR GatesMultiple Inputs Logic GatesNAND Based Logic Gates

NOR Based Logic Gates

Multiple Inputs Logic Gates

Circuit Level

Physical DesignFloor PlanningEstimates of the area of major units in the chip and defines their relative placements.Estimate wire lengths and wring congestions.Challenge: estimate the size of each unit without proceeding through a detailed design of the chip.LayoutDesign VerificationTapeout

A Sample Floor Plan

= of minimum channel lengthA Sample Layout

Layout of an Inverter

In a 0.6 um process 4/2=1.2 um/0.6 um.Design VerificationLVS (Layout vs. Schematic) checks that transistors in a layout are connected in the same way as in the circuit schematic.DRC (Design Rule Checkers) verify that the layout satisfies design rules.ERC (Electrical Rule Checkers) scan for problems such as noise or premature wearout.TapeoutTapeout gets its name from the old practice of writing a specifications of masks to a magnetic tape.GDSFoundries:TSMCUMCIBMFabricated Chip

IC DecapsulationCross Section

Low Cost Package1127Red: Top layer traceGreen: ViaBlue: Bottom layer trace34Package Parasitics