certain semiconductor memory devices and products containing same, 337-470, no. 65959-1 (u.s.i.t.c....

8/11/2019 Certain Semiconductor Memory Devices and Products Containing Same, 337-470, No. 65959-1 (U.S.I.T.C. Apr. 5,

1/179

Appendix A

D 9 ?

3

ECRETARY

CUMMISSION

ppen ix


2/179

UNITED STATE S DEPARTMENT OF COMMERCE

United States Patent and Trademark Office

February

OS, 2002

TH IS IS

TO

CERTIFY TH AT ANNEXED IS A TRUE COPY FROM THE

IRECORDS

OF THIS OFFICE OF THE FILE WRAPPER AND CO NTENTS

OF:

APPLICATION NUM BER:

08/265 535

FILING DATE:

June 24,1994

PATENT NUMBER:

5,452,261

ISSUE DATE: September 19,1995

IW 507655

By Authority of the

'COMMISSIONER OF PATENTS AND TRADEMARKS

P.

R.

GRANT

Certifying Officer


3/179

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..

At t y. Docket No. : M- 2595US

081265535

.AW OFFICES

OF

J une 24, 1994

Our Case Docket No. M- 2595

US

Comm ssi oner of Patent s and Tr ademarks

Washi ngt on, D. C. 20231

Transmt t ed herew th f or f i l i ng i s a pat ent appl i cati on, as f ol l ows:

I nvent or( s)

:ET.,L,

Li gxosg Bu n g and M chael A. Mur r ay

Ti t l e:

-

SERI ALAPDRESS

. ENERATOR .

FO

... VR..M.~-OR~

. Encl osed. al so are:

heets of dr aw ngs:

-

Formal ) X I nf ormal )

- n Assi gnment of t he I nvent i on

t o

-

cert i f i ed copy of a Appl i cat i on.

CLAI MS AS FI LED

Number Number

E a Filed Rate

Basi c Fee

$ 710. 00

Tot al Cl ai ms 10 - 20 - 0 x $22 - 00. 00

Gl ai ms 3 - 3 - 0

x $74

-

00.00

dependent cl ai ms ( $230 t otal f ee)

- 00,oo

Tot al fi l i ns f ee: 710. 00

I ndependent

-

Appl i cati on cont ai ns one or more mul t i pl e

Pl ease make t he f ol l ow ng char ges to Deposi t Account 19- 2386:

XX Fee f or f i l i ng the patent appl i cat i on i n the amount of

$

710. 00

The Comm ssi oner i s hereby authori zed t o char ge any addi t i onal

f ees whi ch may be r equi r ed, or cr edi t any overpayment t o Deposi t

Account 19- 2386.

A Return Post Card and t hi s s heet i n tr i pl i cat e ar e encl osed.

I

hereby certify that this correspondence is being

deposited with he United States Postal

Service

a6 expresa

mail

In

an enveloDe

addressed to: Comnissioner o f Patents

Respectf ul l y subm t t ed,

3

Pw dA4

R.

4L. Y(/-

Nor man R. Kl i vans

Reg.

No.

33, 003

At t orney f or Appl i cant( s)


6/179

. I

' A '

...

5

10

15

20

25

3 0

35

: r/.-

.,

SERI AL ADDRESS GE N E WmF OR BURSTMEMORY

__.

J i nyong chung

/

./

M chael A. Mur r ay

BACKGROUND

OF

THE

I NVENTI ON

Fi el d of t he I nvent i oq

Thi s di scl osur e r el ates t o random access memory

and speci f i cal l y t o a ser i al addr ess gener at or f or a

bur st - t ype r andom access memory.

Descri pt i on of t he Pr i or Art

Vi deo

RAM

( r andomaccess memor y) , synchr onous RAM

and bur st RAM each r equi r e a sequence of i nt e r nal l y

generat ed addresses f or f ast er cycl i ng and pr event i on

of t he external addr ess bus l i nes

from

f ast swi t chi ng

t o

suppr ess sw t chi ng noi se i n t he syst em Typi cal l y

t he st art addr ess

of

a par t i cul ar addr ess bur st i s

provi ded f r om an ext ernal sour ce ( a host computer or a

pr ocessor ) and as subsequent cl ock si gnal s arr i ve at

t he addr ess generator , t he f ol l owi ng addr esses i n the

bur st are generat ed cont i nuousl y i n sequence f or t he

dur at i on

of

t he burst .

addr ess sequencer ( t ypi cal l y a count er)

to

t he

ext ernal l y pr ovi ded st ar t addr ess (A) i n r esponse t o a

PRESET

si gnal . The address sequencer out put i s updat ed

wi t h each

@clock

r i si ng edge, and t he out put s of t he

address gener ator ar e sequent i al l y A, An+ Anp

,

etc.

Such a pr i or art address generat or i s shown i n

Fi g. 1A i ncl udi ng address sequencer

12

out put t i ng t he

sequence of address es t o an out put buf f er

14.

The

t hree i nput si gnal s t o the addr ess sequencer 12 are t he

i nput addr ess si gnal ( t he st art addr ess A), t he @clock

si gnal , and t he PRESET si gnal . Addi t i onal l y, a

The pr i or ar t preset s t he

-1-


7/179

sequence cont r ol si gnal contr ol s whet her t he address

sequencer

12

count s up or down. I n most appl i cati ons,

upcount i ng i s used, and t hi s f uncti on i s bui l t i n,

r ather t han bei ng a cont r ol f unct i on. The associ ated

5 t i m ng di agram i s shown i n Fi g. 2A.

Typi cal l y t he addr ess sequencer

12

( Count er)

i ncl udes a mast er si de and a sl ave si de, each i ni t i al l y

set t o the start addr ess A,,.

t hat t he devi ce of Fi g. 1A i s a par al l el devi ce, where

t he st ar t addr ess A, i s a mul t i - bi t addr ess pr ovi ded by

a pl ur al i t y of l i nes, i .e. an addr ess bus. The addr ess

out si gnal i s al so pr ovi ded on a mul t i - l i ne bus.

out put t o buf f er 14 when the Pr eset si gnal

i s

appl i ed,

second addr ess out A+1

i s out put t o buf f er 14 at t he

t r ai l i ng edge of @clock and t he f ol l owi ng addresses ar e

updat ed at ever y t r ai l i ng edge of t he

@clock

s i gnal .

The addr ess generat or of Fi g. 1A f unct i ons

20

adequat el y; however i t i s sl ower t han desi r ed. Fast er

operat i on i s desi r abl e t o i mpr ove syst emper f ormance

such as needed i n a t ypi cal bur st DRAM ( dynam c r andom

access memor y) chi p. The Fi g. 1A addr ess gener at or

del i ver s t he f i rs t addr ess l at e, due t o t he pr opagati on

sequencer . Thi s means a shor t er st art address dur ati on

t i me

.

To

i mpr ove t he st art addr ess del i ver y, i n a second

pr i or ar t addr ess gener ator t he star t addr ess i s

3 0

pr ovi ded f r om t he Addr ess I nput di r ect l y, i nstead of

goi ng t hr ough t he count ers. ( See Fi g.

lB,

and

cor r espondi ng t i m ng di agr am Fi g.

2B).

Rather t han pr ovi di ng t he st art address

A

t o the

address s equencer as i n Fi g. 1A, t he addr ess sequencer

12

of Fi g.

1B

i s bypassed bef or e and duri ng t he preset

per i od by means of ext ernal addr ess enabl e swi t ch 24

I t i s

t o

be under st ood

10

A s seen i n Fi g.

2A, t he f i r st addr ess out A, i s

15 and kept unti l l eadi ng edge of

@=lock

arr i ves. The

25

del ay t hr ough t he count ers i nsi de t he address

3 5

-2-


8/179

and i nt ernal address enabl e swi t ch 26, and t he st art

addr ess i s pr ovi ded di r ect l y t o t he out put buf f er vi a

ext ernal address enabl e swi t ch 2 4 . Thi s ( s t a r t )

addr ess A i s t her ef ore avai l abl e al most i mmedi at el y as

5 t he addr ess out at buf f er 1 4 , wi t hout pr ocessi ng by t he

addr ess sequencer 12.

hi gher speed) i s desi r abl e i n t erms of addr ess out put .

However , f urt her perf ormance i mprovement (i . e. ,

10 SUMMARY OF THE I NVENTI ON

I n t he above descri bed pr i or art , t he second

address

A,+1 i s

del i ver ed by t he address sequencer t o

t he out put buf f er at t he t i me of t he t r ai l i ng edge of

t he f i r s t Gclock ycl e.

t o the out put buf f er at t he l eadi ng edge of t he @clock

si gnal . Thus one hal f of a cl ock cycl e i s gai ned or

each addr ess bur st .

I n accordance wi t h t he

15

i nvent i on, i nst ead t he second addr ess A,+1 i s del i ver ed

Af t er provi s i on t o t he out put buf f er of t he f i r s t

2 0 address A, ( whi ch i s ext er nal l y suppl i ed as i n Fi g. 1B)

t he external addr ess l i ne i s di sconnect ed f r omt he

out put buf f er

by

an ext ernal address enabl e swi t ch, and

an i nter nal addr ess enabl e swi t ch whi ch connect s t he

addr ess sequencer t o t he out put buf f er i s cl osed,

subsequent i nt er nal l y generat ed addr ess A,+1 t o t he

' out put buf f er , al so as i n Fi g. 1B. Then, dur i ng t he

t i me t hat t he st ar t addr ess A, i s bei ng pr ovi ded t o the

out put buf f er, t he addr ess s equencer oper ates t o

address es of each bur st are t her eby each provi ded t o

t he out put buf f er appr oxi matel y 1/ 2 of a c l ock cycl e

ear l i er t han i n t he pr i or ar t of Fi g.

IB.

The ext ernal l y provi ded addr ess and t he addr ess

out bot h begi n wi t h t he same addr ess A, whi ch i s t he

i ni t i al addr ess i n t he bur st , whi l e us i ng t he pr eset

25

al l owi ng t he address sequencer t o pr ovi de t he

3 0

cal cul at e t he subsequent address A +1. The out put

3 5

-3-


9/179

si gnal t o advance t he counti ng of t he sequence by one

count .

Theref ore,

t he address sequencer i s pr eset t o

address

A,+1

( t he second addr ess i n the bur st) f ol l owi ng

f i r st c l ock s i gnal ar r i ves at t he addr ess sequencer ,

t he address sequencer output i s sampl ed by enabl i ng t he

i nt ernal address enabl e ( second) swi t ch and di sabl i ng

t he ext ernal addr ess enabl e ( f i rs t ) sw t ch. The

10 addr ess sequencer output i s updat ed wi t h each ri si ng

edge of t he cl ock si gnal @clock.

Ther eby t he addr ess

sequencer gener at es each addr ess one cl ock cycl e ahead

of t he ti me that address woul d have been generat ed i n

t he pr i or ar t ,

and t he addr ess out put i s suppl i ed t o

t he out put buf f er

1/2

cl ock cycl e ahead of t he pr i or

ar t ( Fi g. 2B) t i m ng. As i n t he pr i or ar t , t he addr ess

sequencer i ncl udes a mast er/ sl ave count er. However, i n

accor dance w t h t he i nvent i on and i n order t o set t he

addr ess sequencer i ni t i al l y to t he second addr ess

A n + l ,

t he master si de of t he counter

i s

i ni t i al l y

set

t o

val ue An,

and t he sl ave si de of t he count er i s

i ni t i al l y set t o val ue

A,+1.

i ncr ement al t i m ng advant age over t he pr i or art .

5

t he ext ernal l y pr ovi ded st art address A,. When t he

15

2 0

Thi s pr ovi des t he desi r ed

The pr esent i nvent i on i s appl i cabl e speci f i cal l y

25 t o bur st DRAM ( dynamc RAM) oper at i ng i n page mode, and

i s

al so appl i cabl e t o ot her t ypes of bur st memory usi ng

sequent i al t ype addr essi ng.

I n accor dance w t h the i nvent i on, operati on of t he

addr ess generator i s t he same as i n t he pr i or art

3 0

except dur i ng t he preset cycl e. Thus t he per f ormance

advantage i s gai ned dur i ng t he pr eset por t i on of t he

address bur st .

cycl e ahead of t hat provi ded i n t he pr i or art , t hi s

i mproves t he oper ati onal per f ormance of t he syst em i n

whi ch t he burs t memor y is i ns t al l ed.

Si nce t he addresses ar e output one- hal f

35

-4-


10/179

BRI EF DESCRI PTI ON OF THE

DRAWNGS

Fi gs.

IA, I B

show pr i or art addr ess gener ator s.

Fi gs .

2 A ,

2B

show t i m ng di agr ams

f o r

t he pr i or

"

art address generat ors of r espect i vel y Fi gs .

lA,

1B.

wi t h t he pr esent i nvent i on.

generat or of Fi g. 3 .

an

v

5 Fi g.

3 '

shows f l Aaddr ess gener at or i n accor dance

. /

Fi g.

4

shows

a

t i m ng di agram f or t he addr ess

Fi g. 5 shows a schemati c of t he i nter nal addr ess

10 enabl e swi t ch, ext ernal address enabl e swi t ch, and

out put buf f er i n accor dance wi t h t he pr esent i nvent i on.

Fi g.

6

shows a count er i n accordance wi t h t he

pr esent i nvent i on.

Fi g.

7

shows det ai l of one cel l

of

t he count er

of

Fi gs .

8 ,

9 ,

and

10

show ci r cui t r y

or

generat i on

15

Fi g. 6 .

of t he t i m ng s i gnal s f or t he addr ess generat or i n

accor dance w t h he r esent i nvent i on.

Fi qs 11 show$ a t i m ng di agr amf or an addr ess

d

enst

11

Pb

A

20

generat or i n accor dance w t h t he pr esent i nvent i on.

DETAI LED DESCRI PTI ON OF THE I NVENTI ON

Fi g. 3 shows i n a bl ock di agr am seri al addr ess

generat or

18

i n accor dance wi t h t he i nvent i on. Addr ess

buffer 2 2 ,

ext ernal address enabl e swi t ch

2 4

(as

i n

Fi g.

1B)

act uated by an ext ernal address enabl e contr ol

s i gnal

2 8 ,

and i nt ernal address enabl e swi t ch

26 (as

i n

Fi g.

1B)

act uated by an i nt ernal address enabl e contr ol

3 0

s i gnal

30.

Thus t he seri al addr ess generat or

of

Fi g.

3

appear s i n t he bl ock di agr amt o

be

s i m l ar t o t he

ser i al addr ess gener at or of Fi g.

1B;

t he di s t i nct i on i s

i n t he i nt er nal st r ucture and oper at i on

of

address

sequencer

20,

whi ch di f f ers s i gni f i cant l y

from

address

25

generat or

18

i ncl udes address sequencer

20,

out put

35

sequencer

12

of Fi gs .

1 A

and

1B.

/

i

/

. I ,

- 5 -


11/179

5

10

15

20

2 5

i

30

J

35

Sequence cont r ol si gnal 32 (as i n t he pr i or art )

det er m nes whet her address sequencer 20 i s an up or

down count er . I nput si gnal s on l i nes 34, 36 and 38 are

convent i onal ( as i n t he pr i or art) . The out put addr ess

( I f addressoutt l ) i s pr ovi ded on l i ne

40 .

Thi s ci r c ui t ,

l i ke t hat of Fi gs .

1A

and

1B,

i s a par al l el devi ce

pr ovi di ng a mul t i - bi t addr ess. Hence addr ess l i ne 34,

t he out put f r omt he address sequencer on l i ne

42,

and

t he addr ess out l i ne

40

each repr esent mul t i - l i ne

busses wi t h as many l i nes

as

t here are addr ess bi t s i n

t he par t i cul ar appl i cat i on.

Fi g.

4

i l l us t r at es t i m ng f or t he address

generator of Fi g.

3 ,

and spec i f i cal l y t he t i m ng for

ext ernal addr ess swi t ch 24 and i nt ernal address swi t ch

26

as cont r ol l ed r especti vel y by t hei r cont r ol s i gnal s

28,

30 of Fi gur e 3 . I ni t i al l y, external addr ess enabl e

swi t ch

24

i s cl osed ( t he ext ernal addr ess enabl e

cont r ol s i gnal

28

i s hi gh) t hus pr ovi di ng t he

ext er nal l y pr ovi ded addr ess on l i ne

34

di rect l y to

buf f er

2 2 .

Af t er t he i ni t i al addr ess A ( whi ch i s

external l y pr ovi ded) i s pr ovi ded t o buf f er 22, t he

s i gnal

@clock

goes l ow, and t he ext ernal address enabl e

cont r ol s i gnal

28

goes l ow, t hen t he i nt er nal addr ess

enabl e si gnal 30 goes hi gh, cl osi ng swi t ch 26. At t h i s

t i me t he addr ess s equencer

20

has gener at ed t he second

address A,+1.

As

seen i n t he t i m ng di agr am of Fi g.

4 ,

gener ati on of t he second address A+1 overl aps wi t h

provi si on of t he st ar t addr ess A. Thus wi t hi n t he

f i r s t t wo

clockkar

l l of s ta r t address

A,

and

second addr ess

A,+1

ar e out put t o buf f er

22,

i n cont rast

to

t he pr i or art of

Fi g.

2B

i n whi ch onl y

1 1/2

addr esses are out put t ed i t hi n t he f i r st t wo

occur r ences of cl ock&%

* clock-

Thi s hal f - c l ock

cycl e advant age i s t he chi ef benef i t of t he pr esent

i nvent i on. Thus t he gener ati on of addr esses ( Addr ess

-6-

?


12/179

sequencer out " i n Fi g. 4 ) i s one cl ock cycl e ahead

of

t hat i n t he pr i or ar t , and t here i s al so a hal f c l ock

t i m ng advantage i n t he out put addr esses ( "Addr ess

out" ) i n cont rast t o t he pr i or ar t

o f

Fi g. 2B.

I n one embodi ment t he seri al addr ess generat or of

Fi g.

3

i s f or use i n a burst

RAM

operat i ng i n page

mode, wi t h t he ext ernal l y pr ovi ded addr ess bei ng t he

f i r s t ( s t ar t ) address f or each page. Ther ef or e f or

exampl e a RAM chi p havi ng 512 wor ds per page r equi r es

sequencer i s a ni ne-bi t count er .

generator i n accor dance w t h t he i nvent i on i s al so be

sui t abl e f or ot her ( non- page mode) t ypes

of

s er i al l y

generat ed addr esses, wi t h t he addi t i on of convent i onal

st op c i rcui t ry t o term nat e a burst of predet erm ned

l engt h.

I t i s t o be appreci at ed t hat t he ser i al addr ess

generat or

o f

Fi g.

3

i s

used i n pl ace of convent i onal

seri al addr ess generator of Fi gs . 1A,

1B

as a port i on

pr ovi ded on l i ne

4 0

i s convent i onal l y connect ed t o an

address decoder whi ch sel ect s t he desi r ed memory cel l

or cel l s t o be wr i t t en t o or r ead f r o m

of t he RAM chi p i s not i l l ust r at ed herei n as bei ng

5

10

ni ne bi t addr esses, i .e. , 29 = 512. Thus, t he address

The ser i al addr ess

15

20

t ypi cal l y of a chi p. The addr ess out si gnal

( The r emai nder

25 convent i onal .

)

Fi gs . 5 t hr ough 10 show a det ai l ed schemat i c

of

one embodi ment of t he present i nvent i on,

corr espondi ng

t o t hat shown i n t he bl ock di agr amof Fi g. 3 except

t hat t he sequence cont r ol i s not shown, due t o onl y

3 0

upcount i ng bei ng avai l abl e. I n Fi gs.

5

t hrough

10

t he

Smal l number s adj acent each l ogi c gat e

i ndi cat e t he

wi dt h ( i n m cromet ers) of each t ransi st or gat e of t he

l ogi c gat e. Thus, llPlr i ndi cat es t he wi dt h of a

P

channel t r ansi st or gat e and llN1lndi cat es t he wi dt h of

3 5 an N channel t r ansi st or gat e. The gate l engt h i s equal

for al l t r ansi st ors except wher e a t wo number not at i on

-7-


13/179

5

10

BLOCK DI AGRAM

-

FI G. 3

St art addr ess

( An)

PRESET

External

Address

I nte rnal

Addr ess

i s used i . e. , t t48 /211means t he t r ansi st or gat e wi dt h i s

48

m cr ometers and t he t r ansi st or gate l engt h i s

2

m cromet ers. The st andar d ( def aul t ) t r ansi st or gat e

l ength i s 1.2 m cr ometer s, f or t hi s embodi ment .

di agramFi g.

3

and t he corr espondi ng si gnal

desi gnati ons i n schemati c Fi gs.

5

t o

IO,

and i n t he

cor r espondi ng t i m ng di agr am

of

Fi gs

1s;

t her e i s no schemati c equi val ent

to

t he sequence

cont ro l s i gnal i n Fi g. 3 si nce as expl ai ned above the

ci r cui t s hown i n t he schemati c

of

Fi gs . 5 t o IO uses

"up count i ng" onl y and does not have a down count i ng

mode opt i on.

Tabl e 1 shows t he si gnal desi gnati ons i n t he bl ock

(AI, 1::L:

I n Tabl e 1

SCHEMATI C - FI GS. 5-10 TI M NG CHART

- FI G. 11

Same Yn

Same Same

Addr ess

BN, ( Burst Address

N)

Addr ess

An

Sequencer

15

Sequence

cont ro l

Ext erna

1

Addr ess

Enabl e

I nte rnal

Addr ess

Enabl e

Address Out

25

( up count i ng i s i nherent

so

th i s cont r ol i s not

r equi r ed)

AH ( address Hol d) AH

[ f unct i ons as external

address l atchi ng and

di sabl e at s ame t i me]

BAEN- ( Burst Addr ess BAEN-

Enabl e- )

Y,-L,

YmLl

Y,-R,

YmR

( t wo Addr ess Out

pai r s per s i ngl e

address)

, i

30


14/179

( Not Shown)

Tabl e

2

shows t he ext ernal l y pr ovi ded i nput

5

s i gnal s / l i nes f o r t he ci r c ui t

of

Fi gs .

5

t o

10.

TABLE 2

- -

-

-

BCn ( Burst Count er Car r y

-

Output) BCN- 1 ( Burs t

10

N ME DESCRI PTI ON

A,

Ext ernal address

vcc power

L l ef t decoder address enabl e

R r i ght decoder address

YS

AS Addr ess Sense

enabl e

col umn addr ess power up

f-

c.

BE/ OE

AH

ATDOE

WE-

WE1

15

~-

mu1 pl ex

Burst enabl e/ out put enabl e

i nput

Ext ernal address enabl e

Output enabl e contr ol

W i t e Enabl e-

W i t e Enabl e

20

ROW - col umn address

25

-9-


15/179


16/179

ext er nal addr ess enabl e si gnal , cont r ol l i ng swi t ch

5 0

i n Fi g.

5

whi ch cor r esponds to swi t ch 2 4 i n Fi g. 3 .

42

of Fi g.

3

i s desi gnat ed si gnal BN i n Fi g. 5, and i s

swi t ch

26

i n Fi g.

3 .

Sw t ch

52

i s cont ro l l ed

by

t he

i nt ernal addr ess enabl e si gnal whi ch i n Fi g. 5 i s

desi gnat ed BAEN- . ( The i nver se of si gnal BAEN. )

It

i s

t o be under st ood t hat t he si gnal BN i s pr ovi ded f r om

bel ow.

Buf f er

22

of Fi g.

3

cor r esponds t o t he buf f er

ci r c ui t r y 5 6 of Fi g. 5. The out puts of t he buf f er

c i r c ui t r y of Fi g. 5 ar e des i gnat ed as a ' t l ef t l lnd

(Yn-=,

Y Yn R and Y m R . ( Note t her e ar e t wo decoders ,

one f or t he l ef t memory bl ock and t he other f or t he

r i ght memor y bl ock. ) The out put of buf f er

56

cor r esponds t o one bi t of t he addr ess out si gnal of

Si m l ar l y , t he i nt er nal addr ess suppl i ed on l i ne

5 pr ovi ded as an i nput

t o

swi t ch 52 corr espondi ng

to

10 t he count er por t i on of t he address generat or, descr i bed

15

" r i ght " Y ( col umn addr ess) and t he i nverses t hereof

2 0 Fig. 3 .

The l ef t and r i ght (L, R s i gnal s of Fi g. 5

cont r ol t he buf f er 56 out put s, t o pr ovi de address

s i gnal s

to

l e f t

or

r i ght decoder s r especti vel y.

provi ded i s col umn address power up si gnal

YS,

whi ch

di sabl es t he i nput addr ess pass when t he chi p i s i n the

pr echar ge st at e.

t he c i r c ui t of Fi g.

5

( desi gnat ed BA,) i s an i nput t o

t he associ ated Count er Cel l , as descri bed bel ow.

30

addr ess sequencer

20

of Fi g.

3

pr ovi di ng

a

ni ne- bi t

Al so

25

The i nt er nal st art addr ess out put by

Fi g.

6

shows t he counter ( cor r espondi ng t o t he

count .

60-2,

...,

60- 9 connect ed as shown. Each cel l has as a

f i r st i nput t he i nt er nal st art addr ess BA. The second

c el l i nput i s the Carr y si gnal desi gnat ed BC,l f r om t he

si gnal PRESET, and a second t i m ng si gnal

qclock.

The count er has ni ne i dent i cal cel l s

60-1,

35 pr i or cel l . Each Cel l al so recei ves a f i r s t t i m ng

The

-11-


17/179

cv

out put of each count er cel l i s an out put addr ess bi t BN

( whi ch i s t he address out)

whi ch t hen goes t o buf f er 5 6

of Fi g.

5, and a second out put BC, whi ch i s t he car r y

val ue

to

t he subsequent cel l .

occur s onl y once i n t he addr ess sequencer 20 and

ser v i ces al l ni ne addr ess buf f er c i r cui t s ,

of

whi ch

onl y one i s shown i n Fi g.

5 .

5

I t i s t o be under st ood t hat t he count er of Fi g. 6

Fi g. 7 shows det ai l s of one of t he cel l s of Fi g.

10 6 . Si gnal BC,,l i s the car ry i nput s i gnal , whi l e s i gnal

BA, i s t he external addr ess s i gnal .

are @clock and PRESET ( and t hei r i nverses). The cel l

out put i s t he t t r eal l tddr ess BN and a carr y val ue Bc,

t o t he next cel l . The cel l of F i g. 7 i ncl udes

15

convent i onal l y a l ef t - hand s i de whi ch i s t he 9ts l ave11

s i de 70 and a r i ght hand si de whi ch i s t he 9nast ert 9

s i de 72 ( i ndi cat ed by the br oken l i ne). Thus, t here

are t wo l at ches 70a, 72a one or each si de of t he

count er cel l , w t h one l atch at any one ti me updat i ng

i t s val ue whi l e t he second l at ch i s hol di ng t he

pr evi ousl y cal cul at ed dat a and tr ansm t t i ng i t as

out put .

Fi gs . 8 , 9 and

10

show ci r cui t r y for gener ati ng

t he t i m ng s i gnal s

f o r

t he ser i al addr ess generator .

The t wo exter nal l y pr ovi ded ti m ng si gnal s are RAS and

CAS-PAD. These i n t ur n gener at e as shown t he i nter nal

t i m ng si gnal s. The sequence i s t hat t he i nput c l ock

s i gnal CAS-PAD gener at es t i m ng si gnal C A S l b whi ch i n

t urn generat es si gnal BAEN- whi ch i n t urn generat es

30 s i gnal @clock. The @clock s i gnal

of

Fi g. 3 i s shown i n

t he t i m ng di agr amof Fig&

1 1 .

t i m ng s i gnal CAS1b whi ch i s a t i m ng si gnal

for

t he

above- descri bed count er ci r cui t r y. Note t hat si gnal

CASlb

i s i n par t det er m ned by t he si gnal BM (burst

The t i m ng s i gnal s

20

2 5

)J

/ l ( b l

Fi g.

8

shows t he ci r cui t r y whi ch pr ovi des t he

3 5

-12-


18/179


19/179

CL AI M S

.. -. .

We claim:

5

i

10

15

2 0

25

3 0

3 5

generator; and

inal of the address

generates a second

+r il e a first

generator;

switch.

comprising:

enable switch; and

enable switch, wherein

duration

o f

the first: a

addresses, and

enable switch is closed

addresses.

-14-

,,


20/179

3 . The addr ess gener at or of Cl ai m 1, wher ei n t he

second addr ess i s out put t o t he out put t erm nal

of

t he

addr ess sequencer onl y when t he i nter nal addr ess enabl e

swi t ch i s cl osed.

5

4 .

The addr ess gener at or

of

Cl ai m

1,

f ur t her

compri si ng a buf f er seri al l y connect ed bet ween t he

out put t er m nal of t he addr ess s equencer and t he out put

t erm nal

of

t he address generator .

1 0 .

Cl ai m 2 , further

7 . The addr ess gener at or

of

Cl ai m

2 ,

wher ei n t he

25 address sequencer i ncl udes a count er havi ng a mast er

por t i on and a sl ave por t i on.

8 .

The addr ess gener at or of Cl ai m

1,

f ur t her

compri si ng means f or pr ovi di ng an exter nal l y gener at ed

ext ernal l y generat ed address i s a f i r s t addr ess of a

page of t he r andom access memory.

30

addr ess t o the addr ess i nput t er m nal , wher ei n t he

f o r a ser i al l y addr essed

-15-


21/179


22/179


23/179


24/179

Atty. Docket No. M-2595 US

I hereby appoint the following attorney(s)

and/or agent(s) t o prosecute th is application anc

to transact all businesa in th e United States Patent and Trademark Offic e connected

therewitht

Alan H. MacPherson (24,425); Thomas S . MacDonald (17,774); Richard Franklin

(19,128)r Kenneth E. Leeds (30,566); Paul J. Winters (25,246); Brian D. Ogonowsky

(31,988); David W. Heid (25,875); Guy W. Shoup (26,805); Forrest E . Gunnison

(3 2, 89 9) ~ orman R. Klivans

3 3 . 0 0 3 ) ;

David

I.

arroll (29,903); Edward c. Kwok

(33,938); Patrick T. Bever (33,834); David E. Steuber (25,557); Michael Shenker

(34,250); Laura Terlizzi (31,307); T. Lester Wallace (.34,748)1 Ronald J. Meetin

(29,089); James D. Ivey (37,016); Andrew C. Graham (36,531); Ken Jo hn Koestner

(33,004); Hark P. Kahlar (29,178); and Stephen A. Terrile (32,946).

Address all teleph one calls to porman R. Klivans at telephone no. (408) 283-1222

Address all correspondence to Norman R. Klivans

SKJERVEN, MORRILL, MacPHERSON, FRANKLIN & FRIEL

25

METRO

DRIVE. SUITE 700

SAN JOSE, CALIFORNIA 95110

I hereby declare that all statements made herein of my own knowledge are true and that all

statements made on information and belief are believed to be true; and further that thes e

Statements were made with t he knowledge that willful false statements and t he lik e so made

are punishable by fine or imprisonment, o r both, under Title 18, United States Code,

s

1001

and that such willful false statements may jeopardize the validity of the application or any

patent issued thereon.

Full name of sole or first inventor Jinvonq Chuna

Inventor's signature Date

Residence

LOB

Altos Hills.

Post Office Address 12445 Robleda Road

California U.S.A. Citizenship U.S.A.

Los Altos Hills. CA 94022

Full name of second joint inventor, if any Michael A. Murrav

Inventor's signature Date

Post Office Addrese 16432 NE 1 th Street

Citizenship

U.S.A.

esidence

ellevue. Waehinaton 9800 2

Rev.

931109

- 2 -


25/179


26/179

Fig. 2B

(prior

art)

-

.

...

..-.

.

-.

.c i .

- - . .

. _

. . .


27/179


28/179


29/179

v

R

.%J

7 8 26

5 5


30/179

08/265535

c

t

P

3


31/179


32/179

F8/265535

l l

P a

M 65535


33/179


34/179

I

\

/

:

I

J

I

X

3

.e

7

\

08/265535

v,


35/179


36/179


37/179


38/179


39/179

the undersigned at (408: 283-1222, if there are any questions.

This form is being submitted in triplicate.

Respectfully submitted,

Norman

+ P . D w - d

. livans

Attorney

for

Applicants

Reg. NO. 33,003

1 ereby certify that this correspondence is being deposited with the

United States Postal Service ae flrst cla ss mail In en envelope

cddressed to: Commissioner

of

Patentsand

Trademarks,

Washington,

D.C., 20231,on

- 2 -


40/179


41/179

. .

Atty. Docket

No.

M-2595 US

I 'hereby appoint the following attorney( ) and/or agent(s) t o prosecute this' application and

to transact all business i n the United States Patent and Trademark Office connected

therewithr

Alan H. MacPherson (24 423 ; Thomas

5 .

MacDonald (17,7741; Richard Franklin

(19,128); Kenneth

E.

&

$0,5661; Paul

J.

Winters

( w ) t

rian D. Ogonoweky

(31,988)j David W. Held (25, 75); Guy W. Shoup ( 2 6 , 8 0 5 ) t Forrest E. Gunnison

(32,899); Norman

R.

Klivana J;003 ; avid H. Carroll -3); Edward C. Kwok

(33,938); Patrick

T.

Bever 33 8 3 4 ) ; David E. Steuber t u ) ; Michael Shenker

'

d

34,250); Laura Terlizzi ,J07);

T.

Lester Wallace w);onald

J.

Meetin

(29,089); James D. Ivey

( 3 m ;

ndrew

C.

Graham (1 Ken John Koestner

(33,004); Mark P. Kahlerm ;nd Stephen A. Terrile (-6),.

I

.,

one no. (408) 283-1222

..-

A --.-

the like

so

made

Full name of sole or first inventorw

-

-,..-.

or's

nce

ffic

3v. 931109

- 2 -


42/179


43/179


44/179

Ser i al Number : 0 8 / 2 6 5 5 3 5

Art Uni t : 2511

-3-

Claim I i e j e c t i o n s

- 35

USC

102

4. The fo l l ow ng i s a quotat i on of t he appr opr i at e par agr aphs

of 35

U. S. C.

102 that form t he basi s f or t he r ej ecti ons under

t hi s sect i on made i n thi s Of f i ce act i on:

A

person shal l be ent i t l ed t o a pat ent unl ess --

(a)

t he i nvent i on was known

or

used

by

ot hers i n t hi s

count r y,

or pat ent ed or descr i bed i n a pr i nt ed publ i cat i on

i n thi s or a f or ei gn count r y, bef ore t he i nvent i on t her eof

by t he appl i cant f or a patent .

5. Cl ai ms 1 - 4 ,

8 -10

are r ej ect ea under

35

U. S.C.

102(a)

as

bei ng ant i ci pat ed by t h e Pr i or ar r

as

shown i n Fi gs. 1B and

2B).

The Pr i or art d i s c l o s e a s er i al il ic i e s s yener at or havi ng al l t he

f eatures as rec i t ed i n c l a i m

1-4

9 - 9

and met hod

of

gener ati ng a

sequence

o f

address as

r e c i i 4

i r i c l a i l ?

10.

Allowable

S u b j e c t

Matter

6.

re j ected base c l ai m b u t would be al l ovabl e i f r ewr i t t en i n

i ndependent f o rm i nc l udi ng a i l

of.

the l i m ta t i ons o f t he base

cl ai m and any i nt erveni nq cl ai ms.

Cl ai ms 5-7 are obj ected t o a s bei ng dependent

upon

a

Conclusion

7 .

The pri or ar t made of r ecor d dnd r:ot r el i ed upon i s

consi dered per t i nent t o appl i cant ' s di scl osure.

Ogawa (5,097,4471,

Ehy

c-t a.

[5,:46,431)

and Mor i

(5,260,905)

di scl ose sem conduct or i w m o r y de-^ I rv:: I I ~ I V ny ser i al access

memor y.


45/179

.----- - -

Serial Number: 08/265,535 -4-

Art Unit: 2511

8 .

to

S. M a i at telephone number (703) 305-3497.

Any

inquiry concerning this communlcation should be directed

S .M. PRMARY EXAMINER

December 4, 1994

GROUP

2500


46/179


47/179


48/179


49/179


50/179


51/179

...

F G.3A

F

G.3B

r

SAS

S AS

S A T

S A D

MAD

S A

S O M

Sbeet

3.

of 12, 5,Q97.,$47

I I

I

I

I

...

CAD n - l

x n X n+l

.

I I

i

I I

t

I

SA

t I '

I I

SOM

I

L A t


52/179


53/179

US. atent

Sheet

5

of 12 5,097,447

-

m


54/179


55/179


56/179


57/179


58/179


59/179


60/179


61/179


62/179


63/179


64/179

7

5,097,447

8

flops 330

-33m. and a group-B redundancy address

supplied from the ROM.

h e

decision results AG and

B G which are derived from the redundancy decision

circuits

36

and 37, respectively,

are

supplied

to

a gate

and latch circuit

38,

which outputs the redundancy

switching signal SOM blued on he results AG and BO

when the serial access strobe signal SAS rises.

Refemng

IO

FIG S. 7(A), 7(B).

7(C), 7@),

7 E ) . 7 0 ,

7(G), 7 a ) . 7(1). 7(J). and 7(K). the slave address S AD

related

to

the group

A s

renewed each time the clo ck

signal

81 rises,

that

is,

the

serial

access strobe signal

SAS

falls.

T h e

master

address

MAD

related

to

the

group

A

is renewed eac h time the cloc k signal

@I

rim.

that

is,

the serial access strobe signal

SAS

ises. When

the group-A counter 300 makes a round

of

counting, the

carry circuit 32 outputs

the

carry

QA. n

esponse

to

the

carry

QA.

he slave address

SAD

related

to

the group

B

is renewea when the clo ck signal G2 rim hat is. when

the serial

access

strobe signal SAS falls, and the master

address MAD related

to

the group

B

is renewed when

the clock signal

@Irises.

that is, the serial acccss strobe

signal SAS r k s .

FIG. 8 ir a diagram of he entire structure of a semi-

...

signal

SAT.

a clo ck signal cO5~shaving he m e iming

as

the serial access strobe signal SAS, and a clock signal

CpSAj

which

is

M

nverted signal

of

the signal SAS. An

address counter 50 rcceives the column address signal

J and all the clock signals supplied from the clock genera-

tor 496, and outputs the slave address S AD and the

ms ter address MAD. A redundancy decision circuit 51

compares the slave address signal

SAD

with a redun-

dancy address

signal

supplied from a read only memory

10

@OM) 49c. and outpuls a redundancy decision signal

Sx.

h e

edundancy address

signal

indicates the redun-

dancy

cells

provided in the memory

cell

m a y

43.

A

gate and latch circuit

52

temporarily

stores

the redun-

dancy decision circuit

SH,

nd outputs the same s the

T h e

decoder

54

consists

of fust

and second decoders

5 Q

and

5 4 6 BS

shown

in FIG. 9.

When

the redundancy

switching signal SOM

s

inactive, the

f i t

d d e r 4 0

is selected.

On

the other hand, when the redundancy

20 switching signal SOM

is

act ive, the xc ond decoder

5 4 6

is

wlected. Each bit of the decoder output

is

supplied

with the gates of two

MOS

ransistors

T1

and T2,

which

arc

coupled to corresponding signal

lines

ofa bus

15

redundancy switching signal

SOM

to

a

decoder 5 4 .

conductor memory device according

to a

preferred

58. A

data rcgisler 53 has

a

storage capacity equal

to

embodiment

of the

present invention. Referring

toFIG.

25

one line of the memory

cell

array

43,

and includes a

8, the memory device includes a R A M 40 and a SAM group 530 of register

cells

and a group 536 of redun-

(%rial acccss memory) 41.

T h e

RAM

40

is configured dancy register

cells.

ach

of

which is coupled lo a corrc-,

BI follows.

The RAM 40

is supplied with an external sponding pair o f

MOS

ransistors such

as T1

and

T2.

address signal which has

been

multiplexed.

An

address

T h e

edundancy register

cells a re

coupled

to

the con e.

huller

42 receives the

externa l

address signal and sepa-

30

sponding redundancy

cells

provided in the memory Cell

rarely outputs

a

row address signal and a column ad- array

43. T h e

decoder

54 selectsoneof

the register

cells

dress signal.

A

row decoder

44

decodes the row address on the basis of the supplied master address

MAD. ' Ihe

signal, and selects one word line from among

a

plurality data register 53

is

connected

to

the bit lines

of

the mem-

of word liner provided in

a

memory cell array where a

o ry

cell array

43.

Turning

to

FIG . 8. a

serial

input/out-

plurality of memory ce lls MC arc arranged in an array.

35

put buffer

56 is

interposed betwee n a serial input/output

Some ofth e memory cells arc redundancy cells located terminal

55

coupled to an external data line not shown)

at a prcdctermined area in the memory cell array

43.

and the data register

53,

and passes serial data

in

the

The redundancy

cells

are replaceable with (is.. used in

bidirection.

place of) defective cells in the memory cell array 43. A

FIG.

0 is a circuit diagram o f he address counter 50.

column decoder 45 decod es the column addrcss signal,

40 T h e

ddrers counter 50 is made up ofmluter.slave type

and

relccts

one bit line out of

a

plurality of bit lines in flipflo ps

FFo-FF.

which amount to the

number of

bits

the memory

cell

array

43. A w n w

amplifier and

I/O

of the column address signal.

gate

46

amplifies the potential

of

he selected bit line,

FIG.

11 is a

circuit diagram of the muter-slave type

m d performs data reading and writing. An input/out. flip-flop

FFo

E a c h of the other flip-flops FFl-FF"

s

put buffer

48

is interposed between a random input/out-

45

configured in the

snme

manner

m

he flip-flop

FFo

A

put

terminal 47 and the sense amplifier and

I/Ogale 46

slave part S

of the

flip-flop FFoincludes

a

f irst gate

64 .

and pa w s parallel data in the bidirecrion.

a v c o n d

gate

71

and

a

slave-side flipflop

ED.The

fmt

A clock generator 490 is supplied from an extemsl gate 64

is

made up of two Pchannel MOS ransistors

device such as a

CPU

with

a

row addrtss strobe signal

60

1, and two N-channel MOS transiston 62.

a

m,

column address strobe Signal

m,

write en-

H)

which

are

totem

pole

connactcd.

T h e

econd gate 71 is

able si

nd

m,

nd a

transfer signalm.

he

transfer

made

up

of

three P-channef

MOS

ransistors

65,66

and

signal

h nstructs

the R A M

40

and the SAM 41 to 67, and chree N-channel MOS transiston 68 .69 and 70,

operate

in

synchronism with each other.

T h e

clock which are

totem

pole

Connected. T h e

slave-side flip

generator 494 g e n e n t n the initial counter addreu

set-

flop

80

is made up of four Pchannel

MOS

ransistors

cing signal SAT. which is suppliedto I clock generator 55 72. 73, 74 and 75, and four Nchannel MOS

transiston

49b

related

to

the

serial

access

memory

41.

Further, the

76 .77 ,78

and

79.

T h e

fmt

ate

64

inpuu

a

bit &ofthe

clock

generator

490

generates

various

control signals,

column

ddrers signal when the cl oc k signal aSArb

L

which u e upplied to a

RAM pori 57

coupled

10

the @ow).' and

the

clock

Signal -

is

"H high)

The

slave-side flipflop

80

latches the input addrers bit

erminal 47.

On he other hand, the arid a memory (SAM) 60 when the c lo ck s igna l a m s w it ches

from "H"

o "L"

41 is

configured

as

follows.

Tbe

clock

generator 496

in

othe r words, &e clo ck signal switches from

receives a e nitial counter address setting signal SAT % to

"H),

hat is, when the wrial access strobe signal

from the clock generator 490 and the serial

access

SAS falls. Then the slaveiidc flipflop 80 OU I PU U

the

strobe

signal

supplied from th e CPU Tor example. and

latched bit & a s a bit Ao'

(SAD) o

a

m s t e r

part M of

generates the following cloc k signals. Th at is, the cloc k

65

the flip-flop F Foa nd the redundancy decision circuit

51

generator

496

generales

a

clock signal

Oarof he m e

r b o m

in FIG.

8.

t h i n g as

the

initial cou nter address setting signal SAT,

The

muter part

M

includes a

fmt gate

85. and a

a clock signal which

is an

inverted signal

of

the

master-side flipflop 92.

The first

gate

85 is

made up

of


65/179


66/179

5,097,447

11 12

said second serial access addrcsr by a half

ofone

period

of

said pulse signal.

4.

A semiconductor memory device as claimed i n

claim

1,

wherein said selecting means includes gate and

latch means for inputting the comparison result from

5

snid redundancy decision means and outputting the

same

as

a redundancy switching signal in synchronism

with the second edge o f said pulse signal.

5. A semiconductor memory device

as

claimed in

claim

4,

wherein raid gat e and latch means is outputting IO

said redundancy switching signal during one period of

said pulse signal from said second edge thereof.

6.

A semiconductor memory device

as

claimed in

claim 1, funher comprising clock generating means for

generating fin; and second clock pulses which are

180

I5

said serial accesz memory cornprishg:

degrees out of ph ax with each other. and said first and data register means or storing data to be written into

second address generating

mcans

generate said first and

or

read from said random access memory and to

be

second seiial access addresses in synchronism with said input from

or

output to an external signal line in

i r s t and wcond clock pulses. respectively.

serial form,

aid data register

means

including a

first group

of

register

cells

and a xcond group

of

claim 6. wherein said first address generating m a n s redundancy cells:

includes

a

slave flip-flop controlled by said first and

first address generating means. provided for each

of

second clock signals, and raid second

address

generat- . said groups o f address bits, for generating a pan o f

ing means includes a master flip-flop controlled by said

a first serial access address starting from

an

initial

first

and second clo ck signals. address for correspond ing one

of

the groups o f

8. A semiconductor memory device as claimed

in

address bits supplied from an external device;

claim 7. wherein said slave flip-flop provided in said second address generating means, provided for each

first address generating means is connected to said mas- ofsaid groups o f address bits and coupled

to

said

ter flip-flop provided in said second address generating related

i r s t

address generating means,

for

inputting

means.

the related pan of said first serial access address

9. A semiconductor memory device as claimed in and generating a part of

a

F o n d s erial a ccess

claim

I.

wherein said first address generating means address

to be

supplied

to

said data register means.

includes a plurality of slave flip-flops amounting to the said first serial access address having the

m e

number

of

bits forming said lint serial access address. wnten ts as said w o n d serial access address and

and said second address generating means includes a

35

preceding said second serial access address by a

prcdetennined time;lurality

of

master flip-flops amounting to the number

of

bits forming said second serial access address. redundancy decision means, provided for each of said

10. A semiconductor memory device as claimed in groups of address bits and coupled to said first

claim 1.wherein said first serial access address is com- address generating means, for determining whether

posed

of

n bits (n i5

an

integral). and said redundancy

do

the pan o fsaid first

serial

a cc es s a dd re ss is th e m e

address is composed o f n bits, and wherein said redun- as a corresponding part of

a

redundancy address,

dancy decision means includes logic gate means for and

corresponding bits o f aid first serial access address and selecting means. coupled to said redundancy decision

said redundancy address and for outputting th e compar-

means,

for selecting one

of

said first and second

ison result.

groups o f said data register

means

on the basis o f

11. A semiconductor memory device as claimed in the comparison results supplied from said rtdun-

claim 10, wherein said logic gate means includes exclu- dancy decision means provided for the groups of

sive-NOR

gates

provided for the respective bits to be address

bits,

said data registered in said data regis-

compared. and

a

NAND gate which receives output Ler

means

being accessed

in serial

form by said

signals of said exclusive-NOR gates and outputting the x) second

serial

.cccss address.

Comparison result.

wherein when ssid recond serial access address

is

12.

A

semiconductor memory dcvice

as

claimed

in

supplied to said data register means, said da~a

s

c ldm 1. funher comprising generating

means

for gentr - input in or output from said data register

means

in

series.

generating means generates stid fint rerial

access

ad- 55 . 18.

A

emiconductor memory device I L ~ laiared in

dress starting form slid initial address when said indica- claim

17,

wherein said fm t add rss

generating means

tion signal b supplied to said fin1 address generating includes

first

counter mcans for inputting said initid

means.

u~ess

ddress supplied from the external device in

13. A m i c o n d u c t o r memory de*

as

claimed

in

Synchronism with a f i ~ tdge of a pulse signal supplied

'claim 1. wherein said initial address corresponds to a

60

from the exrtmal device and for incrementing the re-

column address to be supplied to said random

-

ted pan of aid

f i t

s e d - addrcss in syn chr e

KIlClTlOry.

nism

with the fubKq uenl first edges

of

said pulse signal,

14. A m ico n duct o r m em o ry device as claimed in m d s ai d m n d d dr es s g en er at in g

means

includes

xc

claim 1 funher comprising a read only memory which and counter means for outputting the related pan of

stores said redundancy address.

65

said

f i rs t

serial access address

as

the related pan

o f

said

IS.

A miconductor memory device

as

claimed

in

sccond serial

a c e s address

in synchronism with a

m -

claim

1.

wherein said semiconductor memow device i~ ond edge of said

pulse

signal following said fmr d g e

UI image memory device which handles image data. thereof So that said

first

serial access address derived

16. A

semiconductor memory device as claimed in

claim 2, wherein the first edge

of

said pulse signal is a

falling edge and th e second edge t hereo f is a rising edge.

17. A semiconductor memory device comprising:

a random access memory including a plurality

of

memory cells and parallel rmd/write

means

for

writing data and rending data into and from said

memory cells on the basis of address information;

and

a

serial

access memory coupled

10

said random acce ss

memory,

said address information being divided into groups

each composed of a predetermined number of ad-

dress bits,

..._

7.

A

semiconductor memory device as claimed in

20

25

30

45

ating

an

indication signal, wherein the said first address


67/179

,

. . . . . . . . . . . . . . . . . . . .

. . . . . . . . .

. ..t.y

. _ . _ _ ...+.-.:. : < ,;: 'I ;.:'-

.

. . . . . . .

. . . . . . . . . . . .

....

._..

. . ~ ~ , ~ ,

. . . . . . . .

......

. . . . . . . . . . . . . . .

.... .

. . . . . . .

5

...- ...- : ........... .;...

.-...

: $ ;. -1:

ccpyc: 5;i P.: - - %

.- i

. -

.....

,eq F p n n d M.OS t ian -

rter 190. n transmksion'gatk 160,

+=A

2 0 0

goes

back high and

+I,VA

280 goes back

low.

Fro m 17 to,tg (after ts).,another address may be loaded

onto external address pad 100 in preparation for anoth er

connected via inverter 190. he gate of transistor

170

at 19). Thus, instead

of

inputting a new recall address

also receives address enable input +=A 200. from pad

100.

one may choose instead to use the incre-

The output of transmission gate 160 lows through IO mcnted address on counter outputs 20 lo automatically

bvt1W~210'ahd'ppears' output 220 ,.w hic h hput s recall the next consecutiv e page.'ln this case, during the

:rintoedd.r& dad din g &cii tr yZZS ehc% d

to

address

I:

ubiquent page recall operation.

4 1 . ~ ~

80

going

high

'' kl ecto r c i rcui t

90.

.

. .

ai tz'sends address signals (Ai) 230, which now specify

Another input to address selector circuit

90

is input the address o f he next consecutive page.'through trans-

fAi)Z30,-bvH.hich conn ectsf o transmission gate.240. The. Il..mission gates e . y d nverters 210 o address decoding

output of transmission..gate '240-then Tows through circuitry 225.

invener 210 nd ends upon asoutput 220,which is input

In operation, as discussed above, the address decod-

to the address decoding circuit 225,

as

shown in FIG.

4.

ing circuit 225 shown in

FIG.

4 is designed such that

Transmission gate

24-9,

similarly IO transmission gate

only of the word lines WL , and its associated recall line

A60 , . co mpri ses n-channel transistor 250. pchannel tran-

20

RL , wi ll be a logical 1 or a given page recall operation.

: istor

2 6 0

and inverter

270,

and is controlled b y internal

Thus, for instance, word line W L, may be activated,

address enable input (+I,vA) 280 into the gate of transis- and'then all of the bit lines Blthrough B , are also acti-

vated. Th e recall line RL n s utilized to recall the data

dress stored on the entire page o f cells, i.e. all of the cells

is

as

25 along word line WL,. Th e dita .are retrieved by 'the

Gn ie Jmplifiers, which may

be'convenIiorial'in'dc'sjgn.

fa] &&pz


77/179


78/179

* '

U.S. Patent ' Sep. 19, 1995 Sheet 9

of 16

5,452,261


79/179

(FILE 'USPAT' ENTERED AT

10:

17:28

ON

02 DEC 94)

L1

L 2

L3

L4

L 5

L 6

L 7

8875 S

ADDRESS

(3W) ( COUNTER# OR SEQUENCER#)

7556 S FIRST (2W) ADDRESS

5020 S SECOND (2W) ADDRESS

716 S SERIAL? (2W) ADDRESS?

2084 S L1 AND

L2

1013 S L3 AND L5

30

S

L 4 A N D L 6

FILE

JPOABS' ENTERED AT 10:33:29 ON 02 DEC 94

4257

S L1

8

L 9

L10

L11

L12

L13

L14

L15

L16

L17

721

S

L 2

4 0 9

S

L3

70 S L 4

300 S L 9 A M 3 LID

0 S L11

AND L12

15

S

LS AND L11

30 S

L8

AND L12

62 S

L8

AND L9

4

S

L16 AND PRESET?


80/179

=>

d

his

FILE 'USPAT' EN TERED AT 13:48:56 ON 01 DEC 94)

L1

L2

179S SERIAL ADDRESS

353

S

BURST (5w) (MEMORY

OR

RAM OR DRAM)

L3

L4

8508

S

ADDRESS

(3W)

SEQUENCER OR COUNTER)

100

S

L1

AND L3

FILE 'JPOABS' ENTERED AT 14:Ol:ZOON 01 DEC 94

L5 58

S

L1

L6 39SL2

L7 4016SL3

L8 8SL8ANDL9

L9

8 S L8AND LIO


81/179


82/179

-

365-230.09

AL;

2 5 1 1 SX

C C C Z l

X R 5 / 2 5 G i O C 5

u . v - - u u U ~ ~ I L I ~A ~ U I V TND TRADEMARK

OFFICE

CERTIFICATE OF CORRECTION

Page

1

of

3

PATENTNO. :

5,260,905

DATED

:

November

9, 1993

INVENTOR(S)

:

Toshi k i Mor i

cnrrerted

asshown below:

Col umn 1, L i ne 28, " i " shoul d read - - i n- - .

Col umn

1,

L i ne

68,

"pr ocess posi t i on" shoul d read - - pr ocess.

The- - .

Col umn 2, L i ne 22, "a re , shoul d read - - are ; - - .

col umn

2 ,

Li ne

2 6 ,

del et e "a" ( f i r s t occurr ence) .

Col umn

2,

L i ne 31, " a" ( second occur r ence) shoul d r ead - - at - - .

Col umn 2, Li ne

49,

af te r "ar ray" i nser t

--1--.

col umn 2, Li ne 57, " comput e" shoul d r ead - - comput er- - .

Col umn 3,

Li ne 61, del et e "t her e".

Col umn

4,

Li ne 61,

59

shoul d r ead --69--.

Col umn

5,

Li ne

5,

" l i es " shoul d read - - l i nes - - .

Col umn

5,

L i ne 11, 56 shoul d r ead --57--.

Col umn 5, Li ne 14, 5 6 shoul d r ead --57--.

Col umn

5,

Li ne

33,

" f or m" shoul d read - - f rom- .

Col umn

5 ,

Li ne

5 3 ,

"count er , " shoul d r ead - - count er

8.--..

Col umn 5, Li ne 55, " i n" shoul d read - - of - - .

Col umn

5,

Li ne 56, "o f " shoul d read - - i n- - .

It K catifid that m o r appears in the aboveidentified patent

and

that said Letters Patent is hereby

-


83/179

- I

....

UNITED STATES PATENT

AND

TRADEMARK OFFICE

CERTIFICATE OF CORRECTION

Page

2 of

3

PATENTNO.

: 5,260,9~5

- November 9, 1 9 9 3

ATED

INVENTOR(S)

:

Toshi ki Mor i

torretted

assfiom,

below:

Col umn 5, L i ne

59,

del et e "present ".

itu

certified

that m o r appears

in the above-identified patent

and

that said Letters Patent

is

hereby

-

Col umn 5 , L i ne

60,

af t er " t he" i nser t - - present - - .

Col umn 6, Li ne 26, del et e "a".

Col umn

6,

L i ne 32, del et e "c l ocks" .

Col umn 6 , Li ne 4 1 ,

" i nput t i ng t he" shoul d read - - i nput i nt o- - .

Col umn 7 , Li ne 3 "f or m" shoul d r ead - - f r o m - .

Col umn

7,

Li ne

21,

"t hr ough" shoul d read - - to- - .

Col umn 7, L i ne 2 2 , "t o" shoul d read - - t hr ough- - .

Col umn 7, Li ne

4 0 ,

"out put " shoul d r ead - - out put s- - .

Col umn 7, L i ne 4 1 , af t er "12-1," i nser t - - and- - .

Col umn 7, Li ne

4 2 ,

"one" shoul d r ead - - cor r espondi ng- - ,

Col umn 8, L i ne

19,

af t er " cor r espondi ng" i nser t - - t rans f er - - ,

and del ete "t r ansf er" .

col umn 8, Li ne

25,

"agate" shoul d r ead - - a gat e- - .

Col umn 8 , Li ne 4 3 , "f orm" shoul d read - - f rom- .

Col umn 9, Li ne 1, 13 shoul d read --14--.


84/179

. .

.

- -

. .

-

. ...

.

UNITED STATES PATENT AND TRADEMARK OFFICE

CERTIFICATE

OF

CORRECTION

PATENTNO. :

5,260,905

Page 3 of 3

DATED :

November

9, 1993

INVENTOR(S)

: Tbshik i .

MGri

Itk

ertified hat

error appears in

the

ahowidentified patent and that s a i d Letters Patent ishereby

Wrrected

a~ s hm~n

elow:

Column 9, Line 7 ad

should

r e a d

- - a s - - .

Column 9 , Line 53, "on" s h o u l d read --one--.

Column 10, Line

50,-

"form" should read

--from--.

~ .

Signedand

Sealed fflis

Twentyfourth

Day

of May, 1994 I

Attest

BRUCE

LEmUN

Commirrionrr of Parrnrr

and

T r a d r m o r b

ttestirig

Officer


85/179

U.S. Patent

Nov.

9, 1993

Sheet 1

of

8 5,260,905

se

RAS.CAS

9

DTOE

DT se,


86/179


87/179

U.S.

Patent

5,260,905


88/179


89/179

U.S.

Patent

b

iz

Nov. 9,

1993

I

I

___.

Sheet 5 of 8

. #

Y

2

.c

b

cv

5,260,905


90/179

U.S.

Patent

....

Nov.

9, 1993

Sheet 6

of

8 5,260,905


91/179

U.S.Patent

NOV.8, 1993

Sheet 7 of

8

5,260,905

....


92/179

U.S.

Patent

Nov.

9,

1993

Sheet 8

of

8

5,260,905


93/179


94/179

. 5,260.905

3

the memory itself docs not provide

a

function which

enables the continuous writing of data such 8 5 the dy-

namic image

A

considerably complicated circuit has to

be

nstalled outside the memory in order

to

display the

dynamic

images

by the conventional image display

apparatus.

SUMMARY

OF

THEINVENTION

An

object of the prcsent invention is therefore to

provide

a

multi-port memory capable of transferring

data to 8 m em or y m a y so LE to display

a

dynamic pic-

ture image or the like at an arbitrary position with the

desired size

on

the screen in

a

simple circ uit structure.

In order to achieve the aforementioned objec tive, in

a first embodiment

of

the present invention, a xm ico n-

ductor memory is provided having a memory array

with a random access function, a firstwrial access mem-

ory with at least one serial output function, a second

serial access memory with at least one

xrial

input func-

4

take in the data,

a

serial address counter which counts

the cl ock cycle s after laking an address signal from the

address signal input means and generates a serial ad-

dress moving sequentially from the bit position where

5 the first and second registers start to take in the input

data to a bit position of more significance, B serial bit

selector which selects the bit position indicated by the

scdal address, a transfer gate to transfer the content of

the fmt register to

a

m em ory m y . and control means

' 0 for controlling per every bit

a

transfer control signal

input to the transfer gate in acco rdance with

an

output

of

the sccond register.

Th e semiconductor memory embodied by the prcsmt

invention in the abo vedescrib ed structure can transfer

the data for displayinga window of the dynamic picture

image or the like at a desired position on the screen t o a

memory array in acco rdance with t he input data from a

access memory to the memory array per every bit in BRIEF DES CRIFTION OF T HE DRAWINGS

accordance with an output of the memory means.

According to a second embodiment of the present

invention. a semiconductor memory includes a first

register which takes input data serially in synchroniza-

tion with clocks, input means for inputting transfer

mask data to con trol the transfer

of

serial data. a selec-

tor which selects either the data from the transfer mask

input means or the transfer mask data generated inside

the memory, a second register which takes output sig-

nals

of

the selector, and control means

for

controlling

per very bit a transfer gate to transfer the serial data in

accordance with an output of the sccond register are

aravided.

These and other objects and features of the present

invention will become clear from the following descrip-

tion taken in conjunction with the preferred embodi-

ment thereof with reference to the accomp anying draw-

ings throughout which like parts are designated by like

reference numerals, and in which:

FIG. 1 isa structural diagram of multi-port memory

according

lo

one preferred embodiment

of

the present

invention:

FIG.

2 is

a

circuit diagram of a transfer gate,

a

data

register, a data selec tor and a mask tegister in the multi-

port m em ory of F I G .

1;

r

-

- - -

According to

a

third embodiment of the prwnt in-

vention

a

semiconductor memory includes a a serial

data input means,

a

first register which takes input data

from the serial d ata input means in synchronization w ith

b

of he transfer of da w

clocks, transfer mask data input means for inputting

transfer mask data to control the transfer of serial data,

a second register which takes data from the transfer

mask data input means synchronously when the first

register takes the input data from the serial data input 45

means, address signal input means fo r indicating

a

bit at

the starting position where th e first and second registers

stan to take in the data.

a

serial address counter which

counts the clock cycles after taking an address signal

F I G .

3

is a diagram

of

an example

of

the transfer of

FIG. 4 is

a

diagram explanatory of another example

FIG.

5 is

a timing chart o f the memory of F I G . 1

when serial data is input and transferred;

FIG.

6

a StNCtUral diagram of

a

conventio nal dual-

port memory;

FIG.

7

is a timing chart

of

th e m emory of F I G . 6

when the serial data i5 transferred and output; and

FIG.

8

is

8

block diagram showing an image dirplay-

h g System

10

which a multi-port memory according to

the present invention isapplied.

data;

from the address signal input means and generatis a 5 0

xr ia l address sequentially moving from the bit position

where the

fmt

and second registers start to rake in the

DETAILED

OF

THE

P REFERRED EMBODIMENT

input data to a bit position

of

more significance, a serial The pr m nt invention provides a semiconductor

bit selector which selects the bit position indicated by memo ry dev ice which includes

a

serial

port

for storing

the serial address,

t

transfer gate lo transfer the content 55 the

Serial

data such as dynamic picture image or the like,

of the first register to a memory may. and control

a

dual-port memory which has

a

random

port for

writ-

means for controlling

per

every bit

a

transfer control

ing

and reading

IO

n arbitrary position of

a

memory

signal input to the transfer gate in accordance with m array and a serial port

for

outputting display data to

CRT.

utput

of

the second register.

FIG. 8 shows a system having a color monitor 57

invention,

a

semiconductor memory includes

a

there connected to a color map

56

via a line 59 to which a

serial data input means, a first register which takes input multi-pori memo ry 51 according to the pr mn t inven-

data from the serial data input means in synchronization tion is applied.

with clocks, a second register which t ak a transfer mask In this system, the color map 56

is

connected, via a

data synchronously when the first register takes the 65 video data bus 6 6 , o the multi-port memory 51 and the

input data from the serial data input means, address col or map 56 and the multi.pon memory 51 are con.

signal input means

for

indicating

a

bit Pt the starting trolled by a serial port control circuit 55 through lines

position where the first and second registers start to 66 and

67.

The multi-pori memory 51

is

connected to an

According to

a

founh embodiment Of the prcsent 6 0


95/179

5,260,905

6

imaging hard-ware 53 via

data bus 62 and an address data register 11 and mask register 13

in

accordance with

bus

63.

an output of the serial address counter

14.

Both the multi-pon memory 51 and imaging hard- The second

serial

address counter

14

functions in the

ware 53 are controlled by the random port control same manner as the first serial address counter

8.

T h e

circuit

5 4

via lies

64

and

65,

respectively. The imaging

5 second serial data register 11 takes in the data from a

hard-ward

53

is connected, via a line

61,

to an interface serial data input terminal

25

to a bit position indicated

52 which

is

connected t o a standard bus 60. he multi- by an output

of

the

serial

bit selector 12, and the mask

pon

memory 51 is connected to

a

serial data writing register 13 t a k a i n

an

output of the selector 1S to a bit

circuit

70

v a serial data line

71

and serial mask line 72. position indicated by the output

of

the serial bit selector

The multi-port memory 51 stores images to be dis-

lo

12. Th e serial bit selector

12,

similar to the d ata selector

played on the colo r monitor 56. The information stored 3. indicates an arbitrary bit position for the second serial

in the multi-port memory 51 is transmitted, via a video data register

11 in

accordance with an output of the

data bus

68,

to the

color

map

56

sequentially and dis- second serial address coun ter

14

and indicates

also

the

played by the color monitor 56. Th e serial port cont rol same bit position for the mask register 13

as

the second

circuit 55 controls the transfer of the information stored

15

serial data register 11.

A

selector 15 is a circuit

to

switch

in the multi-pon memory 51. T o alter the information the mask data to be input to the mask register 13 be-

stored

in

the multi-pon memory 51 through the imaging tween the data input through a mask data input terminal

hard-ware 5 5 in order to change the image to be dis- 27 and the data fixed to logic

1

in accordan ce with a

played on the color monitor 57, the standard bus 60

signal from a mask selection signal input terminal

2 8

transmits suitable com mands to the imaging hard-ware

20

Terminals of nput/output signals and a control signal

53 via the interface 52. Th e random port control circuit

to

realize input/output means of signal

certain semiconductor memory devices and products containing same, 337-470, no. 65959-1 (u.s.i.t.c....

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