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Design Guide

SiRF Proprietary and Confidential

SiRFatlasV Hardware Design Guide

January 2010 Document Number: CS-129512-UG Issue 3

INTRODUCTION

This document serves as a hardware design guide for the SiRFatlasV™ SoC based Evaluation Board (EVB) including boot configuration, power supply, and peripheral interfaces such as RAM, ROM, USB and more. For details about the schematics, contact SiRF field application engineers (FAE).

SiRFatlasV

Hardware Design Guide

January, 2010 SiRF Design Guide – Proprietary and Confidential i

Table of Contents

Introduction .......................................................................................................................... i

SiRFatlasV Feature List ..................................................................................................... 1

Computing Cores ............................................................................................................. 1 Memory Subsystem .......................................................................................................... 1 Advanced Autonomous GPS .............................................................................................. 1 Display, Graphics, and Multimedia ...................................................................................... 1 Peripherals and Interfaces ................................................................................................. 1

Power Integration.................................................................................................... 1 Audio Integration .................................................................................................... 1 NAND Flash Storage ............................................................................................... 2 SD/MMC/MMC+ Controller ....................................................................................... 2 USB Connectivity .................................................................................................... 2 Packaging.............................................................................................................. 2

Temperature Range.......................................................................................................... 2

SiRFatlasV System Block Diagram .................................................................................. 3

Boot Configuration ............................................................................................................. 4

Power Supply ...................................................................................................................... 5

Power Pins ...................................................................................................................... 5 Decoupling CAP and Placement on the PCB Board ............................................................... 6 Power Consumption ......................................................................................................... 6 Power-On Sequence......................................................................................................... 6

On-Chip PMU ....................................................................................................................... 6

Modac ................................................................................................................................... 7

UART..................................................................................................................................... 7

I2C….. .................................................................................................................................... 7

USP….................................................................................................................................... 8

NAND .................................................................................................................................... 8

DRAM .................................................................................................................................... 8

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January, 2010 SiRF Design Guide – Proprietary and Confidential ii

USB… ................................................................................................................................... 8

PCB Layout ..................................................................................................................... 8

TSC/ADC .............................................................................................................................. 9

Add ESD devices to the Touch Screen Interface (TSI) for ESD protection. ................................ 9 PCB Layout ..................................................................................................................... 9

SD/MMC .............................................................................................................................. 10

PCB Layout ....................................................................................................................11

LCD….................................................................................................................................. 11

PCB Layout ....................................................................................................................11

Crystal ................................................................................................................................ 11

PCB Layout ....................................................................................................................12

GPIO.................................................................................................................................... 12

Reset Button Connection ................................................................................................ 12

Avoid I/O Leakage During SoC Power-Off .................................................................... 14

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January, 2010 SiRF Design Guide – Proprietary and Confidential iii

List of Tables

Table 1: Mode Configuration Pins................................................................................................. 5 Table 2: Power Pins ................................................................................................................... 6 Table 3: On-Chip PMU Specifications and Applications.................................................................... 7 Table 4: Reset Behavior.............................................................................................................13 Table 5: Reset Behavior when Working as a Reset Button ..............................................................14

List of Figures

Figure 1: SiRFatlasV System Block Diagram .................................................................................. 3 Figure 2: USB DP/DN Route........................................................................................................ 8 Figure 3: USB Layout Rule .......................................................................................................... 9 Figure 4: ADC Power Supply and Reference Decoupling ................................................................10 Figure 5: SD0 Power Circuit .......................................................................................................11 Figure 6: 24MHz Crystal Circuit...................................................................................................11 Figure 7: 32.768KHz Crystal Circuit .............................................................................................12 Figure 8: P-MOS and N-MOS in I/O Pad.......................................................................................14 Figure 9: Random RTC Reset or On Key 15s Issue........................................................................15 Figure 10: Workaround for Random RTC Reset or On Key 15s Issue ...............................................16

SiRFatlasV


January, 2010 SiRF Design Guide – Proprietary and Confidential 1

SiRFatlasV FEATURE LIST

Computing Cores

500 MHz ARM11 with 16KB D-cache and I-cache, 16KB D-TCM and I-TCM

250 MHz Enhanced DSP for GPS

Low Power advanced 65nm process

Memory Subsystem

64-bit 250MHz system bus with 16 DMA channels

1.8V 16-bit Mobile-DDR support

1.8V 16-bit DDR2 support

Advanced Autonomous GPS

64 channels

-161 dBm sensitivity

SiRF Always-Fix technology

Able to acquire and track Galileo signals on all channels

Display, Graphics, and Multimedia

Capable of supporting up to 800x480 at 16 bits color

Support RGB565 or 16bit CPU I/F TFT LCD panel

Hardware VPP (Video post processor) for de-interlace, scalar, color space conversion

Two hardware overlay layers

Peripherals and Interfaces

Power Integration

Two switching DC/DC for core (700mA) and DRAM (500mA)

One high PSRR and low noise 150mA LDO for I/O and peripheral

One high PSRR and low noise 100mA LDO for analog power

One high PSRR and low noise 10mA LDO for PLL

One high PSRR and low noise 50mA LDO for RF

Audio Integration

One mono differential audio output with 93db SNR and 70db THD (“A” weighted)

One stereo audio output with 93db SNR and 70db THD (“A” weighted) Connectivity

One dedicated AC97/I2S interface

Two dedicated UART ports

Two USP ports for PCM, DSP, I2S, SPI, UART mode

Two I2C ports

12-bit ADC with 4-wire touch screen controller and 3 channel analog input, stream measurement mode for low cost audio input

SiRFatlasV



NAND Flash Storage

8-bit NAND Flash interface with 12/24bit configurable BCH HW ECC support

Supports direct boot from SLC or MLC NAND

Support SLC 512B, 2KB, 4KB page size

Support MLC 2KB, 4KB, 8KB page size

SD/MMC/MMC+ Controller

SDIO support for WiFi, DVB-T/DVB-H/T--DMB/S-DMB

Supports direct boot from SD/MMC+ Managed NAND

Two 8-bit SD1.01/SD 2.1/MMC4.3 ports

Two 4-bit SD1.01/SD2.1/MMC4.3 ports

USB Connectivity

One USB 2.0 High Speed interfaces with on chip PHY

Can be Host, Device or OTG

Transfer up to 480Mbps

Packaging

10mm x 13mm 285 ball TFBGA with 0.65mm pitch

Temperature Range

-20°C ~ +70°C extended commercial grade

SiRFatlasV



SiRFatlasV SYSTEM BLOCK DIAGRAM

Figure 1: SiRFatlasV System Block Diagram

SiRFatlasV



BOOT CONFIGURATION

SiRFatlasV supports many types of boot media including NAND Flash and SD cards. The boot mode can be set through the mode configuration pins according to the table below.

NOTE – Set the pins with pull-up or pull-down resistors (10 kOhm to 100 kOhm), do not leave these pins set to float.

Working Mode

X_TEST_MODE[5:4]

Sub-Mode

X_TEST_MODE[3:2]

Feature 1

X_TEST_MODE[1]

Feature 0

X_TEST_MODE[0]

2'B00: Normal 2'B01: Normal With ARM JTAG 2'B10: Function ATE

2'B00: Embedded ROM NAND Boot (SLC)

1'b0: SLC 1'b0: 2KB page

1'b1: 4KB page

1'b1: LBA-Nand 1'bx: 2KB page

2'B01: NAND Boot(SLC) 1'bx: Don't Care 1'b0: 512B page

1'b1: 2KB page

2'B10: Embedded ROM NAND Boot (MLC)

1'b0: ECC 12bit per 1KB

1'b0: 2KB page

1'b1: 4KB page

1'b1: ECC 24bit per 1KB

1'b0: 4KB page

1'b1: 8KB page

2'B11: Embedded ROM SD/MMC Boot

- -

2'B11: TEST MODE

2'B00: Scan Mode

2’b00: INTEST_AC_DC

2’b01: EXTEST_AC_DC

2’b10: Reserved

2’b11: Reserved

2'B01: Reserved - -

2'B10: CHIP TEST1

1’b0: Boundary Scan

1’b0: NANDTree

1’b1: BSD

1’b1: Macro Test0

1’b0: BIST

1’b1: Efuse (x_reset_b = 1'b0)

2'B11: CHIP TEST2 1’b0: Macro Test1

1’b0: USB PHY Stand Alone TEST

1’b1: TSC/PLL TEST

SiRFatlasV



Working Mode

X_TEST_MODE[5:4]

Sub-Mode

X_TEST_MODE[3:2]

Feature 1

X_TEST_MODE[1]

Feature 0

X_TEST_MODE[0]

1’b1: Macro Test2

1’b0: MEM PHY TEST

1’b1: Reserved

Table 1: Mode Configuration Pins

The following lists the configuration rules for different boot modes:

For SD/MMC boot mode, use the SD0 port.

For SLC NAND Flash/MLC and SD boot media, use UART1 to download the Nboot image. This means that UART1 must be used as the debug port for the MLC/SD boot mode.

POWER SUPPLY

Power Pins

Pin Name Typical Voltage (V) Description

VDDIO_L 3.3/3.0/2.8/1.8 LCD related I/O pads power

VDDIO_N 3.3/3.0/2.8/1.8 NAND flash related I/O pads power

VDDIO 3.3/3.0/2.8 I/O pads power

VDDIO_MEM 1.8/2.5 The pad power of the memory interface

VDD_CORE 1.2 Main core digital power

GND - Main digital GND

VDDIO_RTC 3.3 RTC pad power

VDD_RTC - Internal LDO output, connect to bypass cap

VDD_PLL0/1 1.2 PLL pad power

VSS_PLL0/1 - PLL GND

VDDIO_OSC 3.3 OSC Pad power

VSSIO_OSC - OSC PAD GND

VDD_USB 1.2 USB core digital power

VDDA_USB 3.3 USB analog power

VSSA_USB - USB GND

VDD_TSC 1.2 TSC core digital power

VSS_TSC - TSC core GND

SiRFatlasV



Pin Name Typical Voltage (V) Description

VDDA_TSC 3.3 TSC analog power

VSSA_TSC - TSC GND

VDDIO_DAC 3.3 MoDAC PAD power

VSSIO_DAC - MoDAC PAD GND

Table 2: Power Pins

Decoupling CAP and Placement on the PCB Board

For VDD_CORE (1.2V), six 1uF/0402/MLCC need to be placed under the CPU.

Six 220nF/0402/MLCC for VDDIO_MEM

Three 220nF/0402/MLCC for VDDIO

One 220nF/0402/MLCC for VDDIO_N

One 220nF/0402/MLCC for VDDIO_L

One 220nF/0402/MLCC for VDDIO_DAC

For more details on the placement, contact SiRF field application engineers for the sample PCB layout.

Power Consumption

For power and current budget, refer to: CS-130805-DS SiRFatlasV Datasheet.

Power-On Sequence

The SiRFatlasV system power on sequence should follow the sequence in the CS-130805-DS SiRFatlasV Datasheet.

The power on reset has two important valid reset time values:

RTC power on reset: X_RTC_RST_B should keep the logic low after the 32KHz crystal is stable

SOC logic hardware reset: X_RESET_B should keep the logic low after the 24MHz crystal is stable

Refer to the SiRFatlasV Datasheet to view the power on reset time’s requirement.

ON-CHIP PMU

The on-chip power management unit (PMU) covers two DCDC converters (dcdc1, dcdc2), and four to five LDOs.

NOTE – There are two versions of the PMU for SiRFatlasV: the first version has four LDOs (LDO1~4), and the second version has five LDOs.

SiRFatlasV



Spec and Configuration Application

DCDC1 1.8v/2.5v, 500mA Memory power supply

DCDC2 1.2v, 700mA CPU core power supply

USB core

TSC core power supply

LDO1 3.3V, 100mA TSC

ADC

USB analog power

LDO2 3.3V, 150mA

VDDIO

VDDIO_N

VDDIO_L

VDDIO_DAC

VDDIO_OSC

LDO3 1.2V, 10mA PLL pad power supply

LDO4 3.3v,50mA GPS power supply

LDO5 3.3V VDDIO_RTC

Table 3: On-Chip PMU Specifications and Applications

MODAC

Refer to CS-130255-UG SiRFatlasV Audio Hardware Design Guide for the Modac design.

UART

There are two UARTs on the SiRFatlasV chip, but only UART0 has the DMA function. Use UART0 to transmit large amounts of data at high speed.

UART0 has a hardware flow control function.

UART1 must be used as the debug port.

I2C

Add pull-up resistors to all I2C pins.

If there are many I2C devices on one bus, do not release the bus without powering on some of the devices, otherwise the bus will hang. In this scenario, use GPIO to simulate the I2C bus.

SiRFatlasV



USP

All USP ports can support the DMA function which allows users to transmit large amounts of data at high speed.

USP ports can simulate UART functions but do not support odd/even parity.

USP ports can simulate PCM or I2S (DSP mode), in this case X_TFS_0,1 itself can be used as a frame sync pin.

NAND

Add a pull-up resistor on the pin X_DF_WP_B since it is open drain.

DRAM

Refer to CS-129773-UG SiRFatlasV DDR2/mDDR Hardware Design Guide.

USB

Pay attention to the following when designing the USB module:

Add ESD devices to the DP/DN and ID pins.

Add an 820-Ohm resistor in series with the pin x_usb_vbus to prevent overvoltage.

PCB Layout

The USB 2.0 specification requires that the USB DP/DN traces maintain a 90 Ohm differential impedance (see paragraph 7.1.1.3 in USB specification Rev 2.0 for more details). A continuous ground plane is required directly beneath the DP/DN traces and extending at least 5 times the spacing width to either side of the DP/DN lines. Maintain the differential impedance close to 90 Ohm.

For different dielectric thicknesses, copper weight or board stack-ups, the trace width and spacing will need to be recalculated. Keep the DP and DM lines symmetrical both in shape and length. Single-ended impedance is not as critical as the differential impedance, a range of 42 Ohm to 78 Ohm is acceptable (while the common mode impedance must be within the range of 21 Ohm to 39 Ohm).

Figure 2: USB DP/DN Route

SiRFatlasV



In order to minimize crosstalk, make sure that signal traces are routed close to the two USB differential signals. The minimum recommended spacing is 3xa for low-speed non-periodic signals, and 7xa for high-speed periodic signals. A continuous ground plane below the DP/DN lines is required.

Figure 3: USB Layout Rule

TSC/ADC

Add ESD devices to the Touch Screen Interface (TSI) for ESD protection.

PCB Layout

Due to the analog nature of this block, routing should be done carefully and according to the following rules:

Keep all analog net routing as small as possible.

Shield all critical analog nets using the Analog Ground (AGND), especially single-ended nets. Pay attention to the routing of the input lines. Any noise coupling will be treated as an input signal, thereby reducing the dynamic range of the ADC.

Keep all analog, reference and power supply lines as wide as possible. Respect the maximum wire resistance values mentioned in the Routing Constraints section when there is a need to increase the line width or to use several metal layers.

Use as many vias as possible when changing between metal layers.

Power supply decoupling should follow the figure below. The capacitors should be good quality ceramic and that they must be placed as close to the chip as possible.

SiRFatlasV



Figure 4: ADC Power Supply and Reference Decoupling

SD/MMC

Add an external pull-up resistor to all data and command signals when using an SD/MMC card or an iNAND/moviNAND card. Use SD0 but not SD2 as the boot media.

For MMC/ moviNAND, the pull-up resistor should be:

50 kOhm ~ 100 kOhm for the DATA net

4.7 kOhm ~ 100 kOhm for the CMD net

For SD/iNAND, the pull-up resistors to all data and command signals should be 10 kOhm ~ 100 kOhm.

Add a quick discharging circuit by pulling the SD0's power low to GND with a 1 kOhm resistor when SD0 is in power-down state (see R307 to Q303 in Figure 5.) The reason for doing this is:

The iNAND may not reboot normally if it did not discharge after power-off.

SiRFatlasV



Figure 5: SD0 Power Circuit

NOTE – An alternative way for quick discharging is to use an IC (such as AAT4280IGU-3-T1) instead of the circuit shown above.

PCB Layout

Route all signals with equal length.

LCD

Add an EMI filter to all nets.

PCB Layout

All nets should be routed as equal length.

CRYSTAL

The following figures are recommended circuits for the external crystal clock input.

Figure 6: 24MHz Crystal Circuit

SiRFatlasV



Figure 7: 32.768KHz Crystal Circuit

Crystal part number:

24 MHz, E3SB24.0000F16D23, HOSONIC.

32.768 KHz, 12.5pF, FC-135, EPSON.

PCB Layout

The crystal oscillator is sensitive to stray capacitance and noise from other signals. It can also interfere with other signals and cause EMI noise. Therefore the load capacitors, crystal and parallel resistors should be placed close to each other. The ground under the circuit should remain intact.

GPIO

If a pin is set to GPIO, then GPIO type and settings should be checked. The following settings should be avoided:

If a GPIO is set as output, then ensure that the output value does not conflict with peripherals during running mode for better power consumption management.

RESET BUTTON CONNECTION

SiRFatlasV has several reset function pins:

X_RTC_RST_B

This is a reset signal used to reset all RTC domain logic and power on/off control logic. After the VDDIO_RTC first powers on, X_RTC_RST_B should be active to guarantee that the RTC logic is reset and the power on/off control logic enters the RTC_COLDBOOT state. When the system is running, any time X_RTC_RST_B is active, the RTC logic is reset, causing X_system_en and X_dram_en to output low, and all SoC power except the RTC power will shutdown.

X_RESET_B

This is a hardware logic reset that resets all SoC logic except the RTC domain logic and power on/off control logic. After the IO power is supplied, X_RESET_B should be active to guarantee the SoC logic is reset. While the system is running, any time X_RESET_B is active, all SoC logic except the RTC logic and power on/off control logic will be reset

SiRFatlasV



Warm_RST_B(X_GPIO[8])

This pins default is GPIO<8> and is configured by the software as a warm reset, when input is low, SoC logic will finish all warm reset procedures, DRAM will be set in self-refresh, and most of the SoC logic will be reset except the RTC logic and power on/off control logic.

On_Key 15 second reset

When a user presses the On_key continuously for up to 15 seconds, the SoC will reset similar to X-RTC_RST_B

The following table describes the behavior of various types of reset.

Module X_RTC_RST_B On_Key 15s X_RESET_B Warm-reset

Power on/off control logic Yes Yes No No

GPSRTC Power-off Power-off Yes No

SYSRTC Yes Yes No No

RISC Core Power-off Power-off Yes Yes

RISC Interface Power-off Power-off Yes Yes

Interrupt Controller Power-off Power-off Yes Yes

CLKC Power-off Power-off Yes Yes

Timer Power-off Power-off Yes Yes

Reset controller Power-off Power-off Yes No

GPIO Power-off Power-off Yes Yes

System Arbiter Power-off Power-off Yes Yes

RISC CP14 Registers Power-off Power-off Yes No

Other SoC logic blocks Power-off Power-off Yes Yes

Table 4: Reset Behavior

NOTE – “Power-off” means the SoC logic will be powered off through x_system_en and x_dram_en as “low”; “Yes” means the SoC power is supplied, the logic module is reset.

For details about the resets, refer to CS-130805-DS SiRFatlasV Datasheet.

If the GPS device has a reset button, it is recommended to use warm-reset or X_REST_B to connect to this reset button. The following table shows the behavior when these four types of reset work as the reset button.

SiRFatlasV



Behavior X_RTC_RST_B

On_Key 15s X_RESET_B Warm-Reset

Power off logic through x_system_en

and x_dram_en Yes Yes No No

RTC time loss Yes Yes No No

SoC logic is reset when system running Power-off Power-off Yes Yes

SoC logic is reset when system is in deep-sleep or hibernation

Power-off Power-off No No

Reboot when system is running No (press On_key again)

No (press On_key again)

Yes Yes

Reboot when the system is in deep-sleep or hibernation



No No

Table 5: Reset Behavior when Working as a Reset Button

AVOID I/O LEAKAGE DURING SOC POWER-OFF

The SiRFatlasV SoC has an ESD protection circuit between the I/O pad’s power and the I/O pad, when the I/O pad is not powered there is an external source to drive this pad “high” or “toggle”, therefore there may be leakage from the external source to the I/O power, and this may result in system instability.

Figure 8: P-MOS and N-MOS in I/O Pad

SiRFatlasV



This issue happens during the four typical cases of I/O power loss:

When the system enters deep-sleep or hibernation mode

Before the SoC goes into deep-sleep mode or hibernation mode, the software needs to shutdown peripherals’ power to avoid the peripherals driving the SoC I/O pads and thus resulting in I/O leakage when the I/O power is disabled.

When the system is running, the user randomly presses the On-Key for 15s or X_RTC_RST_B

These two reset issues happen randomly by end users but are not controlled by software. It may result in serious system instability. For example:

Figure 9: Random RTC Reset or On Key 15s Issue

When the system is running and the random RTC reset or On Key 15s issue happens, x_system_en and x_dram_en will output low to disable most of the LDO and buck inside the PMU. However because the software has no time to control the GPIO to disable the RF LDO, the RF LDO will keep working and the RF chip will still be powered on. Thus the RF chip keeps driving signals to to the SoC’s I/O pad through the GPS BB signal pads and the pad’s internal ESD circuit, leakage will go to the I/O VDD. Although the I/O LDO is disabled, this leakage causes the I/O VDD to have a 1.xV~2.xV floating voltage, therefore the RF LDO’s enable signal and LCD backlight boost ’s enable signal will also have a 1.xV~2.xV level signal. The voltage may be above the RF LDO and LCD boost enable signal threshold, so these two regulators keep working.

The I/O leakage due to the RF LDO issue is a dead-loop. The LCD backlight boost will result in a white-screen and an uncomfortable user experience. Especially, when the system goes into this dead-loop status, the end user can only remove the battery to recover the system.

To solve this problem, reset the SoC logic before the SoC’s I/O and core power loss. Assume that on the hardware design, the default status of the peripheral’s enable signals such as RF power enable and LCD backlight enable, after system power-on and reset is “disabled”, when the random RTC reset or On key 15s issue happens, x_system_en or x_dram_en goes to low to disable most of the SoC regulators. If, before the SoC I/O and core power are fully discharged, there is a way to pull X_RESET_B to low rapidly,

SiRFatlasV



then the peripheral enable control signals will be reset to “disabled” before the I/O and Core power are discharged, then the I/O leakage dead-loop will be destroyed, and the system will become stable.

The following is a work around circuit to solve this problem.

Figure 10: Workaround for Random RTC Reset or On Key 15s Issue

When a random RTC reset or On key issue happens, x_system_en is pulled low, so x_reset_b will also be pulled low quickly via the diode between x_reset_b and x_system_en. Before the Core and I/O power are really discharged the SoC logic is reset and the I/Os which control the enabled peripherals will go to the default reset status. The hardware design should guarantee these control signals are set to “disable” at the default reset stage, check the SiRFatlasV Datasheet pin list to find every I/O pad’s reset status, then based on the peripheral’s enable/disable level, add external pull-up or pull-down resisters to make sure all these enable signals are in “disable” status at the default reset stage

NOTE – RC delay of X_RESET_B is about 20ms and RC delay of X_RTC_RST_B is about 880ms.

System is in deep-sleep or hibernation mode, with peripheral power on and drive signal to SoC

When the system goes into deep-sleep or hibernation mode, x_system_en is pulled low, and most of the SoC’s power is disabled. However there is still a chance that some external modules are powered on and can drive the output signals high or toggle to the SoC pads. For example, the debug module or external TMC or Radar module uses an external adaptor for power and has a UART connection between the GPS device and the module. In these cases, there may be I/O leakage from the powered module to the power-off SoC’s I/O VDD. This leakage may result in potential system instability.

To solve the problem:

– Use the above work around method to ensure that the peripherals are disabled before the SoC I/O and core power are discharged.

X_SYSTEM_ENDischarge if power off

D103

MA2S728

12R139

51K 1%

C127

2.2uF

X_SYSTEM_EN

C101

1uF/10V

X_RESET_BX_RESET_B X_RTC_RST_B

R140

510K 1%

12

VDDIO_RTC

R166 NC

C158

100nF

C159

100nF

D101

MA2S728

12

S101

12

VDDIO_RTC

Warm RESET

R16010K

D102

MA2S728

12

X_ON_KEY_B

VDDIO_RTC

S102

12

X_RTC_RST_B

X_GPIO8

R165 0R

RTC RESET

SiRFatlasV



– Insert a switch on the signal path between the powered external module and the SoC I/O pads. Use the SoC’s I/O to control the switch or control the external module’s power supply to make sure that when system goes into deep-sleep or hibernation mode, the external module is powered off at same time

January, 2010 SiRF Design Guide – Proprietary and Confidential Part number: CS-129512-UGP3

© 2010 SiRF Technology, Inc., a member of the CSR plc group of companies

This document contains proprietary information to SiRF Technology, Inc. and shall not be reproduced or transferred to other

documents or disclosed to others or used for any purpose other than that for which it was obtained without expressed written consent of SiRF Technology, Inc.

All other products or company names mentioned herein are used for identification purposes only, and may be trademarks of

registered trademarks of their respecti ve owners.

SiRF Technology, Inc. reserves the right to make changes in its products, specifications and other information at any time wi thout notice. SiRF assumes no liability or responsibility for any claims or damages arising out of the use of this document, or from the use

of integrated circuits based on this document, including, but not limited to claims or damages based on infringement of paten ts, copyrights or other intellectual property rights. SiRF makes no warranties, either express or implied with respect to the information

and specifications contained in this document. Performance characteristics listed in this data sheet do not constitute a warranty or guarantee of product performance. All terms and conditions of sale are governed by the SiRF Te rms and Conditions of Sale, a copy

of which you may obtain from your authorized SiRF sales representative.

No statements or representations in this document are to be construed as advertising, marketing, or offering for sale in the United States imported covered products subject to the Cease and Desist Order issued by the U.S. International Trade Commission in its

Investigation No. 337-TA-602. Such products include SiRFstarIII chips that operate with SiRF software that supports SiRFInstantFix, and/or SiRFLoc servers, or contains SyncFreeNav functionality.

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