cd-610 service manual
TRANSCRIPT
SERVICEMANUAL
CD-610
moc.m-retni.wwwAEROK NI EDAM
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PLAYER
ELECTRICAL ADJUSTMENT PROCEDURE (FRONT PART)ELECTRICAL ADJUSTMENT PROCEDURE (FRONT PART)
1
MB95F108AHWMB95F108AHW8-bit Proprietary Microcontrollers
Electrical Adjustment ProcedureSpecificationsElectrical Parts ListTop and Bottom View of P.C.BoardWiring DiagramBlock DiagramSchematic DiagramExploded View of Cabinet & Chassis / Mechanical Parts list
1~424344~4546~4950~5152~5354~5960~61
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CONTENTSCONTENTS
DESCRIPTION
FEATURE
The MB95100AH series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,the microcontrollers contain a variety of peripheral functions.
64-pin plastic LQFP (FPT-64P-M03)
• F²MC-8FX CPU core Instruction set optimized for controllers
Multiplication and division instructions 16-bit arithmetic operations Bit test branch instruction Bit manipulation instructions etc.
• Clock Main clock Main PLL clock Subclock (for dual clock product) Sub PLL clock (for dual clock product)
• Timer 8/16-bit compound timer 2 channels 16-bit reload timer 8/16-bit PPG x2 channels 16-bit PPG x2 channels Timebase timer Watch prescaler (for dual clock product)
• LIN-UART Full duplex double buffer Clock asynchronous or clock synchronous serial transfer capable
• UART/SIO Clock asynchronous or clock synchronous serial transfer capable
• I²C* Built-in wake-up function
• External interrupt Interrupt by edge detection (rising, falling, or both edges can be selected) Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected
• Low-power consumption (standby) mode Stop mode Sleep mode Watch mode (for dual clock product) Timebase timer mode
• I/O port: Max 54 General-purpose I/O ports (Nch open drain) : 6 ports General-purpose I/O ports (CMOS) : 48 ports
TEST
2 3
PIN ASSIGNMENT PIN DESCRIPTION
(Continued)
Pin no.Pin name Circuit
type DescriptionFPT-64P-M03FPT-64P-M09
1 AVcc - A/D power supply pin
2 AVR - A/D reference input pin
3 PE3/INT13
PGeneral-purpose I/O port. The pins are shared with the external interrupt input.
4 PE2/INT12
5 PE1/INT11
6 PE0/INT10
7 P83
O General-purpose I/O port8 P82
9 P81
10 P80
11 P71/TI0H
General-purpose I/O port.The pin is shared with 16-bit reload timer ch0 output.
12 P70/TO0General-purpose I/O port.The pin is shared with 16-bit reload timer ch0 input.
13 MOD B An operating mode designation pin
14 X0A Subclock oscillation pin
15 X1
16 Vss - Power supply pin (GND)
17 Vcc - Power supply pin
18 C H Capacitor connection pin
19 PG2/X1AH/A
Single clock product is general-purpose port. Dual clock product is main clock oscillation pin (32 kHz). 20 PG1/X0A
21 RST B’ Reset pin
22 P00/INT00
CGeneral-purpose I/O port.The pins are shared with external interrupt input. Large current port.
23 P01/INT01
24 P02/INT02
25 P03/INT03
26 P04/INT04
27 P05/INT05
28 P06/INT06
29 P07/INT07
30 P10/UI0 GGeneral-purpose I/O port.The pin is shared with UART/SIO ch0 data input.
(FPT-64P-M03, FPT-64P-M09)
ssV
A0
NA/03
P0 0
NA /13
P1 0
NA /23
P2 0
NA/ 33
P3 0
NA/43
P4 0
NA /53
P5 0
NA /63
P6 0
NA /73
P7 0
NA/04
P8 0
NA/14
P9 1
NA /24
P0 1
NA /34
P1
NIS/76
PT
OS /66
PK
CS/56
P
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc 1 48 P64/EC1AVR 2 47 P63/TO11
P E3/INT13 3 46 P62/TO10P E2/INT12 4 45 P61/PPG11P E1/INT11 5 44 P60/PPG10P E0/INT10 6 43 P53/TRG1
P83 7 42 P52/PPG1P82 8 41 P51/SDA0P81 9 40 P50/SCL0P80 10 39 P24/EC0
P71/TI0 11 38 P23/TO01P70/TO0 12 37 P22/TO00
MOD 13 36 P21/PPG01X0 14 35 P20/PPG00X1 15 34 P14/PPG0
Vss 16 33 P13/TRG0/ADT G
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ccV
C *A1
X/2G
P*
A0X/ 1
GP
TS
RP
00T
NI/00P
10T
NI/10P
20T
NI/20P
30T
NI/30P
40T
NI/40P
50T
NI/50P
6 0T
NI/ 60P
7 0T
NI/ 700I
U/ 01P
0O
U /11P
P0
KC
U/ 21
64
TOP VIEW
* Single clock product is general-purpose port, and dual clock product is subclock oscillation pin.
TEST
4 5
Pin no.Pin name Circuit
type DescriptionFPT-64P-M03FPT-64P-M09
31 P11/UO0
H
General-purpose I/O port.The pin is shared with UART/SIO ch0 data output.
32 P12/UCK0General-purpose I/O port.The pin is shared with UART/SIO ch0 clock I/O.
33P13/TRG0/
ADTG
General-purpose I/O port.The pin is shared with 16-bit PP G ch0 trigger input (TRG0) and A/D trigger input (ADTG).
34 P14/PPG0General-purpose I/O port.The pin is shared with 16-bit PPG ch0 output.
35 P20/PPG00
H
General-purpose I/O port.The pins are shared with 8/16-bit PPG ch0 output. 36 P21/PPG01
37 P22/TO00 General-purpose I/O port.The pins are shared with 8/16-bit compound timer ch0 output. 38 P23/TO01
39 P24/EC0General-purpose I/O port.The pin is shared with 8/16-bit compound timer ch0 clock input.
40 P50/SCL0I
General-purpose I/O port.The pin is shared with I 2C ch0 clock I/O.
41 P51/SDA0General-purpose I/O port.The pin is shared with I 2C ch0 data I/O.
42 P52/PPG1H
General-purpose I/O port.The pin is shared with 16-bit PPG ch1 output.
43 P53/TRG1General-purpose I/O port.The pin is shared with 16-bit PPG ch1 trigger input.
44 P60/PPG10
K
General-purpose I/O port.The pins are shared with 8/16-bit PPG ch1 output. 45 P61/PPG11
46 P62/TO10 General-purpose I/O port.The pins are shared with 8/16-bit compound timer ch1 output. 47 P63/TO11
48 P64/EC1General-purpose I/O port.The pin is shared with 8/16-bit compound timer ch1 clock input.
49 P65/SCKGeneral-purpose I/O port.The pin is shared with LIN-UART clock I/O.
50 P66/SOTGeneral-purpose I/O port.The pin is shared with LIN-UART data output.
51 P67/SIN LGeneral-purpose I/O port.The pin is shared with LIN-UART data input.
52 P43/AN11
JGeneral-purpose I/O port.The pins are shared with A/D analog input.
53 P42/AN10
54 P41/AN09
55 P40/AN08
Pin no.Pin name Circuit
type DescriptionFPT-64P-M03FPT-64P-M09
56 P37/AN07
JGeneral-purpose I/O port.The pins are shared with A/D analog input.
57 P36/AN06
58 P35/AN05
59 P34/AN04
60 P33/AN03
61 P32/AN02
62 P31/AN01
63 P30/AN00
64 AVss - A/D power supply pin (GND)
TEST
6 7
SP232ACTSP232ACTEnhanced RS-232 Line Drivers/Receivers
DESCRIPTION
FEATURE
The Sipex SP231A, SP232A and SP233A are enhanced versions of the Sipex SP231, SP232 and SP233 RS-232 line drivers/receivers. They are pin-for-pin replacements for these earlier versions and will operate in their sockets. Performance enhancements include 10V/us slew rate, 120k bits per second guaranteed transmission rate, and increased drive current for longer and more flexible cable configurations. Ease of use enhancements include smaller, 0.1uF charge pump capacitors, enhanced ESD protection, low power dissipation and overall ruggedized construction for commercial environments. The series is available in plastic and ceramic DIP and SOIC packages operating over the commercial, industrial and military temperature ranges.
The Sipex SP231A, SP232A and SP233A are enhanced versions of the Sipex SP231, SP232 and SP233 RS-232 line drivers/receivers. They are pin for-pin replacements for these earlier versions, will operate in their sockets with capacitors ranging from 0.1 to 100µF,either polarized ornon–polarized, and feature several improvements in both performance and ease of use. Performance enhancements include 10V/µs slew rate, 120k bits per second guaranteed transmission rate, and increased drive current for longer and more flexible cable configurations. Ease of use enhancements include smaller, 0.1µFchargepump capacitors, enhanced ESD protection, low power dissipation and overall ruggedized construction for commercial environments.
The SP232A, SP233A, SP310A and SP312A include charge pump voltage converters which allow them to operate from a single +5V supply. These converters convert the +5V input power to the 10V needed to generate the RS-232 output levels. Both meet all EIA RS-232D and CCITT V.28 specifications.The SP231A has provisions for external V+ supplies. With this power supplied externally, the current drain due to charge pump operation is considerably reduced, typically to 400µA.
The SP310A provides identical features as the SP232A. The SP310A has a single control line which simultaneously shuts down the internal DC/DC converter and puts all transmitter and receiver outputs into a high impedance state. The SP312A is identical to the SP310A with separate tri-state and shutdown control lines.
The SP231A is available in 14-pin plastic DIP, CERDIPand 16-pin SOICpackages for operation over commercial, industrial and military temperature ranges. The SP232A is available in 16-pin plastic DIP,SOIC and CERDIP packages, operating over the commercial, industrial and military temperature ranges. The SP233A is available in a 20-pin plastic DIP and 20–pin SOIC package for operation over the commercial and industrial temperature ranges. The SP310A and SP312A are available in 18-pin plastic, CERDIP and SOIC packages for operation over the commercial and industrial temperature ranges. Please consult the factory for DIP and surface-mount packaged parts supplied on tape-on-reel, as well as parts screened to MIL-M-38510.
PIN ASSIGNMENT
V GN
D
T O
UT
R IN
R O
UT
T IN
T IN
R O
UT
CC 1 2
C +
V+ C -
C +
C -
V- T O
UT
R IN1
1 1
A232PS
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1 2 2 2 2
1 2
TEST
8
ELECTRICAL ADJUSTMENT PROCEDURE (REAR PART)ELECTRICAL ADJUSTMENT PROCEDURE (REAR PART)
9
PCM1738EPCM1738E24-Bit, 192kHz Sampling,Advanced Segment, Audio-StereoDIGITAL-TO-ANALOG CONVERTER
DESCRIPTIONFEATURE
The PCM1738 is a CMOS, monolithic, IntegratedCircuit (IC) that includes stereo Digital-to-AnalogConverters (DACs) and support circuitry in a small SSOP-28 package. The data converters utilize a newly developed advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1738 provides balanced current outputs, allowing the user to optimize analog performance externally, and accepts industry standard audio data formats with 16- to 24-bit data, providing easy interfacing to audio DSPand decoder chips. Sampling rates up to 200kHz are supported.
The PCM1738 also has two optional modes of operation: an external digitalfilter mode (for use with the DF1704, DF1706, and PMD200), and a DSD decoder interface for SACD playback applications. A full set of user-programmablefunctions are accessible through a 4-wire serial controlport that supports register write and read functions.
24-BIT RESOLUTION ANALOG PERFORMANCE (VCC = +5V):
Dynamic Range: 117dB typ SNR: 117dB typ THD+N: 0.0004% typ Full-Scale Output: 2.2Vrms (at post amp) DIFFERENTIAL CURRENT OUTPUT: ı 2.48mA SAMPLING FREQUENCY: 10kHz to 200kHz SYSTEM CLOCK: 128, 192, 256, 384, 512,
or 768fS with Auto Detect ACCEPTS 16-, 20-, AND 24-BIT AUDIO DATA DATA FORMATS: Standard, I2S, and Left-
Justified 8x OVERSAMPLING DIGITAL FILTER:
Stopband Attenuation: –82dB Passband Ripple: ı 0.002dB OPTIONAL INTERFACE TO EXTERNAL
DIGITAL FILTER AVAILABLE OPTIONAL INTERFACE TO DSD DECODER
FOR SACD PLAYBACK USER-PROGRAMMABLE MODE CONTROLS:
Digital Attenuation: 0dB to –120dB, 0.5dB/Step Digital De-Emphasis Digital Filter Roll-Off: Sharp or Slow Soft Mute Zero Detect Mute Zero Flags for Each Output DUAL-SUPPLY OPERATION:
+5V Analog, +3.3V Digital 5V TOLERANT DIGITAL INPUTS SMALL SSOP-28 PACKAGE
8371MCP
24LC02B24LC02B2K I²C™ Serial EEPROM
DESCRIPTION PACKAGE TYPE (SOIC)
FEATURE
PIN DESCRIPTION
• Single supply with operation down to 1.8V• Low-power CMOS technology - 1 mA active current typical - 1µA standby current typical (I-temp)• Organized as 1 block of 256 bytes (1 x 256 x 8)• 2-wire serial interface bus, I²C™ compatible• Schmitt Trigger inputs for noise suppression• Output slope control to eliminate ground bounce• 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility• Self-timed write cycle (including auto-erase)• Page write buffer for up to 8 bytes• 2 ms typical write cycle time for page write• Hardware write-protect for entire memory• Can be operated as a serial ROM• Factory programming (QTP) available• ESD protection > 4,000V• 1,000,000 erase/write cycles• Data retention > 200 years• 8-lead PDIP, SOIC, TSSOP and MSOP packages• 5-lead SOT-23 package• Pb-free finish available• Available for extended temperature ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C
The Microchip Technology Inc. 24AA02/24LC02B(24XX02*) is a 2 Kbit Electrically Erasable PROM. The
operation down to 1.8V, with standby and active currents
has a page write capability for up to 8 bytes of data. The
available in the 5-lead SOT-23 package.mount SOIC, TSSOP and MSOP packages and is also
with a 2-wire serial interface. Low-voltage design permits
24XX02 is available in the standard 8-pin PDIP, surface
of only 1µA and 1 mA, respectively. The 24XX02 also
device is organized as one block of 256x8-bit memory
20X
X42A0
A1
A2
Vss
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
PDIP/SOIC/TSSOP/MSOP
BLOCK DIAGRAM
HV
EEPROM Array
Page
YDEC
XDEC
Sense Amp.
MemoryControlLogic
I/OControlLogic
I/O
WP
SDA
SCL
VCC
VSSR/W Control
Latches
Generator
Name
A0
A1
A2VssSDASCLWP
PDIP SOIC TSSOP MSOP SOT23 Description
Vcc
1 1 1 1
2 2 2 2
3 3 3 3
-
-
-4 4 4 4 25 5 5 56 6 6 67 7 7 7
8 8 8 8
315
4
Not Connected
Not Connected
Not ConnectedGroundSerial Address/Data I/OSerial ClockWrite-Protect Input
1.8V to 5.5V Power Supply
TEST
10 11
BLOCK DIAGRAM PIN CONFIGURATION
PIN ASSIGNMENT
RST
ZEROL
ZEROR
LRCK
DATA
BCK
SCKI
DGND
VDD
SCKO
MDO
MDI
MC
CS
VCC3
AGND2
IOUTL –
IOUTL+
VCC2
VCC1
VCOM3
IREF
VCOM2
VCOM1
AGND1
IOUTR+
IOUTR –
MUTE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCM1738
PIN NAME TYPE FUNCTION
1 RST IN Reset (1)
2 ZEROL OUT Zero Flag for L-Channel.3 ZEROR OUT Zero Flag for R-Channel.4 LRCK IN Left/Right clock (f S ) input for normal operation. (1)
WDCK clock input in external DF mode. Connected to GND in DSD mode.5 DATA IN Serial Audio data input for normal operation. (1)
L-channel audio data input for external DF and DSD modes.6 BCK IN Bit Clock. Input. Connected to GND for DSD mode. (1)
7 SCKI IN System Clock Input for normal operation. (1)
BCK (64f S ) clock input for DSD mode.8 DGND – Digital Ground9 VDD – Digital Supply, +3.3V10 SCKO OUT System Clock Output11 MDO OUT Serial data output for function control register. (2)
12 MDI IN Serial data input for function control register. (1)
13 MC IN Shift Clock for function control register. (1)
14 CS IN Mode Control chip select and latch signal. (1)
15 MUTE IN Analog output mute control for normal operation. (1)
R-channel audio data input for external DF and DSD modes.16 IOUTR – OUT R-Channel Analog Current Output –17 IOUTR+ OUT R-Channel Analog Current Output +18 AGND1 – Analog Ground19 VCOM1 – Internal Bias Decoupling Pin20 VCOM2 – Common Voltage for I/V21 IREF – Output current reference bias pin. Connect 16k resistor to GND.22 VCOM3 – Internal Bias Decoupling Pin23 VCC1 – Analog Supply, +5.0V24 VCC2 – Analog Supply, +5.0V25 IOUTL+ OUT L-Channel Analog Current Output +26 IOUTL – OUT L-Channel Analog Current Output –27 AGND2 – Analog Ground28 VCC3 – Analog Power Supply, +5.0V
NOTES: (1) Schmitt-trigger input, 5V tolerant. (2) Tristate output.
Inpu
t
I/F
8xO
vers
ampl
ing
Dig
ital
Filte
ran
dFu
nctio
nC
ontro
l
Adva
nced
Segm
ent
DAC
Mod
ulat
or
BCK
Syste
m C
lock
Man
ager
ZERO
Det
ect
Pow
er S
uppl
y
RST
MU
TE CS
MC
MD
I
LOREZ
ROREZ
SCKI
Syst
em C
lock
OKCS
MD
O
Func
tion
Con
trol
I/F
Cur
rent
Segm
ent
DAC
Bias
and
VRE
F
Cur
rent
Segm
ent
DAC
V CC 1
V CC2
V CC 3
V DD
DNGD
1DNGA
2DNGA
LRC
K
DAT
AI O
UTL
+
I OU
TL–
IV a
nd F
ilter
I OU
TR–
I OU
TR+
VC
OM2
I REF
VC
OM1
VC
OM3
IV a
nd F
ilter
TEST
12 13
AK4117AK4117Low Power 192kHz Digital Audio Receiver
DESCRIPTION
FEATURE
The AK4117 is a S/PDIF AES/EBU receiver supporting sample rates up to 192kHz and resolution up to 24-bit. The integrated channel status decoder supports both consumer and professional modes. The AK4117 can automatically detect a Non-PCM bit stream. Combining the AK4117 with a multi-channel codec such as AKM’s AK4527B or AK4529 can create a complete AC-3 system. Mode settings can be controlled via microprocessor serial interface. A low power mode is available for normal speed modes and the small 24pin VSOP package saves board space.
BLOCK DIAGRAM
Inpu
t S
elec
tor
Clo
ck
Rec
over
yC
lock
G
ener
ator
DA
IF
Dec
oder
AC
-3/M
PE
G
Det
ect
µP I/
F
Aud
io
I/F
X'ta
l O
scill
ator
PD
N
INT0
LRC
KB
ICK
SD
TO
DA
UX
XTO
XTI
RAV
DD
AVS
S
CD
TIC
DTO
CC
LKC
SN
DV
DD
D
VS
S
MC
KO
RX
0 R
X1
Err
or &
Det
ect
STA
TUS
INT1
Q-s
ubco
debu
ffer
2 to
1
UO
UT
TEST
14
ELECTRICAL ADJUSTMENT PROCEDURE (CD MAIN PART)ELECTRICAL ADJUSTMENT PROCEDURE (CD MAIN PART)
15
PIN LAYOUT
PIN FUNCTION
PIN NAME I/O FUNCTION
External Resistor Pin12kΩ-5% ~ 13kΩ+5% resistor to AVSS externally.
Analog Power Supply PinReceiver Channel 1 (Internal Biased Pin)No Connect
No internal bonding.Receiver Channel 0 (Internal Biased Pin)Digital Power Supply PinDigital Ground PinX'tal Input PinX'tal Output PinOutput Channel Clock PinAudio Serial Data Clock PinAudio Serial Data Output PinAuxiliary Audio Data Input PinMaster Clock Output PinNo Connect
No internal bonding.U-bit Output Pin
When UOUTE bit = “0”, UOUT pin = “L”.Control Data Output PinControl Data Input PinControl Data Clock PinChip Select PinInterrupt 1 PinInterrupt 0 PinPower-Down & Reset PinWhen “L”, the AK4117 is powered-down and reset, and all output pins go to“L” and the control registers are reset to default state.Analog Ground Pin
-
-I
-
I--I
OOOOI
O
-
O
OIII
OO
I
-
R
AVDDRXI
NC
RX0DVDDDVSSXTIXTOLRCKBICKSDTODAUXMCKO
NC
UOUT
CDTOCDTICCLKCSNINT1INT0
PDN
AVSS
1
23
4
56789
1011121314
15
16
171819202122
23
24
Note 1: All input pins except internal biased pins should not be left floating.
6
5
4
3
2
1R
AVDD
NC
RX1
RX0
DVDD
DVSS 7
XTI 8
AVSS
PDN
INT0
INT1
CSN
CCLK
CDTI
CDTO
TopView
10
9XTO
LRCK
BICK 11
SDTO 12
UOUT
NC
MCKO
DAUX
19
20
21
22
23
24
18
17
15
16
14
13
MB95F108AWMB95F108AW8-bit Proprietary Microcontrollers
DESCRIPTION
FEATURE
The MB95100A series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions.
64-pin plastic LQFP (FPT-64P-M03)
• F²MC-8FX CPU core Instruction set optimized for controllers
Multiplication and division instructions 16-bit arithmetic operations Bit test branch instruction Bit manipulation instructions etc.
• Clock Main clock Main PLL clock Subclock (for dual clock product) Sub PLL clock (for dual clock product)
• Timer 8/16-bit compound timer x 2 channels 16-bit reload timer 8/16-bit PPG x 2 channels 16-bit PPG x 2 channels Timebase timer Watch prescaler (for dual clock product)
• LIN-UART Full duplex double buffer Clock asynchronous or synchronous serial transfer capable
• UART/SIO Clock asynchronous or synchronous serial transfer capable
• I²C* Built-in wake-up function
• External interrupt Interrupt by edge detection (rising, falling, or both edges can be selected) Can be used to recover from low-power consumption modes.
• 10-bit A/D converter 10-bit resolution
• Low-power consumption (standby mode) Stop mode Sleep mode Watch mode (for dual clock product) Timebase timer mode
• I/O port: Max 55 General-purpose I/O ports (Nch open drain) : 6 ports General-purpose I/O ports (CMOS) : 49 ports
TEST
16 17
PIN ASSIGNMENT
ssV
A0
NA/03
P0 0
NA/13
P1 0
NA/23
P2 0
NA/33
P3 0
NA/43
P4 0
NA/53
P5 0
NA/63
P6 0
NA/73
P7 0
NA/04
P8 0
NA/14
P9 1
NA/ 24
P0 1
NA/3 4
P1
NIS/76
PT
OS/66
PK
CS/56
P
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc 1 48 P64/EC1AVR 2 47 P63/TO11
P E3/INT13 3 46 P62/TO10P E2/INT12 4 45 P61/PPG11P E1/INT11 5 44 P60/PPG10P E0/INT10 6 43 P53/TRG1
P83 7 42 P52/PPG1P82 8 41 P51/SDA0P81 9 40 P50/SCL0P80 10 39 P24/EC0
P71/TI0 11 38 P23/TO01P70/TO0 12 37 P22/TO00
MOD 13 36 P21/PPG01X0 14 35 P20/PPG00X1 15 34 P14/PPG0
Vss 16 33 P13/TRG0/ADT G
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ccV
0G
PA1
X/ 2G
PA 0
X/1G
PT
SR
P00
TNI/00
P10
TNI/10
P20
TNI/2 0
P30
TNI/3 0
P40
TNI/40
P50
TNI/50
P60
TNI/60
P70
TNI/7 0
0IU/ 01
P0
OU/ 1 1
P0
KC
U2 1P
64
TOP VIEW
PIN DESCRIPTION
(Continued)
Pin no. Pin name Circuit type Description
1 AVcc ⎯ A/D power supply pin
2 AVR ⎯ A/D reference input pin
3 PE3/INT13
PGeneral-purpose I/O portThe pins are shared with the external interrupt input.
4 PE2/INT12
5 PE1/INT11
6 PE0/INT10
7 P83
O General-purpose I/O port8 P82
9 P81
10 P80
11 P71/TI0H
General-purpose I/O port.The pin is shared with 16 - bit reload timer ch0 output.
12 P70/TO0General-purpose I/O port.The pin is shared with 16 - bit reload timer ch0 input.
13 MOD B An operating mode designation pin
14 X0A Crystal oscillation pin
15 X1
16 Vss ⎯ Power supply pin (GND)
17 Vcc ⎯ Power supply pin
18 PG0 H General-purpose I/O port.
19 PG2/X1AH/A
Single-system product is general-purpose port. Dual-system product is Crystal oscillation pin (32 kHz). 20 PG1/X0A
21 RST B’ Reset pin
22 P00/INT00
CGeneral-purpose I/O port.The pins are shared with external interrupt input. Large current port.
23 P01/INT01
24 P02/INT02
25 P03/INT03
26 P04/INT04
27 P05/INT05
28 P06/INT06
29 P07/INT07
30 P10/UI0 GGeneral-purpose I/O port.The pin is shared with UART/SIO ch0 data input.
TEST
18 19
Pin no. Pin name Circuit type Description
31 P11/UO0
H
General-purpose I/O port.The pin is shared with UART/SIO ch0 data output.
32 P12/UCK0 General-purpose I/O port.The pin is shared with UART/SIO ch0 clock I/O.
33 P13/TRG0/ADTG
General-purpose I/O port.The pin is shared with 16-bit PPG ch0 trigger input (TRG0) and A/D trigger input (ADTG).
34 P14/PPG0 General-purpose I/O port.The pin is shared with 16-bit PPG ch0 output.
35 P20/PPG00
H
General-purpose I/O port.The pins are shared with 8/16-bit PPG ch0 output. 36 P21/PPG01
37 P22/TO00 General-purpose I/O port.The pins are shared with 8/16-bit compound timer ch0 output. 38 P23/TO01
39 P24/EC0 General-purpose I/O port.The pin is shared with 8/16-bit compound timer ch0 clock input.
40 P50/SCL0I
General-purpose I/O port.The pin is shared with I2C ch0 clock I/O.
41 P51/SDA0 General-purpose I/O port.The pin is shared with I2C ch0 data I/O.
42 P52/PPG1H
General-purpose I/O port.The pin is shared with 16-bit PPG ch1 output.
43 P53/TRG1 General-purpose I/O port.The pin is shared with 16-bit PPG ch1 trigger input.
44 P60/PPG10
K
General-purpose I/O port.The pins are shared with 8/16-bit PPG ch1 output. 45 P61/PPG11
46 P62/TO10 General-purpose I/O port.The pins are shared with 8/16-bit compound timer ch1 output. 47 P63/TO11
48 P64/EC1 General-purpose I/O port.The pin is shared with 8/16-bit compound timer ch1 clock input.
49 P65/SCK General-purpose I/O port.The pin is shared with LIN-UART clock I/O.
50 P66/SOT General-purpose I/O port.The pin is shared with LIN-UART data output.
51 P67/SIN L General-purpose I/O port.The pin is shared with LIN-UART data input.
52 P43/AN11
J General-purpose I/O port.The pins are shared with A/D analog input.
53 P42/AN10
54 P41/AN09
55 P40/AN08
Pin no. Pin name Circuit type Description
56 P37/AN07
J General-purpose I/O port.The pins are shared with A/D analog input.
57 P36/AN06
58 P35/AN05
59 P34/AN04
60 P33/AN03
61 P32/AN02
62 P31/AN01
63 P30/AN00
64 AVss ⎯ A/D power supply pin (GND)
TEST
20 21
BLOCK DIAGRAM
1
P80 ~ P83
P14/PPG0
P53/TRG1
P65/SCK
P67/SIN
PE0/INT10 ~ PE3/INT1 3
AV CC
AV SS
AVR
P52/PPG1
P50/SCL0
P51/SDA0
P40/AN08 ~ P43/AN11
P30/AN00 ~ P37/AN07
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P12/UCK0
P62/TO10
P61/PPG11
P60/PPG10
P63/TO11
P 00/INT00 ~ P07/INT07
P10/UI0
P64/EC1
P71/TI0
P66/SOT
P70/TO0
RST
X0,X1
PG2/X1A*
PG1/X0A*
PG0
MOD, VCC, VSS
P13/TRG0/ADTG
P20/PPG00
P11/UO0
I 2C
F 2MC-8FX CPU
UART/SIO
16 bit-PPG ch0
8/16-bit PPG ch0
10-bit A/Dconverter
C
16-bit PPG ch1
LIN-UART
8/16-bit PPG ch1
ROM
RAM
Port Port
External interrupt ch8 to ch11
8/16-bit compoundtimer ch0
16-bit reload timer
8/16-bit compoundtimer ch1
Interrupt control
Wild register
Reset control
Clock control
Watch prescaler
Watch counter
External interrupt ch0 to ch7
sub lanretnI
* : Single-system product is general-purpose port, and dual-system product is subclock oscillation.
Other pins
S5L9290X02S5L9290X02DIGITAL SIGNAL PROCESSOR FOR INTERNET AUDIO
DESCRIPTION
FEATURE
S5L9290X02 is a signal processing LSI for the Internet Audio (CD-MP3 etc) interface only. Digital processing function (EFM demodulation, error correction), spindle motor servo processing, wide capture range DPLL and 1-bit DAC for the Internet Audio CD player are installed in S5L9290X02.
• Signal processing part— EFM data demodulation— Frame sync detection, protection, insertion— Sub code data processing (Q data CRC check, Q data register installed)— Error correction (C1: 2 error correction, C2: 4 erasure correction)— Installed 16K SRAM for De-interleave— Interpolation— Digital audio interface— CLV servo control (X1, X2)— Wide capture range digital PLL ( ± 50%)• Digital filter, DAC part— 4 times over sampling digital filter— Digital de-emphasis (can be process the 32kHz, 44.1kHz, 48kHz)— Sigma-delta stereo DAC installed— Audio L.P.F installed
48-LQFP-0707#1
TEST
22 23
BLOCK DIAGRAM PIN CONFIGURATION
DPL
L
CLV
Serv
o
LOC
KSM
EFSM
DP
SMD
SW
DC
K
EFM
I
VCO
1LF
Tim
ing
Gen
erat
or
Mic
omIn
terf
ace
WFC
KRF
CK
C4M XI
N
ISTA
T
MLT
MD
AT
MC
KM
UTE
Subc
ode
Out
EFM
Dem
odul
ator
ECC
16K
SRA
M
Addr
ess
Gen
erat
or
SQC
KSB
CK
SOS1
SQD
TSB
DT
Inte
rpol
ator
I/O
Inte
rfac
e
JITB
LPF
PWM
SAD
TOLR
CKO
BCKO
LCH
OU
TRC
HO
UT
VHAL
FVR
EF
1-bi
tD
AC
Dig
ital
Out
Dig
ital
Filte
r
C2P
OD
ATX
SAD
TILR
CKI
BCKI
S5L9290X02DSP+DAC
48-LQFP-0707
VSSA_PLL
VCO1LF
VSSD_PLL
VDDD_PLL
XIN
XOUT
EFMI
LOCK
SMEF
C2PO
JITB
DATX
VDDD3-5V
VDDD2-3V
SBCK
SQDTSMON
VT
SE
T
SD
MS
KC
DW
MUTE
IK
CB
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
VDDD1_5V
VSSD1_5V
SF
KL
SF
KL
BT
ES
ER
TLM
TA
DM
KC
M
TA
TS I
1S0
S
KC
QS
VSSD2-3V
SADTO
LRCKO
BCKO
IK
CRL
IT
DA
S
CA
D_D
SS
V
CA
D_D
DD
V
TU
OH
CR
CA
D_A
SS
V
FE
RV
FLA
HV
CA
D_A
DD
V
TU
OH
RL
L LP_
AD
DV
TEST
24 25
PIN DESCRIPTION
NO. NAME I/O Pin Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VSSA_PLL
VCO1LF
VSSD_PLL
VDDD_PLL
VDDD1-5V
XIN
XOUT
VSSD1
EFMI
LOCK
SMEF
SMDP
SMDS
WDCK
TESTV
LKFS
C4M
RESETB
MLT
MDAT
MCK
ISTAT
SOS1
SQCK
SQDT
MUTE
VDDD2-3V
VSSD2
VDDD3-5V
SBCK
JITB
C2PO
DATX
SADTO
-
O
-
-
-
I
O
-
I
O
O
O
O
O
I
O
O
I
I
I
I
O
O
I
O
I
-
-
-
I
O
O
O
O
Analog Ground for DPLL
Pump out for VCO1
Digital Ground Separated Bulk Bias for DPLL
Digital Power Separated Bulk Bias for DPLL (3V Power)
Digital power (5V Power, I/O PAD)
X’tal oscillator input (16.9344MHz)
X’tal oscillator output
Digital Ground (I/O PAD)
EFM signal input
CLV Servo locking status ouput
LPF time constant control of the spindle servo error signal
Phase control output for Spindle Motor drive
Speed control output for Spindle Motor drive
Word clock output (Narmal Speed : 88.2kHz, Double Speed : 176kHz)
Various Data/Clock Input
The Lock status output of frame sync
4.2336MHz clock output
System Reset at ‘L’
Latch data input from Micom
Serial data input from Micom
Serial data receiving clock input from Micom
The internal status output to Micom
Subcode sync signal (S0+S1) output
Subcode-Q data transfering bit clock input
Subcode-Q data serial output
System mute at ‘H’
Digital Power (3V Power, Internal Logic)
Digital Ground (Internal Logic)
Digital Power (5V Power, I/O PAD)
Subcode data transfering bit clock
Internal SRAM jitter margin status output
C2 pointer output
Digital audio data output
Serial audio data output (48 slot, MSB first)
NO. NAME I/O Function Description
35
36
37
38
39
40
41
42
43
44
45
46
47
48
LRCKO
BCKO
BCKI
LRCKI
SADTI
VSSD_DAC
VDDD_DAC
RCHOUT
VSSA_DAC
VREF
VHALF
VDDA_DAC
LCHOUT
VDDA_PLL
O
O
I
I
I
-
-
O
-
O
O
-
O
-
Channel clock output
Bit clock output
Bit clock input
Channel clock input
Serial audio data input (48 slot, MSB first)
Digital Ground for DAC
Digital Power for DAC (3V Power)
Right-Chnanel audio output through DAC
Analog Ground for DAC
Referance Voltage output for bypass
Referance Voltage output for bypass
Analog Power for DAC (3V Power)
Left-Channel audio outpu through DAC
Analog Power for PLL (3V Power)
TEST
26 27
K4S641632HK4S641632HSDRAM 64Mb H-die
DESCRIPTION
FEATURE
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG?s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
• JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed address• Four banks operation• MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave)• All inputs are sampled at the positive going edge of the system clock• Burst read single-bit write operation• DQM (x4,x8) & L(U)DQM (x16) for masking• Auto & self refresh• 64ms refresh period (4K cycle)• Pb-free Package• RoHS compliant
BLOCK DIAGRAM
Ban
k Se
lect
Dat
a In
put R
egis
ter
4M x
4 /
2M x
8 /
1M x
16
4M x
4 /
2M x
8 /
1M x
16
PMA esneS
reffuB tuptuOlortnoC O/I
Col
umn
Dec
oder
Late
ncy
& B
urst
Len
gth
Prog
ram
min
g R
egis
ter
retsigeR sserddA
reffuB woRretnuoC hserfeR
reffuB .loCredoceD woR
SARL
RBCL
LCK
E
LRA
SLC
BRLW
ELD
QM
CLK
CK
EC
SR
AS
CA
SW
EL(
U)D
QM
LWE
LDQ
M
DQ
i
CLK
AD
D
LCAS
LWC
BR
4M x
4 /
2M x
8 /
1M x
16
4M x
4 /
2M x
8 /
1M x
16
Tim
ing
Reg
iste
r
* Samsung Electronics reserves the right to change products or specification without notice.
TEST
28 29
PIN CONFIGURATION
PIN
S1L9226XS1L9226XRF AMP & SERVO SIGNAL PROCESSOR
DESCRIPTION
FEATURE
As a pre-signal & servo signal processor for the DISC-MAN, S1L9226X is a low voltage, low consumption current IC that can read CD-RW, and CD-R discs and can be applied to various products, such as the CDP/VCD/CDMP3 for the DISC-MAN. It is a hard-wired free-adjustment servo, which automatically controlled the control point of the pre-signal portion.
• RF amplifier (CD, CD-R, CD-RW applicable)• Gain setting & monitoring for the CD-R, CD-RW DISC• RFAMP offset adjustment• Focus error amp & Febias adjustment• Tracking error amp & balance, gain adjustment• FOK, defect, mirror detect• Center voltage amplifier• APC (Automatic Power Control)• RF AGC & EQ control (AGC Level Control Compatible)• Enhanced EFM slice (Double Asymmetry Method)• Focus servo loop & offset adjustment• Tracking servo loop & offset adjustment• Sled servo loop• Spindle servo loop• Auto-sequence• Fast search mode (1 - 36000 track jump)• Interruption countermeasure• Focus & Tracking servo muting controlled by EFM duty check• RF peaking prevention system by EFM duty check• Focus, tracking, spindle loop pole move option• Operating voltage 2.7V ??3.3V• Power saving mode
<Notice> LPC Control used by side beam signal, it related to pick-up assurance. When used pick-up, the specification is present extra.
48-LQFP-0707#1
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip selectDisables or enables device opemasking or enabling all inputs except ration by CLK, CKE and DQM
CKE Clock enableMasks system clock to freeze operat ion from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.
A0 ~ A11 AddressRow/column addresses are multiplexed on the same pins.Row address : RA0~ RA11,
Column address : (x4 : CA0 ~ CA9 ,x8 : CA0 ~ CA8 ,x16 : CA0 ~ CA7)
BA 0 ~ BA1 Bank select addressSelects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.
RAS Row address strobeLatches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.
CAS Column address strobeLatches column addresses on the positive going edge of the CLK with CAS low.Enables column access.
WE Write enableEnables write operation and row precharge.Latches data in starting from CAS, WE active.
DQM Data input/output maskMakes data output Hi-Z, tSHZ after the clock and masks the output.Blocks data input when DQM active.
DQ0 ~ X15 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/groundIsolated power supply and ground for the output buffers to provide improved noise immunity.
N.C/RFUNo connection/reserved for future use
This pin is recommended to be left No Connection on the device.
123456789101112131415161718192021222324252627
545352515049484746454443424140393837363534333231302928
(Top view)
54Pin TSOP (II)(400mil x 875mil)(0.8 mm Pin pitch)
x16 x8 x4 x16x8x4VDDDQ0
VDDQDQ1DQ2VSSQDQ3DQ4
VDDQDQ5DQ6VSSQDQ7VDD
LDQMWE
CASRAS
CSBA0BA1
A10/APA0A1A2A3
VDD
VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8VSSN.C/RFUUDQMCLKCKEN.CA11A9A8A7A6A5A4VSS
VDDN.C
VDDQN.C
DQ0VSSQ
N.CN.C
VDDQN.C
DQ1VSSQ
N.CVDDN.CWE
CASRAS
CSBA0BA1
A10/APA0A1A2A3
VDD
VSSN.CVSSQN.CDQ3VDDQN.CN.CVSSQN.CDQ2VDDQN.CVSSN.C/RFUDQMCLKCKEN.CA11A9A8A7A6A5A4VSS
VDDDQ0
VDDQN.C
DQ1VSSQ
N.CDQ2
VDDQN.C
DQ3VSSQ
N.CVDDN.CWE
CASRAS
CSBA0BA1
A10/APA0A1A2A3
VDD
VSSDQ7VSSQN.CDQ6VDDQN.CDQ5VSSQN.CDQ4VDDQN.CVSSN.C/RFUDQMCLKCKEN.CA11A9A8A7A6A5A4VSS
TEST
30 31
BLOCK DIAGRAM
4
12
RF AGC & EQControl
Focus OK DetectDefect Detect Mirror
Gen
CenterVoltage
APC. LaserControl &
LPC
Tracking Servo Loop- Gain & Phase Compensation- Track Jump- Offset Adjust- TZC Gen.
Tracking Error(RW)
I/V AMP
RF & FocusError (CD-RW)
I/V AMP
Hardware Logic- Auto-Sequencer- Fast Search- Febias, Focus Servo, Tracking Offset ADJ.- Tracking Balance & Gain Adjust- Interruption Detect- EFM Muting System
Sled Servo &Kick Gen
SpindleServo LPFEFM
ComparatorMicom Data Interface Logic Decoder
Focus Servo Loop- Gain & Phase Compensation- Focus Search- Offset Adjust- FZC Gen.
EQO
PD
LD
LPFT
TEIO
TZC&SSTOP
ATSC
TEO
TEM
SLP
SLO
SLM
FEO
FEM
SPDLO
SPDLM
IQ
E
OF
R
MF
R
CQ
E
FE
RV
ED
P
FD
P
DB
DP
CA
DP
TA
TSI
KC
M
AT
AD
M
TLM
TE
SE
R
KC
DW
IVL
C
KC
OL
YS
A
MF
E
5
45
46
44
43
6
7
8
9
10
11
1413 15 16 17 19 18 20 22 21
24
23
30
29
25
26
27
28
29
36
33
34
35
37
38
3941 40424748123
EFMI
DCCI
DCC0
MCP
DCB
VCC/VDD
FRSH
FSET
FLB
FGD
FSI
TGU
PIN CONFIGURATION
PIN DESCRIPTION
S1L9226X
OE
T
ME
T
PLS
OLS
MLS
ISTAT
MCK
MDATA
MLT
RESET
WDCK
CLVI
LOCK
ASY
EFM
SPM
IM
FE
CC
V
HS
RF
TE
SF
BLF
DG
F
IS
F
UG
T
OQ
E
IQ
E
OF
R
MF
R
PD
LD37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
SPO
ME
F
OE
F
DN
G
PO
TS
S/C
ZT
OIE
T
TF
PL
CS
TA
PDAC
PDBD
PDE
DCB
MCP
DCCI
DCCO
VREF
EQC
Pin No. Symbol I/O Description
1 RFM I RF summing amp. inverting input
2 RFO O RF summing amp. output
3 EQI I RFO DC eliminating input(use by MIRROR, FOK ,AGC & EQ terminal)
4 EQO O RF equalizer output
5 EFMI I EFM slice input. (input impedance 47K)
6 VCC P Main power supply
7 FRSH I Capcitor connection to focus search
8 FSET I Filter bias for focus,tracking,spindle
9 FLB I Capacitor connection to make focus loop rising band
10 FGD I Terminal to change the hign frequency gain of focus loop
11 FSI I Focus servo input
12 TGU I Connect the component to change the high frequency of tracking Loop
13 ISTAT O Internal status output
14 MCK I Micom clock
15 MDATA I Data input
16 MLT I Data latch input
17 RESET I Reset input
(Continued)
TEST
32 33
MLC3300MLC3300MPEG Audio Layer2/3 and WMA with CDROM Decoder
DESCRIPTION
The MLC3300 is a single chip of ultra low power multi formatdigital audio decoder with additional CDROM decoder. It alsooffers more variety of flexibility and very high performance touser’s application. This product employs new cutting-edge and highperformance RISC-DSP CPU core, very efficient and flexible firmwareand multiplex peripherals. The embedded RISC-DSP core andadvanced architecture provide most efficient performance fordecoding multi format digital audio files and controllability forCompact disc player system.
The MLC3300 is fabricated with advanced CMOS technology anddesigned for consuming innovative ultra low power. The MLC3300decodes MPEG layer2 and layer3 formats and WMA (Windowsmedia audio) format including ASF (Advanced Systems Format) files.The MLC3300 is also designed to be able to employ many kinds ofNon-Volatile memory as external program memory and SDRAM asexternal data memory. The external Non-Volatile memory can beused as not only upgradeable program memory area but alsousers’ data storage. Also the external SDRAM can be used as the flexiblememory buffer for MPEG / WMA bit stream, compressed audio data andtemporary data of the host controller. The MLC3300 supports two waysfor handshaking with host system controller in both paralleland serial communication. The programmable-DAC-controller-configuration and auto-sampling-rate-conversion functionalitiescan be communicated with any general DAC and dedicatedRed Book audio DAC.
FEATURE
1. Physical - Supply voltage: 2.5V ± 10%, I/O supply power: 3.3V ± 10% - Ultra low power consumption: 65mW ± 10% - Flexible crystal frequencies of 16.9344Mhz and 33.8688Mhz - 100 TQFP
2. Firmware - Single-chip MPEG 1/2 layer 2 and 3 decoder with CDROM decoder - Windows Media Audio (WMA) decoding regardless bit rate - Audio decoding of Window Media Video (WMV) - Supports ASF (Advanced Systems Format) decoding - Support ID3 tag V1 and V2 extraction. - Extension to MPEG 2 / layer 2 and 3 for low bit rates (MPEG 2.5 - LSF) - Bit stream with variable bit rates (bit rate switching) are supported. - Full MPEG bit rates including free format - Full bit rates WMA file Decoding - Supports Software MUTE / Pause / Resume
- Supports ISO9660 CDROM Mode1/Mode2 format (CDROM-XA) - Supports Joliet decoding both single-session and multi-session disc - Supports Joliet Level 3 decoding as call UDF Bridge - Supports UDF (Universal Disk Format) decoding in Packet writing format CD-RW disc and in Non-packet writing CD-R disc. - Support the sorting directories and files in name order. - Support the playing list file as like xxx.pls and xxx.m3u - High quality voice recoding - CD-TEXT format decoding in Lead-in area. - Digital volume control - 7-band sound Equalizer for MP3, WMA and Red book audio CD - 7 band graphic Equalizer for MP3, WMA and Red book audio CD - MEBB (MCS Logic Enhanced Bass band) sound algorithm - Optional sampling rate conversion to 44.1Khz for off-chip general audio DAC - Channel mixing or separating for two different audio sources - Improved high quality sound at high compression rate of ESP - Supports time display (Normal / FF / FB) - Dynamic classification of memory area cluster
3. Interface - Serial Host Controller interface / Parallel Host Controller Interface - Audio PCM output delivered via I2S bus - Connection to external memory SDRAM from 16M bits to 256M bits with 16 bits data bus Programmable access time control - Connection to external program memory Flash (NOR type), EPROM and Mask ROM up to 16M bits with 8 bits data bus 2-wire I2C serial EEPROM Host controller direct access to NOR-Flash, EPROM, Mask ROM - Compatible with various format of CDROM (Mode 1, Mode 2/Form 1 and Mode 2/Form 2) - Supports Fast CDROM decoding up to 4X - Real-Time One Error Correction and Detection for CDROM - Additional functionality achievable by downloading supplied firmware - Video CD mode (Play MPEG audio data from VCD) - Audio CD mode 1) Audio bypass mode. 2) Anti-shock proof on audio CD mode:
18 CLVI I Input the spindle control output from DSP
19 WDCK I 88.2KHz input terminal from DSP
20 LOCK I Sled run away inhibit pin (L: sled off & tracking gain up)
21 EFM O EFM output for RFO slice(to DSP)
22 ASY I Auto asymmetry control input
23 SPM I Spindle amp. inverting input
24 SPO O Spindle amp. output
25 SLM I Sled servo inverting input
26 SLO O Sled servo output
27 SLP I Sled servo noninverting input
28 TEM I Tracking servo amp.inverting input
29 TEO O Tracking servo amp. output
30 FEM I Focus servo amp. inverting input
31 FEO O Focus servo amp. output pin
Pin No. Symbol I/O Description
32 GND P Main ground
33 TZC/SSTOP
ITracking zero crossing input & Check the position of pick-up wherther inside or not
34 TEIO B Tracking error output & Tracking servo input
35 LPFT I Tracking error integration input (to automatic control)
36 ATSC I Anti-shock input
37 LD O APC amp. output
38 PD I APC amp. input
39 PDAC I Photo diode A & C RF I/V amp. inverting input
40 PDBD I Photo diode B & D RF I/V amp. inverting input
41 PDF I Photo diode F & tracking(F) I/V amp. inverting input
42 PDE I Photo diode E & tracking(E) I/V amp. inverting input
43 DCB I Capacitor connection to limit the defect detection
44 MCP I Capacitor connection to mirror hold
45 DCCI O Output pin to connect the component for defect detect
46 DCCO I Input pin to connect the component for defect detect
47 VREF O (VCC+GND)/2 Voltage reference output
48 EQC I AGC_equalize level control terminal & capacitor terminal to input in to VCA
TEST
34 35
BLOCK DIAGRAM PIN CONFIGURATION
MLC3300 / MLC3310
57
61DAE
47
ATAD
D
37 2 7 1 7 0 7
KC
MD
9 6 8 6 76
DD V
6 6 5 6
SSV
46 36 26 16 06 95 7 58 5 65
45
44
43
42
41
40
39
38
37
BA1BA0
UDQM
AD12SDCSN
SDCLK
AD11
RASN
CASN
CKE
WEN
VDD
VSS36
35
34
33
32
3130
2928
2726
VDD
BCLKDATA
LRCK
SCOR
VSS
PLLAVDDPLLAVSS
XIXO
IOVDD
IOVSS
81
82
83
84
85
86
87
88
89
90
91
9293
94
9596
9798
99100
SSV
DDV
1 2 3 4 5 6 7 8 9 01 11 21 31 41 51 61 71 81 91 0 2
TOP VIEW100 TQFP
AD10
AD8
SCLK
SDAT
SLAT
SENSEB
HAD0
HAD1
SYNC
CN
nTESER
NC must be connected to ground
DDV
OI
SSVOI
AD5
AD6
AD4
AD3
0DA
7D
6D
5D
4D
2D
3D
1D
0DR ETL IF
AD9
SSV
HAD2
KC
RLD
KCB
D
IOVSSIOVDD
AD7
DDV
LDQM
51D
12 22 32 42 52
50
4948
4746
55 45 2535 15
76
77
78
79
80
HAD3
HAD4HAD5HAD6
7DA
H
01D
9D
8D
31D
21D
11D
41D
]1[5P
]2[5P
AD2
SSVOI
DDV
OI
XISEL
]3[5P
]4[5P
ED
OMSP
1DA
71DAE
81DAE
91DAE
02DAE
NEWE
NEOE
N SCE
] 0[5P
AD[12:0]
D[15:0]
SDCSN
RASN
CASN
WEN
Reset&
Clock
ExternalDAC
Interface
PLLRISC-DSP
CORE
MemoryInterface
MQ
D]L/U[
]0:1[A
B
XIXO
RESETn
FILTER
DDATA
DLRCK
DBCK
DMCK
EK
C
KLC
DS
EPIOP5[4:0]
Cache
XISEL
HostInterface
SCLK
SDAT
SLATSENSEB
PSMODE
DATA
LRCK
BCK
SCOR
CDROMDecoder
SYNC
MP3/WMAFirmware
ROM
EAD[20:16]
NE
WE
NE
OE
NS
CE
[Fig 1] Host Controller Serial Interface
Note: The PSMODE pin has to be stuck to IOVDD for this serial interface mode.
TEST
36 37
PIN DESCRIPTION
Pin# Pin Name I/O DescriptionDefault
I/OMode
Pull-upPull-down
1 FILTER O 820pF capacitor is connected to PLLAVSS for PLL O2 VDD Digital Power supply3 VSS Digital Ground
External SDRAM data bus [0]Also used as data[0] for external program memoryExternal SDRAM data bus [1]Also used as data[1] for external program memoryExternal SDRAM data bus [2]Also used as data[2] for external program memoryExternal SDRAM data bus [3]Also used as data[3] for external program memoryExternal SDRAM data bus [4]Also used as data[4] for external program memoryExternal SDRAM data bus [5]Also used as data[5] for external program memoryExternal SDRAM data bus [6]Also used as data[6] for external program memory
11 VDD Digital Power supply12 VSS Digital Ground
External SDRAM data bus [7]Also used as data[7] for external program memory
14 D8 I/O External SDRAM data bus [8] I Pull-up15 IOVDD IO Power supply16 IOVSS IO Ground17 D9 I/O External SDRAM data bus [9] I Pull-up18 D10 I/O External SDRAM data bus [10] I Pull-up19 D11 I/O External SDRAM data bus [11] I Pull-up20 D12 I/O External SDRAM data bus [12] I Pull-up21 D13 I/O External SDRAM data bus [13] I Pull-up22 D14 I/O External SDRAM data bus [14] I Pull-up23 D15 I/O External SDRAM data bus [15] I Pull-up
External SDRAM address bus [0]Also used as address[0] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [1]Also used as address[1] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [2]Also used as address[2] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [3]Also used as address[3] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [4]Also used as address[4] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [5]Also used as address[5] for external EPROM,Mask-ROM or FLASH-NOR
D0
D1
D2
D3
D4
D5
D6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D7 I/O
AD0 O
AD1 O
AD2 O
AD3 O
AD4 O
AD5 O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
4
5
6
7
8
9
10
13
24
25
26
27
28
29
Pin# Pin Name I/O DescriptionDefault
I/OMode
Pull-upPull-down
External SDRAM address bus [6]Also used as address[6] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [7]Also used as address[7] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [8]Also used as address[8] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [9]Also used as address[9] for external EPROM,Mask-ROM or FLASH-NOR
34 AD10 O External SDRAM address bus [10] O35 VDD Digital Power supply36 VSS Digital Ground
External SDRAM address bus [11]Also used as address [10] for external EPROM,Mask-ROM or FLASH-NORExternal SDRAM address bus [12]Also used as address [11] for external EPROM,Mask-ROM or FLASH-NOR
39 CSN O SDRAM Chip selector O40 CKE O SDRAM clock enable O41 RASN O SDRAM RAS O42 SDCLK O SDRAM clock O43 IOVSS IO Ground44 IOVDD IO Power supply45 CASN O SDRAM CAS O46 WEN O SDRAM WE O
SDRAM Bank selector 0Also used as address [12] for external EPROM,Mask-ROM or FLASH-NORSDRAM Bank selector 1Also used as address [13] for external EPROM,Mask-ROM or FLASH-NORSDRAM Lower data byte DQMAlso used as address [14] for external EPROM,Mask-ROM or FLASH-NORSDRAM Upper data byte DQMAlso used as address [15] for external EPROM,Mask-ROM or FLASH-NORAddress[16] for external EPROM, Mask-ROM orFLASH-NORAddress[17] for external EPROM, Mask-ROM orFLASH-NORAddress[18] for external EPROM, Mask-ROM orFLASH-NORAddress[19] for external EPROM, Mask-ROM orFLASH-NOR
AD6 O O30
31 AD7 O O
33 AD9 O O
32 AD8 O O
37 AD11 O
38 AD12 O
47 BA0 O
48 BA1 O
49 LDQM O
50 UDQM O
51 EAD16 O
52 EAD17 O
53 EAD18 O
54 EAD19 O
O
O
O
O
O
O
O
O
O
O
TEST
38 39
Pin# Pin Name I/O DescriptionDefault
I/OMode
Pull-upPull-down
Address[20] for external EPROM, Mask-ROM orFLASH-NOR
56 EWEN O External FLASH-NOR WEN O57 EOEN O External EPROM, Mask-ROM or FLASH-NOR OEN O58 ECSN O External EPROM, Mask-ROM or FLASH-NOR CSN O59 P5[0] I/O General Purpose I/O I Notes (1) I Notes(1)60 VDD Digital Power Supply61 VSS Digital Ground62 DBCK O I²S Serial Output Clock O63 DLRCK O I²S Serial Output Frame Identification O64 DDATA O I²S Serial Output Data O O65 DMCK O Master clock Output for the DAC O66 IOVSS IO Ground67 IOVDD IO Power supply68 NC I Not Connection (This pin has to connected to IOVSS) I Pull-down69 RESETn I Chip Reset signal active “L” I Pull-up70 P5[1] I/O General Purpose I/O I Notes(1)71 P5[2] I/O General Purpose I/O I Notes(1)72 P5[3] I/O General Purpose I/O I Notes(1)73 P5[4] I/O General Purpose I/O I Notes(1)74 PSMODE I Communication mode with host controller I I75 HAD7 I/O Data bus [7] for parallel interface with host controller I Pull-up76 HAD6 I/O Data bus [6] for parallel interface with host controller I Pull-up77 HAD5 I/O Data bus [5] for parallel interface with host controller I Pull-up78 HAD4 I/O Data bus [4] for parallel interface with host controller I Pull-up79 HAD3 I/O Data bus [3] for parallel interface with host controller I Pull-up80 HAD2 I/O Data bus [2] for parallel interface with host controller I Pull-up81 HAD1 I/O Data bus [1] for parallel interface with host controller I Pull-up82 HAD0 I/O Data bus [0] for parallel interface with host controller I Pull-up83 SENSEB O Communication handshaking output with host controller O
Communication control signal input with host controllerRefer to Chapter 5.1 and 7.4Communication control signal input with host controllerRefer to Chapter 5.1 and 7.4Communication control signal input with host controllerRefer to Chapter 5.1 and 7.4
87 SYNC O CDROM Sync interrupt O88 VDD Digital Power supply89 VSS Digital Ground90 LRCK I LRCK input from CDDSP I91 DATA I Serial bit DATA input from CDDSP I92 BCLK I BCLK input from CDDSP I93 SCOR I Sub-code block Sync from CDDSP I94 XISEL I XI clock selector (Refer to Chapter 5.3) I95 IOVDD IO Power supply96 IOVSS IO Ground97 XISEL I Clock In (16.9344Mhz / 33.8688Mhz) I98 XO O Clock Out O99 PLLAVSS PLL Ground
100 PLLAVDD PLL Power supply
84 SLAT I
O55 EAD20 O
85 SDAT I
86 SCLK I
I
I
I
SST39VF020SST39VF020Multi-Purpose Flash
DESCRIPTION FEATURE
The SST39LF512/010/020/040 and SST39VF512/010/020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8CMOS Multi-Purpose Flash (MPF) manufactured withSST’s proprietary, high performance CMOS SuperFlashtechnology. The split-gate cell design and thick-oxide tunnelinginjector attain better reliability and manufacturabilitycompared with alternate approaches. The SST39LF512/010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF512/010/020/040devices write with a 2.7-3.6V power supply. The devicesconform to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39LF512/010/020/040 and SST39VF512/010/020/040 devicesprovide a maximum Byte-Program time of 20µsec. Thesedevices use Toggle Bit or Data# Polling to indicate thecompletion of Program operation. To protect againstinadvertent write, they have on-chip hardware and SoftwareData Protection schemes. Designed, manufactured, andtested for a wide spectrum of applications, they are offeredwith a guaranteed typical endurance of 10,000cycles.Data retention is rated at greater than 100 years.
The SST39LF512/010/020/040 and SST39VF512/010/020/040 devices are suited for applications that requireconvenient and economical updating of program, configuration,or data memory. For all system applications, theysignificantly improves performance and reliability, while loweringpower consumption. They inherently use less energyduring Erase and Program than alternative flash technologies.The total energy consumed is a function of the appliedvoltage, current, and time of application. Since for anygiven voltage range, the SuperFlash technology usesless current to program and has a shorter erase time, thetotal energy consumed during any Erase or Program operationis less than alternative flash technologies. These devicesalso improve flexibility while lowering the cost for program,data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Programtimes, independent of the number of Erase/Program cyclesthat have occurred. Therefore the system software or hardwaredoes not have to be modified or de-rated as is necessarywith alternative flash technologies, whose Erase and Programtimes increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39LF512/010/020/040 and SST39VF512/010/020/040 devices are offeredin 32-lead PLCC and 32-lead TSOP packages. The SST39LF/VF010 and SST39LF/VF020 are also offered in a 48-ballTFBGA package. See Figures 1, 2, 3, and 4 for pin assignments.
• Organized as 64K x8/ 128K x8/ 256K x8/ 512K x8• Single Voltage Read and Write Operations – 3.0-3.6V for SST39LF512/010/020/040 – 2.7-3.6V for SST39VF512/010/020/040• Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention• Low Power Consumption (typical values at 14 MHz) – Active Current: 5 mA (typical) – Standby Current: 1 µA (typical)• Sector-Erase Capability – Uniform 4 KByte sectors• Fast Read Access Time: – 45 ns for SST39LF512/010/020/040 – 55 ns for SST39LF020/040 – 70 and 90 ns for SST39VF512/010/020/040• Latched Address and Data• Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 1 second (typical) for SST39LF/VF512 2 seconds (typical) for SST39LF/VF010 4 seconds (typical) for SST39LF/VF020 8 seconds (typical) for SST39LF/VF040• Automatic Write Timing – Internal VPP Generation• End-of-Write Detection – Toggle Bit – Data# Polling• CMOS I/O Compatibility• JEDEC Standard – Flash EEPROM Pinouts and command sets• Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) – 48-ball TFBGA (6mm x 8mm) – 34-ball WFBGA (4mm x 6mm) for 1M and 2M• All non-Pb (lead-free) devices are RoHS compliant
TEST
40 41
BLOCK DIAGRAM
PIN ASSIGNMENTS
PIN DESCRIPTION
Y-Decoder
I/O Buffers and Data Latches
Address Buffers & Latches
X-Decoder
DQ7 - DQ0
Memory Address
OE#
CE#
WE#
SuperFlashMemory
Control Logic
A11A9A8
A13A14NC
WE#
VDDNCNC
A15A12
A7A6A5A4
A11A9A8
A13A14NC
WE#
VDDNC
A16A15A12A7A6A5A4
A11A9A8
A13A14A17
WE#
VDDNC
A16A15A12A7A6A5A4
A11A9A8
A13A14A17
WE#
VDDA18A16A15A12A7A6A5A4
SST39LF/VF512SST39LF/VF010
SST39LF/VF020SST39LF/VF040
SST39LF/VF512
12345678910111213141516
OE#A10CE#DQ7DQ6DQ5DQ4DQ3
VSS VSS VSS VSSDQ2DQ1DQ0A0A1A2A3
OE#A10CE#DQ7DQ6DQ5DQ4DQ3
DQ2DQ1DQ0A0A1A2A3
OE#A10CE#DQ7DQ6DQ5DQ4DQ3
DQ2DQ1DQ0A0A1A2A3
OE#A10CE#DQ7DQ6DQ5DQ4DQ3
DQ2DQ1DQ0A0A1A2A3
32313029282726252423222120191817
Standard Pinout
Top View
Die Up
SST39LF/VF020SST39LF/VF020 SST39LF/VF040
Symbol Pin Name Functions
AMS¹-A0
DQ7-DQ0
CE#OE#WE#VDD
VSS
NC
To provide memory addresses. During Sector-Erase AMS-A12 address lines willselect the sector. During Block-Erase AMS-A16 address lines will select the block.To output data during Read cycles and receive input data during Write cycles.Data is internally latched during a Write cycle.The outputs are in tri-state when OE# or CE# is high.To activate the device when CE# is low.To gate the data output buffers.To control the Write operations.To provide power supply voltage :
Unconnected pins
Address Inputs
Data Input/output
Chip EnableOutput EnableWrite EnablePower Supply
GroundNo Connection
3.0-3.6V for SST39LF512/010/020/0402.7-3.6V for SST39VF512/010/020/040
KA9259HDKA9259HD5-Channel Motor Drive IC
DESCRIPTION
FEATURE
PIN ASSIGNMENTS
The KA9259D is a monolithic integrated circuit, and suitable for 5-CH motor driver which drives focus actuator,tracking actuator, sled motor, spindle motor and loading motor of compact disk player system.
. 4-CH Balanced Transformerless(BTL) Driver
. 1-CH (Forward/Reverse) DC Motor Driver With Speed Control Circuit
. Built-in TSD (Thermal Shutdown) Circuit
. Built-in 5V Regulator (With an External PNP Transistor)
. Built-in Mute Circuit
. Wide Operating Supply Voltage Range: 6V~13.2V
28-SSOPH-375
KA9259D
1 2 3 4 5 6 7 8 9 10 11 13 14
28 27 26 25 24 23 22FIN
21 20 19 18 17 16 15
FIN12
1.1O
D
2.1O
D
1.2O
D
2.2O
D
2.4O
D
1 .4O
D
2. 3O
D
1.3O
D
2.4ID
1.4ID
LT
CD
L
3ID
2.5O
D
1.5O
D2.5I
D
1.1ID
2 .1 ID
BE
R
OG
ER
ET
UM
1.5ID
2ID
1D
NG
2D
NG
3D
NG
2C
CV
1C
CV
FE
RV
TEST
42
SPECIFICATIONSSPECIFICATIONS
43
PIN DESCRIPTION
Pin Number Pin Name I/O Pin Function Description
Channel 1 output 1
Channel 1 output 2
Channel 1 input 1
Channel 1 input 2 (Adjustable)
External transistor base drive output
Regulator output
Mute signal input
Ground 1
Channel 5 input 1 (Loading Motor)
Channel 2 input
Channel 2 output 1
Channel 2 output 2
Ground 2
Channel 5 input 2 (Loading Motor)
Channel 5 output 1 (Loading Motor)
Channel 5 output 2 (Loading Motor)
Channel 3 output 1
Channel 3 output 2
Channel 3 input
Channel 5 (Loading Motor) speed control input
Power supply voltage 1
Power supply voltage 2
Bias voltage input
Channel 4 input 1 (Adjustable)
Channel 4 input 2
Channel 3 output 1
Channel 3 output 2
Ground 3
DO1.1
DO1.2
DI1.1
DI1.2
REB
REO
MUTE
GND1
DI5.1
DI2
DO2.1
DO2.2
GND2
DI5.2
DO5.1
DO5.2
DO3.1
DO3.2
DI3
LD CTL
VCC1
VCC2
VREF
DI4.1
DI4.2
DO4.1
DO4.2
GND3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
O
O
I
I
O
O
I
-
I
I
O
O
-
I
O
O
O
O
I
I
-
-
I
I
I
O
O
-
Audio ChannelFrequency ResponseT.H.D. (with A filter)S/N(with A Filter)Analog Output LevelHeadphone Output LevelQuantizationAnalog Output TerminalDigital Output (TOS LINK/RCA)Player RespondsOperation Temperature
Power Source
Power ConsumptionWeight 6.2kg/13.7lbDimensions
* Specifications and design subject to change without notice for improvements.
18W(Standby: Less than 1W)
482(W)x88(H)x380(D)mm/19(W)x3.5(H)x14.9(D)in
SPDIF(IEC958)CD-DA/MP3/WMA-10°C ~ +40°C
100–120VAC or 220–240VAC; 50/60Hz(Supplied AC mains transformer depends on country requirements)
6dB±2dB(load impedance 32 Ohm) 3.5dB±2dB24-bitRCA-2CH/XLR-2CH/XLR MIX-1CH
2 Channels20Hz~20kHz±1dB0.002% (Less than 0.02%)100dB (Better than 90dB)
CD-610
TEST ELECTRICAL PARTLISTELECTRICAL PARTLIST
44 45
Ref. Part No. Description Value Ref. Part No. Description ValueC754 S35608212430 CE820P50/1608,820P 820PC704 C714-715 S35611032530 CE0.01U50K/1608,0.01U 0.01U
X701 3938000880 10MHZ/CSTLS,10MHz 10MHz C728 C738CN706 4428594508 08P/53014/2,53014-08P 53014-08P C740-741 C783Q701 S20110499001 PNP/KTA1504S-Y/SOT23,KTA1504S-Y KTA1504S-Y C785Q702-703 S20260403001 N/FDV303N/SOT23,FDV303N FDV303N C739 S35611532530 CE0.015U50K/1608,0.015U 0.015UIC707 S21161034001 BA33FP/TO252-3,BA33FP BA33FP C711 C724 S35612222530 CE2200P50K/1608,2200P 2200PIC709 S21161054001 BA33C25FP/TO252-5,BA33C25FP BA33C25FP C748-749 C751IC706 S21211642901 MB95F108AW/LQFP64P,MB95F108AW MB95F108AW C778IC703 S21213001501 MLC3300/TQFP100P,MLC3300 MLC3300 C755-758 S35612232530 CE0.022U50K/1608,0.022U 0.022UIC702 S21213480701 S5L9290X/LQFP48P,S5L9290X S5L9290X C760-761IC705 S21235328102 SST39VF020/TSOP,SST39VF020 SST39VF020 C763-765 C767IC704 S21243540702 K4S641632H-TL75/TSOP54P K4S641632H-TL75 C770 C772 C803IC701 S21271480701 S1L9226X/LQFP48P,S1L9226X S1L9226X C721 S35613332530 CE0.033U50K/1608,0.033U 0.033UIC710 S21288280701 KA9259D/SSOPH28P,KA9259D KA9259D C712 C731 S35614722530 CE4700P50K/1608,4700P 4700PD702-705 S22100500001 D/1N4148/SOT23,1N4148 1N4148 C716 S35616832530 CE0.068U50K/1608,0.068U 0.068UFB701 S26001212029 BEAD/HB1M121JT/2012,HB-1M2012-121JT HB-1M2012-121JT X702 S39102999900 16.934MHZ/HC-49U/SMD,16.934MHz 16.934MHzR731-734 R790 S30100007121 R0J/1608,0 0 CN705 S44443412603 03P/12505WR/1.25,12505WR-03P 12505WR-03PR738-739 R751 S30100107121 R1J/1608,1 1 CN704 S44443412604 04P/12505WR/1.25,12505WR-04P 12505WR-04PR757 R792 CN703 S44445520602 02P/20022WR/2,20022WR-02P 20022WR-02PR701 S30101007121 R10J/1608,10 10 CN702 S44510410615 15P/FFCFPC553-1/1.0,FFCFPC553-15P FFCFPC553-15PR796 S30101007231 R10J/2012,10 10 CN701 S44510410616 16P/FFCFPC553-1/1.0,FFCFPC553-16P FFCFPC553-16PR713 R721 R781 S30101037121 R10KJ/1608,10K 10K SW701 S46680020001 PU/MPU12371MLB1,MPU12371MBL1 MPU12371MBL1R775-776 R779R794-795R715 R799 S30101057121 R1MJ/1608,1M 1MR735 S30101337121 R13KJ/1608,13K 13KR711 S30101537121 R15KJ/1608,15K 15K D201-204 2058100996 D/1N4006,1N4006(4007) 1N4006(4007)R704 R706 R708 S30101547121 R150KJ/1608,150K 150K JK202 2128008400 OPTO/TOTX177L,TOTX177L TOTX177LR797 FB201-209 2648609900 H5B/BEAD,VALUE VALUER730 S30101837121 R18KJ/1608,18K 18K R301 3009103973 R10KJ/A,10K 10KR716 S30102037121 R20KJ/1608,20K 20K X201 3938000840 11.3MHZ/CSA,11.2896MHz 11.2896MHzR752-754 S30102217121 R220J/1608,220 220 AN102 4353978210 11P/LW-5267/2.5,ASS'Y-11P ASS'Y-11PR760-761 R772 S30102227121 R2.2KJ/1608,2.2K 2.2K JK203-205 4408194210 XLR/F/5031-030/V,XLR/F XLR/FR710 S30102237121 R22KJ/1608,22K 22K CN206 4428536316 16P/FMN-BTRK/2,FMN-BTRK-16P FMN-BTRK-16PR707 R709 R712 S30102247121 R220KJ/1608,220K 220K CN905 4428589420 20P/ZIF8370,ZIF8370-20P ZIF8370-20PR793 CN205 4428594509 09P/53014/2,53014-09P 53014-09PR729 S30102437121 R24KJ/1608,24K 24K JK206 4438095310 RCA/JK44N/02H/4438095310,RCA02P RCA02PR756 S30102717121 R270J/1608,270 270 JK201 4438095510 RCA/JC27HN/01H/4438095510,RCA01P RCA01PR723-724 S30102747121 R270KJ/1608,270K 270K JK207 4438189610 DS09P/M/4438189610,D-SUB09P D-SUB09PR758-759 S30102797231 R2.7J/2012,2.7 2.7 RLY201-204 5528006900 12V/DPDT1A/S2L1/2,VALUE VALUER705 S30103037121 R30KJ/1608,30K 30K Q201 2008606111-T PNP/KRA107M,KRA107M KRA107MR717 S30103327121 R3.3KJ/1608,3.3K 3.3K C209 C211 3409210071-T EC10U50/SGT,10/50 10/50R719 S30103927121 R3.9KJ/1608,3.9K 3.9K C213-215 C238 R740-743 S30104707121 R47J/1608,47 47 C247 C258 R745-750 C291-293R755 R764-771 C305-306R773-774 C201 3409210141-T EC100U25/SGT,100/25 100/25R782-788 R791 C285 C287-290 3409210971-T EC1U50/SGT,1/50 1/50R720 R778 R780 S30104727121 R4.7KJ/1608,4.7K 4.7K C242 C244 3409222071-T EC22U50/SGT,22/50 22/50R789 C256-257 C260R702 R714 S30104737121 R47KJ/1608,47K 47K C265 C299-300R703 R725-726 S30106837121 R68KJ/1608,68K 68K C202 C204 C223 3409247041-T EC47U25/SGT,47/25 47/25R727 S30108207121 R82J/1608,82 82 C226 C234 C237R718 S30108227121 R8.2KJ/1608,8.2K 8.2K C249-250 C261C717 C787 C798 S34121000422 EC10U16/RC,10/16 10/16 C263 C275 C282C727 C784 C786 S34121010242 EC100U6.3/RC,100/6.3 100/6.3 C297-298C800 C208 C312-313 3509104530-T CE0.1U50Z/Y5V/T,0.1U 0.1UC742 C780 S34122210442 EC220U16/RC,220/16 220/16 C229-231 C233 3609182120-T MA0.0018U100T,0.0018/100(M) 0.0018/100(M)C703 C734 C736 S34124700232 EC47U6.3/RC,47/6.3 47/6.3 C216 C221-222 3609562120-T MA0.0056U100T,0.0056/100(M) 0.0056/100(M)C744 C753 C227C759 C762 C766 C228 C232 3609822120-T MA0.0082U100T,0.0082/100(M) 0.0082/100(M)C768-769 C771 C280 3639104111-T MA0.1U50/ECQVT,0.1/50(M) 0.1/50(M)C729 S34124790422 EC4.7U16/RC,4.7/16 4.7/16 Q202-207 S20160405003 NPN/KRC107S/SOT23,KRC107S KRC107SC730 C773 C796 S35101024321 CE1000P50/1608,1000P 1000P Q208 S2040000100 PNP/KRA107M,KRA107S KRA107SC701 C705-707 S35101045321 CE0.1U50Z/1608,0.1U 0.1U Q209-210 S20560405003 NPN/KTD1304/SOT23,KTD1304 KTD1304C709 C713 IC205-210 IC212 S21101083204 NJM5532M/DMP08P/2,NJM5532M NJM5532MC722-723 IC201 S21161034001 BA33FP/TO252-3,BA33FP BA33FPC725-726 C735 IC202 S21221242701 AK4117/VSOP24P,AK4117 AK4117C737 C743 IC211 S21252145405 74HC04/SOP14P/2,74HC04 74HC04C745-747 C750 IC204 S21275160001 MAX232/SOP16P,MAX232CWE MAX232CWEC752 C777 C779 IC203 S21282287601 PCM1738/SSOP28P,PCM1738 PCM1738C781-782 C792 D205-208 S22300502001 D/BAT54S/SOT23,BAT54S BAT54SC797 C799 L201-202 S26104R73062 4.7UH/3225/ELJFA,4.7 uH 4.7 uHC801-802 R202 R209 S30100007231 R0J/2012,0 0C774-775 S35102004321 CE20P50/1608,20P 20P R213-215 R249C719-720 S35104744331 CE0.47U50Z/2012,0.47U 0.47U R316-317 S30101017231 R100J/2012,100 100C702 C793-794 S35601012430 CE100P50/1608,100P 100P R201 R207-208 S30101027231 R1KJ/2012,1K 1KC732 S35602092430 CE2P50/1608,2P 2P R238 R241 R243C795 S35602202430 CE22P50/1608,22P 22P R267-268C790-791 S35603312430 CE330P50/1608,330P 330P R288-289C708 S35603912430 CE390P50/1608,390P 390P R242 R244 S30101037231 R10KJ/2012,10K 10K
CD-610 CD B'D
CD-610 MAIN B'DCD-610 REAR B'D
Ref. Part No. Description Value Ref. Part No. Description ValueR269-270 R960-961R275-278 R287 R970-981R290-293 R304 R933 R958 S30104717231 R470J/2012,470 470R286 S30101047231 R100KJ/2012,100K 100K R921 R930 R935 S30104727231 R4.7KJ/2012,4.7K 4.7KR247-248 S30101137231 R11KJ/2012,11K 11K R955R203 R240 R245 S30101237231 R12KJ/2012,12K 12K R922 R936 S30108227231 R8.2KJ/2012,8.2K 8.2KR217 S30101337231 R13KJ/1608,13K 13K C903 S34211070350 TT100U10/C,100/10 100/10R205-206 S30102227231 R2.2KJ/2012,2.2K 2.2K C910 S34211090633 TT1U25/A,1/25 01 25R204 R246 S30102237231 R22KJ/2012,22K 22K C909 S35101024331 CE1000P50/2012,1000P 1000PR263-264 C904-905 S35101045331 CE0.1U50Z/2012,0.1U 0.1UR261-262 S30102727231 R2.7KJ/2012,2.7K 2.7K C907-908R250 S30103307231 R33J/2012,33 33 C913-914 C920R210-212 S30103317231 R330J/2012,330 330 C906 S35611032540 CE0.01U50K/2012,0.01U 0.01UR216 R235-237 S30104707231 R47J/2012,47 47R283-285R294-300 D501 2058100996 D/1N4006,1N4006(4007) 1N4006(4007)R234 R239 S30104717231 R470J/2012,470 470 D502-503 2058304100 D/1N4148,1N4148 1N4148R257-260 IC501 2118010932 NJM4556AD/2,4556AD 4556ADR271-272 R279 VR501 3228065700 503B/09/RK097122T,50KB*2 50KB*2R281 R305 R315 AN205 4353978710 09P/53014/2,ASS'Y-9P ASS'Y-9PR282 S30105607231 R56J/2012,56 56 JK501 4438097310 PHN04P/4438097310,PHONE04P PHONE04PR218-233 S30106217330 R620J1/8W/2012,620 1/8W 620 1/8W RLY501 5528006900 12V/DPDT1A/S2L1/2,VALUE VALUER937 S30106807231 R68J/2012,68 68 C501 C504 3409247041-T EC47U25/SGT,47/25 47/25R273-274 S30124305230 R43KF/2012,43K 1% 43K 1% Q501 S20160405003 NPN/KRC107S/SOT23,KRC107S KRC107SC283 C316-317 S35101024331 CE0.001U50J/2012,0.001U 0.001U L501-502 S26102R23025 2.2UH/FIB222KJT/2012,2.2 uH 2.2 uHC203 C205 C210 S35101045331 CE0.1U50Z/2012,0.1U 0.1U R510 R512 S30101027231 R1KJ/2012,1K 1KC212 C218-220 R503 R505 S30102227231 R2.2KJ/2012,2.2K 2.2KC224-225 R511 R513 S30102247231 R220KJ/2012,220K 220KC235-236 C241 R504 R506 S30103307231 R33J/2012,33 33C243 C246 R501-502 S30106227231 R6.2KJ1/8W/2012,6.2K 1/8W 6.2K 1/8WC253-254 C262 C503 C506 S35101045331 CE0.1U50Z/2012,0.1U 0.1UC264 C281 C284 C502 C505 S35608212440 CE820P50/2012,820P 820PC286 C295-296 C507-510C310C267-273 C294 S35601012440 CE100P50/2012,100P 100PC301-302 C304 CN906 4428594505 05P/53014/2,53014-05P 53014-05PC206-207 S35601502440 CE15P50/2012,15P 15P SW902-909 4628985710 TC/THVV501BAA,THVV501BAA THVV501BAAC252 C255 C279 S35601802440 CE18P50/2012,18P 18P SW914-915C274 S35612232540 CE0.022U50K/2012,0.022U 0.022U R901 R909 S30101027231 R1KJ/2012,1K 1K
R907 R915 S30101537231 R15KJ/2012,15K 15KR903 R911 S30102227231 R2.2KJ/2012,2.2K 2.2K
D901 2058304100 D/1N4148,1N4148 1N4148 R908 S30102737231 R27KJ/2012,27K 27KZD901 2058502024 ZD/UZ2.4BM,2.4BM 2.4BM R904 R912 S30103327231 R3.3KJ/2012,3.3K 3.3KVFD901 2328130992 LC/9-ST-37GINK,9-ST-37GINK 9-ST-37GINK R905 R913 S30104727231 R4.7KJ/2012,4.7K 4.7KR916 3009229973 R2.2J/A,2.2 2.2 R906 R914 S30108227231 R8.2KJ/2012,8.2K 8.2KX901 3938000880 10MHZ/CSTLS,10MHz 10MHzLUG901 4350001200 01P/CNT,ASS'Y-01P ASS'Y-01PAN906 4353978410 05P/AN/2,ASS'Y-05P ASS'Y-05P RMC901 2438200950 37.9KHZ/RPM7138,RPM7138-H4 RPM7138-H4AN101 4353978610 10P/AN/2,ASS'Y-10P ASS'Y-10P CN902 4428594504 04P/53014/2,53014-04P 53014-04PAN902 4353978810 04P/AN/2,ASS'Y-04P ASS'Y-04P SW901 4628985710 TC/THVV501BAA,THVV501BAA THVV501BAACN901 4428589420 20P/ZIF8370/1.25,ZIF8370-20P ZIF8370-20P C902 3409210071-T EC10U50M/SG/T,10/50 10/50CN903 4428594508 08P/53014/2,53014-08P 53014-08P R928 S30101017231 R100J/2012,100 100SW913 4628985710 TC/THVV501BAA,THVV501BAA THVV501BAA C901 S35101024331 CE1000P50/2012,1000P 1000PSW917-932BZ901 5540000050 BUZZER/PKM22EPP-40,CAP-1205SL(9.5) CAP-1205SL(9.5)C915 3409222033-T EC22U16/SET,22/16 22/16C911 C921 3409247033-T EC47U16M/SE/T,47/16 47/16Q903 S20110499001 PNP/KTA1504S-Y/SOT23,KTA1504S-Y KTA1504S-YQ902 S20160405003 NPN/KRC107S/SOT23,KRC107S KRC107SQ901 S20160499001 NPN/KTC3875S-Y/SOT23,KTC3875S-Y KTC3875S-YIC903 S21103030502 KIA7045AF/SOT89,KIA7039AF KIA7039AFIC901 S21211642902 MB95F108AW/LQFP64P,MB95F108AHW MB95F108AHWIC902 S21233089902 24LC02B/SOP08P,24LC02B 24LC02BD902 S22300502001 D/BAT54S/SOT23,BAT54S BAT54SFB901 S26001212029 2200PF/FIB222JT/2012,HB-1M2012-121JT HB-1M2012-121JTR917-918 R954 S30101027231 R1KJ/2012,1K 1KR910 R925-927 S30101037231 R10KJ/2012,10K 10KR939 R948-950R957 R966-967R991R923 R944 S30101537231 R15KJ/2012,15K 15KR983-990 S30102217231 R220J/2012,220 220R919 R929 R932 S30102227231 R2.2KJ/2012,2.2K 2.2KR968 R998-999R956 S30102297230 R2.2J/2012,2.2 2.2R924 R945 S30102737231 R27KJ/2012,27K 27KR920 R934 S30103327231 R3.3KJ/2012,3.3K 3.3KR992-993R969 S30103337231 R33KJ/2012,33K 33KR902 R931 S30104707231 R47J/2012,47 47R941-943R951-953
CD-610 REMOTE SENSE B'D
CD-610 FRONT B'D
CD-610 HEADPHONE B'D
CD-610 FUNCTION KEY B'D
TOP AND BOTTOM VIEW OF P.C.BOARD TOP AND BOTTOM VIEW OF P.C.BOARD
46 47
48 49
BOTTOM
CD MAIN B’D 4002900300
WIRING DIAGRAMWIRING DIAGRAM
50 51
REAR B’D
HEADPHONE
B‘D
SMPS
FUNCTION B‘D
CD MECH
FRONT B‘D
RemoteSenseB‘D
CN905CN206CN205
AN205
CP702
CN906
AN102
CN1
CN102
CN902
AN906
AN902
CN901AN101
CN101
INPUT
BLOCK DIAGRAMBLOCK DIAGRAM
52 53
SCHEMATIC DIAGRAMSCHEMATIC DIAGRAM
54 55
CD PART
56 57
FRONT PART
58 59
REAR PART
EXPLODED VIEW OF CABINET & CHASSIS / MECANICAL PARTLISTEXPLODED VIEW OF CABINET & CHASSIS / MECANICAL PARTLIST
60 61