Catapult™ C SynthesisCrossing the Gap between Algorithm and Hardware Architecture

Mac MooreNorth American Product SpecialistAdvanced Synthesis Solutions

MAPLD 2005

Introducing Catapult C Synthesis Catapult C Synthesis launched May 31st, 2004

— 100+ man years of research and development— 3 years of customer proof and validation— Initial focus on wireless companies:

STMicroelectronics, Nokia, Ericsson

Product took center stage at DAC 2004— “ Most important announcement at DAC”

- Gary Smith, Dataquest— No. 1 “must see” product

- Gartner Dataquest annual DAC list

Catapult news in 2005— EDN Top 100 products— John Cooley’s DAC must see list— Recent Press Releases: SystemC verification

extension, Fraunhofer, Panasonic, Sanyo customer adoption

Front Page -EETimes

Catapult C Synthesis – Algorithm to RTLDevelop Algorithms using ANSI C+

+No proprietary extension

Focus on the functional intent

Develop Algorithms using ANSI C++

No proprietary extensionFocus on the functional intent

Synthesize with Catapult CExplore the design space

Find the optimal architecture

Synthesize with Catapult CExplore the design space

Find the optimal architectureTechnology

Files

TechnologyFiles

ArchitecturalConstraints

ArchitecturalConstraints

Generate High Speed ModelsVerilog, VHDL, SystemC

Accelerate system level verification

Generate High Speed ModelsVerilog, VHDL, SystemC

Accelerate system level verification

Untimed TLMUntimed TLM

Timed TLMTimed TLM

Cycle TLMCycle TLM

Generate Target Optimized RTL Faster and better than hand-coded

For ASIC, FPGA or FPGA prototyping of ASICs

Generate Target Optimized RTL Faster and better than hand-coded

For ASIC, FPGA or FPGA prototyping of ASICs

Automatically Verify the RTLGeneration of testbench infrastructure

Seamlessly reuse original C++ test vectors

Automatically Verify the RTLGeneration of testbench infrastructure

Seamlessly reuse original C++ test vectors

Optimized Design Architecture

Exhaustive design space exploration Often yields superior designs over hand-coded RTL

Algorithmic C++

RTLOptimization

Scope

Local Minima

X

X

Architectural Scenarios

Are

aGlobal Minima – Out of Reach

Within Reach!

XIP Block

A

A

A

A

A

Result

Result

Incremental Design Analysis Analysis tools tackle algorithm

complexity and interactively converge to the optimal solution

“Cause-and-Effect” cross-probing links any result with the original C source

Graphical reports provide better understanding of synthesis results

Ease-of-Use smooths learning curve and facilitates tool adoption

User interface built on live database— Incremental analysis— Incremental exploration— Incremental optimization

Customer Adoption Design types

— Filters (FIR, IIR…)— Tranforms (FFT, DCT …)— Equalizers— Interleavers— FEC (Viterbi, Reed Solomon…)— Video Line Filters— JPEG/MPEG Pixel pipes— …

Applications:— Wireless Communications— Satellite Communications— WLAN— Base Stations— VoIP— Sound Broadcast— Video and Multimedia— Digital TV— Storage— Aerospace & Military— …

Catapult C Synthesis Summary Only pure ANSI C++ algorithmic synthesis tool

— Easiest to write, most concise, fastest to simulate, best results

1st production quality C++ tool— Over 30 completed ASIC & FPGA designs— Documented case studies,

references and testimonials

Used by top customers worldwide— ST, Ericsson, Nokia, Alcatel, Siemens, Panasonic, Sanyo

Focus: Engineers developing complex wireless and video hardware— Yields safer silicon with fewer bugs— More efficient design flow yielding smaller hardware in less time— Automated verification flow