Case Studies: MIPS, ARM, x86, M68000,and HP 3000

P. A. Wilsey

Univ of Cincinnati

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Examples Studied

1. MIPS: modern load/store architecture; principlearchitecture of textbook.

2. ARM: modern load/store architecture; low power,commercially successful.

3. X86: old style general register architecture.4. Motorola 6800: old style general register architecture;

orghogonal opcode/operand encoding; once commerciallysuccessful.

5. HP 3000: old style stack architecture (mini-computer);logically separates program and instruction spaces.

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MIPS

Basic Characteristics

I load/store architectureI 32-bit/64-bit wordsize (discussing 32-bit versions here)I 32-bit program counter (PC)I 32 32-bit general purpose registersI 32 32-bit ft pt registers located in floating-point coprocessorI word and byte addressable (word operands must be

aligned)I 32-bit status register (Figure B.7.1)I 2 operating modes: user and privilegedI big (word 0 ≡ byte 0) or little (word 0 ≡ byte n) endian

supportI memory mapped I/O

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Instruction Format

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits ALL instrs are 32 bits longop rs rt rd shamt funct Arith instr formatop rs rt address/immediate Transfer, branch, immediateop absolute address Jump instructions

I shamt: shift amount

I funct: additional info to distinguish operation

I register indirect jumps availble

I no separate integer condition codes, branches holdoperands to test

I delayed branching with pc relative branching

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The CPU Registers

I R0 always holds the value zeroI Technically available for general useI By convention, usage setup as:

I R1, R26, and R27: reserved for the assembler andoperation systems

I R2, R3: used for return valuesI R4-R7: used for the first four arguments to subroutinesI R8-R15, R24, R25: general use, contents preserved by

called environmentI R16-R23: general use, contents preserved by calling

environmentI R28: points to the middle of a 64K memory block used to

hold static dataI R29: stack pointerI R30: frame pointerI R31: return address

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Exceptions

I all exceptions trap to address 0x80000180 (where theexecption handler is assumed to reside)

I 32-bit cause register (Figure B.7.2), holds cause ofexception

I instructions mfc0/mfc1 and mtc0/mtc1 move from/tocontrol processor (which contains info on the exception)

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The ARM

Basic Characteristics

I load/store architectureI 32-bit wordsizeI word and byte addressable (word operands must be

aligned)I 32-bit status registerI 6 different operating modes:

User, FIQ, IRQ, Supervisor, Abort, and UndefinedI 16 32-bit general purpose registers (R15 is the PC)I banked registers (some have alternates in each operating

mode)I big or little endian support (set by external pin)I conditional execution of instructionsI instructions can conditionally set condition codes

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Instruction Format

031 27 19 15 11 3

RmOtherRdRnOpcodeCond

I offset summed with RnI offset is specified as an immediate or as a registerI register ofset values can be shifted right/left before

summingI offsets store magnitude onlyI offset direction held in opcode

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Status Register (CPSR)

Condition CodesN, Z, C, V

Processor Mode Bits

Interrupt disable bits (FIQ, IRQ)

30 67 4 02831 29

I condition codes conditionally set (selected by instr bit(Figure B.2)

I banked for each operating modeI Operating Modes: User, FIQ, IRQ, Supervisor, Abort, and

Undefined

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Banked Registers

R13

R14

R15

CPSR

R11

R12

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0

USER IRQFIQ Supervisor Abort Undefined

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x86

Basic Characteristics

I general register architectureI 16-/32-/64-bit wordsize (discussing 32-bit versions here)I numerous extensions/additions over the yearsI first released in 1978; 8086, 16-bit, based on 8008I 8086: registers dedicated to specific purposesI 8087: adds ft pt w/ stackI 80386 (1985): registers extended to 32-bits, 8 general

purpose; primarily 2-address, variable length instructions(lengths of 1-15 bytes), complex instr encoding

I Pentium/Pentium Pro add MMX (SIMD) instructions (1997)I some instructions have different behaviors in real/protected

modeI 3 operating modes: real, protected, virtualI condition codes

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The Motorola 68000

Basic Characteristics

I general register architecture

I 32-bit internal data path

I 16-bit external data path

I word accesses on word addresses only

I big-endian address alignment (word 0 ≡ byte 0)

I terminology: word 16-bits; longword 32-bits

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The Register Structure

I 32-bit PC

I 8 32-bit data registers D0–D7

I 8 32-bit address registers A0–A7

I A7 is a stack register

I A7 is really 2 distinct registers; one for user mode & one forsupervisor mode

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Instructions

I full compliment of addressing modesI opcode/operands are orthogonalI e.g., ADD instruction:

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Branching

I Short form:

I Long form:

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The HP 3000: A Stack Based Processor

Basic Characteristics

I stack in MM (some H/W buffers)I 16-bit wordsizeI 16-bit address busI one 16-bit index registerI one 16-bit status register

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The Memory Structure

I logically separate program/data spacesI program space has 3 associated CPU registers

I PB: program base, program starting pointI PL: program limit, end of programI PC: program counter

I data space divided into 2 parts: the stack area and thedata area.

I data space has 5 associated CPU registersI DB: data base, indicates start of stackI SP: stack pointerI SL: stack limit, bounds the total stack sizeI DL: data limit limit, bounds on the static data areaI Q: stack marker (activation record)

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The Program and Data Spaces

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The Q Register

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Instructions

I instruction formatI 16-bit lengthI typical memory instruction (Load/Store)

I typical stack instruction

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Addressing Modes

Mode bits 9-0 Effective AddrPC+ 00dddddddd [PC]+ddddddddPC- 01dddddddd [PC]-ddddddddDB+ 10dddddddd [DB]+ddddddddQ+ 110ddddddd [Q]+dddddddQ- 1110dddddd [Q]-ddddddSP- 1111dddddd [SP]-dddddd

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