cascaded channel model, analysis, and hybrid decoding for
TRANSCRIPT
1/16
Kui Cai1, K.A.S Immink2, and Zhen Mei1
Advanced Coding and Signal Processing Lab 1Singapore University of Technology and Design (SUTD)
2Turing Machine Corporation, Netherlands
Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer
Magnetic Random Access Memory (STT-MRAM)
9TH ANNUAL NON-VOLATILE MEMORIES WORKSHOP, UCSD, MARCH 2018
2/16
Introduction of STT-MRAM
A promising emerging non-volatile memory (NVM) technology – Non-volatility
– High endurance
– Good scalability
– High write/read speed
– Low power consumption
‘1->0’ ‘0->1’
magnetic tunneling junction (MTJ)
3/16
Major Technical Challenges
Process variation & thermal fluctuation result in the simultaneous existence of 3 types of errors
Write errors – Process variation induced variation of the MTJ geometry and
nMOS transistor size
=> widened distribution of the switching current
threshold & variation of the transistor driving current
– Thermal fluctuation => switching is probabilistic
– The write error rate for 0->1 switching (P1), is much higher than that for 1->0 switching (P0)
Read disturb errors – Accidental flipping of MTJ during read (Pr)
– Caused by a large read current due to process variation or thermal fluctuation
Read decision errors – Fail to differentiate the two resistance states due to widened
resistance distributions
– Caused by process variation induced variations of the tunneling oxide thickness and cross-section area, the tunneling oxide imperfection and the interfacial scattering effect
MTJ switching current
pro
ba
bility d
ensity f
unction
Block schematic of MTJ switching current distribution
4/16
Modeling of STT-MRAM
Memory physics based modeling [1]
– Modeling of switching current distributions
• Analytical approach to compute Jc using macrospin model
• Statistical approach to compute MTJ switching current distributions
– Modeling of magnetization dynamical switching using LLG equations
• Switching current vs switching time
– Modeling of NMOS transistors
• Generates MTJ driving current distributions for given NMOS parameters at a specific technology node
– Modeling of static resistance distributions
• Statistical model to estimate distributions due to parametric variations
• Quantum tunneling model: interface imperfections; oxygen vacancy defects in MgO
Memory circuit level modeling – Compact models [2]
[1] B. Chen, K. Cai, G.C. Han, S.T. Lim, and M. Tran, “A portable dynamic switching model for perpendicular magnetic tunnel junctions considering both thermal and process variations”, IEEE Trans. Magnetic, vol. 51, no. 11, Article #:1300704, Nov. 2015. [2] W. Guo et al., “SPICE modelling of magnetic tunnel junctions written by spin-transfer torque,” J. Phys. D, Appl. Phys., vol. 43, no. 21, pp. 215001-1–215001-8, 2010.
5/16
We propose a new class of binary-input, asymmetric, and memoryless channel model, the cascaded binary asymmetric channel (BAC) and Gaussian mixture channel (GMC) model [3]
– A communication type of channel model
The combined model of the write error and read disturb error
[3] K. Cai and K.A.S Immink, “Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM),” IEEE Trans. Magnetics, vol. 53, no. 11, Article #:8204311, Nov. 2017.
The Cascaded BAC and GMC Channel Model
6/16
The Cascaded BAC and GMC Channel Model
Cascaded Binary Asymmetric Channel (BAC) and Gaussian Mixture Channel (GMC) Model
Significantly improves the memory array error rate simulation speed
Facilitates the theoretical design and analysis of the memory sensing and error correction
coding schemes for STT-MRAM
7/16
Channel raw bit error rate (BER) analysis
Channel Raw Bit Error Rate (BER)
Dominant error events distributions
9/16
The Maximum Likelihood (ML) Decision Criterion
Optimum decoding for the cascaded BAC-GMC channel
10/16
Extended Hamming Codes with Hybrid Decoding
The state of the art ECCs for STT-MRAM – Everspin’s 16Mb MRAM: (71, 64) Hamming code [4]
– TDK-Headway’s 8Mb STT-MRAM test chip (2017): 2-bit ECC [5]
As an example, we adopt an extended Hamming code
– (72, 64) extended Hamming code
We first propose a modified Chase decoder with ML metric for STT-MRAM
We further present a two-stage hybrid decoder
Successful error
correction? Yes
No
Hard decision-decoding
Modified Chase decoding
Exit
[4] https://www.everspin.com/file/162/download
[5] http://hobbydocbox.com/Radio/66149727-Basic-principles-challenges-and-opportunities-of-stt-mram-for-embedded-memory-applications.html
11/16
• Chase decoder with ML metric
performs significantly better than
both the hard-decision decoder
(HDD) and Chase decoder with the
conventional metric
• The two-stage hybrid decoder
achieves similar performance with
the full Chase decoder
• The (72, 64) code with hybrid
decoding performs significantly
better than (71, 64) code with
hybrid decoding
• The hybrid decoder can greatly
improve the system’s tolerance to
the process variation (2% more), in
the presence of write errors 8 9 10 11 12 13 14 15 16
10-5
10-4
10-3
10-2
10-1
100
0/
0 (%)
FE
R
P1=110-4
1 w/o ECC
2 (71,64) code, HDD
3 (71, 64) code, Chase, Cascaded ML metric
4 (71, 64) code, Hybrid
5 (72, 64) code, HDD
6 (72, 64) code, Chase, SED metric
7 (72, 64) code, Chase, GMC ML metric
8 (72, 64) code, Chase, Cascaded ML metric
9 (72, 64) code, Hybrid
Simulation Results
12/16
10-6
10-5
10-4
10-3
10-2
10-5
10-4
10-3
10-2
10-1
100
P1
FE
R
1 w/o ECC
2 (71,64) code, HDD
3 (71, 64) code, Chase, BAC-GMC ML metric
4 (71, 64) code, Hybrid
5 (72, 64) code, HDD
6 (72, 64) code, Chase, SED metric
7 (72, 64) code, Chase, GMC ML metric
8 (72, 64) code, Chase, BAC-GMC ML metric
9 (72, 64) code, Hybrid
Simulation Results (contd.)
• There is a high error floor at
FER = 4×10-4, for the HDDs of both
the (71,64) code and (72, 64) code.
This means the system will never
work with the HDD, no matter how
small the write error rate P1 is
• The hybrid decoder of the (71, 64)
code only slightly lower the error
floor.
• The (72, 64) code with hybrid
decoding overcomes the high error
floor with the HDD, and improves
the maximum affordable write error
rate
• The hybrid decoder can greatly
improve the system tolerance to the
write errors, irrespective of the
resistance spread.
13/16
Decoding Latency Analysis
• The decoding latency of the hybrid decoder is just 0.11% higher than the hard-decision decoder
Computational complexity analysis of the full-Chase decoder
Latency of the hybrid decoder
14/16
Conclusions
We have proposed the cascaded BAC-GMC model, a new communication type of channel model for STT-MRAM – To significantly improve the memory array error rate simulation speed
– To facilitate the theoretical design and analysis of the memory sensing and error correction coding schemes for STT-MRAM
We have derived for the cascaded BAC-GMC channel – The channel raw BERs
– The bit LLR
– The ML decision criterion
As an example, we present a hybrid decoding algorithm for extended Hamming codes for the cascaded channel – The hybrid decoding algorithm can significantly improve the system’s tolerance to
both the write errors and the read errors, with little increase of the decoding latency over the HDD
– It can also be directly applied to other extended BCH codes, for the applications of NVMs with relaxed requirement on the decoding latency
15/16
Subsequent Work
“Polar coding for STT-MRAM”
– Accepted by Intermag 2018
“Dynamic threshold detection based on pearson
distance detection”
– Accepted by IEEE Trans. Commun.