Cadence Verilog Simulation Guide and Tutorial

PART IECE 4680 Computer Architecture

Fall 2005

Outline

Introduction Setting up the environment Compilation Elaboration Simulation Examples LAB Exercises

Introduction

This guide describes, via a tutorial, how to set up the personal environment (paths and evnrionment variables), and simulate Verilog models using the Cadence tools.

This guide is presented in three sections: 1. How to set up your environment to view

the documents and run the simulator tools. 2. Executing the Verilog simulator. 3. How to visualize the simulation results.

Logging in Instructions Cadence tools can be accessed from these locations: Engg 2360, Engg 3350,

PC lab 2359 and 2351. 1.1 Logging in from a SPARC station Select one of the engineering UNIX servers like Egypt.eng.wayne.edu,

Kenya.eng.wayne.edu …At the login window type your WSU access ID followed by ENTER and then type your password followed by ENTER. If asked what interface to use we recommend you choose CDE. If you ever want to change your login "session" you may do so by selecting the OPTIONS button on the login window and choose a session listed in the Sessions Menu (CDE, OpenWindows).  

1.2 Logging in from a PC using EXCEED Log in the pc, then go to Start > Programs>Humming Bird>Exceed>Exceed (XDMCP-Broadcast), a hostname list will show up, select the host with host address started with ”141.217.200” from the list and click ok(most of the available host’s host name are country name). A login window will come out. After this, the procedure is the same as the above “Logging in from a SPARC station”.

Setting up the environment I. Modify your “ .cshrc ” file

Double click the text editor icon (as in figure below)

Open the file “.cshrc”(it is a hidden file, you just enter the file name under your home directory to open it), then do the following:

I. Find the following line:source /usr/local/etc/ALLSET II. comment out that line, i.e. put # sign in front, like this:#source /usr/local/etc/ALLSET III. add these line:source /opt/cds/setup_files/cds_setup Finally, source the .cshrc file(type ”source .cshrc”) or open a new

terminal. kenya% source .cshrc

Setting up the environment II.

In your $HOME directory, create the cadence directory.

kenya % cd $HOME

kenya % mkdir cadence

  Create verilog directory under cadence directory.

kenya % cd $HOME/cadence

kenya % mkdir verilog

kenya % cd verilog

Writing Verilog code

Setting up a new directory for the design – a 1-bit full addder

kenya % mkdir adder

kenya % cd adder

kenya % mkdir src

  Using a text editor, type your Verilog code.

Example – 4-bit Full Adder//** ******Full Adder ******************module fulladder(sum, c_out, x, y, c_in);output sum, c_out;input x, y, c_in;wire a, b, c;xor (a, x, y);xor (sum, a, c_in);and (b, x, y);and (c, a, c_in);or (c_out, c, b);endmodule//********* 4-Bit Adder **********************module FourBitAdder(sum, c_out, x, y, c_in);output [3:0] sum;output c_out;input [3:0] x, y;input c_in;wire c1, c2, c3;fulladder fa0(sum[0], c1, x[0], y[0], c_in);fulladder fa1(sum[1], c2, x[1], y[1], c1);fulladder fa2(sum[2], c3, x[2], y[2], c2);fulladder fa3(sum[3], c_out, x[3], y[3], c3);endmodule

Saved it as fulladder.v

Invoking NCLaunch Make sure you are at the $HOME/cadence/verilog directory. Do with the following command in a shell windows:

kenya % nclaunch & or

kenya % >nclaunch –new &

Single-Step and Multi-Step Modes

NC-Launch allows you to invoke NC-Sim in one of two modes Multi-Step mode allows you to compile source files, elaborate

design units, and simulate snapshots, for Verilog, VHDL, and mixed-language designs. This gives you greatest control and flexibility to specify simulation options and features.

Single-Step mode calls NC-Verilog to compile and simulate your design in a signal invocation. For designs entirely written in Verilog, this provides an easy way to select NCVerilog options graphically and run simulation.

Choose MultiStep

Components of NCLaunch I.

Menu Bar

Toolbar Icons

Design AreaFile Browser

Console Window

NCLaunch command opens up the NCLaunch graphical user interface (GUI) main window. The main window(NCL window) is composed of a menu bar, toolbar icon strip, file browser, design area and console window as shown in the figure below.

Components of NCLaunch II.

The main NCLaunch window is divided into the following components:

Menu Bar and Tool Bar--Provide the commands and fast action buttons that let you manipulate design elements and start the various tools.

File Browser--The pane on the left side of the window displays the files in the file system.

Design Area--The pane on the right side of the window displays objects in the libraries.

Console Window--Displays output from tools, and allows you to input commands.

Toobar Icons

a. Edit File. By selecting a file and clicking this icon, a text editor (defined in your Preferences) appears with the files contents to review or modify.b. Refresh. Updates your browsers with any changes.c. Compile VHDL Files (multi-step only). Compiles selected VHDL files that will appear as design units under your work library in the Library Browser.d. Compile Verilog Files (multi-step only). Compiles selected Verilog files that will appear as design units under your work library in the Library Browser.e. Elaborate Files (multi-step only). By selecting the top level design unit and clicking this icon, your design will be elaborated.f. Run Simulation. Starts a simulation of your selected design.g. Browse Logfiles. Launches the NCBrowse message browser to analyze selected log files.h. Waveform Viewer. Starts a session of the waveform viewer tool with selected database files.

a b c d e f g h

Compile the Verilog code.

Select your Verilog source file fulladder.v from File Browser area To invoke Verilog compiler

Select NCLaunch->Tools -> Verilog Compiler --- click OK button. The results of the compilation appear in the Console Window of the NCLaunch window. After the source files have been compiled, you can click the plus sign (+) to the left of worklib in the Design Area. This expands the library and lists the Verilog design units that you have compiled. If there is no error reported, go to the next step; otherwise, read the error messages and fix your Verilog codes accordingly. Then, recompile the code again until there is no error.

Elaborating the Design After compiling the Verilog source code, you must elaborate the

design using a program called NCELAB. The elaboration process constructs a design hierarchy based on the instantiation and configuration information in the design, establishes signal connectivity, and computes initial values for all objects in the design. This design hierarchy is stored in a simulation snapshot. The snapshot is the representation of your design that the simulator uses to run the simulation.

To elaborate the design: Click the plus sign to the left of the worklib library in the Library

Browser to expand it. Expand the adder design unit.

Select the top-level design unit. Select NCLaunch -> Tools -> Elaborator

Creating the Testbench for 4-bit Full Addermodule testbed();reg c_in;reg [3:0] y;reg [3:0] x;wire c_out;wire [3:0]sum;FourBitAdder A1(sum, c_out, x, y, c_in);Initialbeginx = 4'b0001; y = 4'b0001; c_in = 1'b0;#25 x = 4'b0001; y = 4'b0010;#25 x = 4'b0010; y = 4'b0011;#25 x = 4'b0001; y = 4'b1111;#25 x = 4'b0001; y = 4'b1111; c_in = 1'b1;#25 x = 4'b1000; y = 4'b1111; c_in = 1'b0;#25 x = 4'b0001; y = 4'b0001; c_in = 1'b1;#25 x = 4'b0001; y = 4'b0010;#25 x = 4'b0010; y = 4'b0011;#25 x = 4'b0011; y = 4'b1111;#25;endinitial#250 $finish;endmodule

• Saved the testbench as fulladder_test.v

• Repeat the above steps to compile and elaborate fulladder_test

Simulation with NcSim Loading the Snapshot into the Simulator Design Area, in the snapshot folder, select the testbench file,

worklib.fulladdertest:module Select ->(NCLaunch)Tools > Simulator The simulator window(NC Verilog window) will show up:

Components of NCSim The window is divided into the following sections: The Menu Bar, which contains the pulldown menus that let you execute

simulator commands. The Tool Bar, which contains buttons that give you fast access to

commonly used commands and to the other SimVision tools. The Source Browser, which displays your source code. You can select

scopes, signals, or ports in the Source Browser and operate on them. The Scope Region, which displays the current scope and lets you quickly

set the scope to another level in the hierarchy. The Input/Output Region, which displays simulator output and lets you

give command-line input to the simulator. The Message Region, which displays information about the menu item or

button where the mouse pointer is pointing.

Viewing Signals in SignalScan Waveform Viewer

You will now select signals that you want to probe to a database and display in the Signalscan waves waveform viewer.

NCVerilog-> Select > Signals from the menu of the simulator.

To invoke the Signal scan click on the button

in the upper right corner of NCVerilog window.

Simulate the design • To simulate, click the Run Simulation button on the NCVerilog window or select Run ->Continue

•The below is the output of the waveform

LAB

1.Run the example throughout. 2. Modify the 4-bit Full Adder to a 8-bit Full

Adder and create the corresponding test bench

3.Show the waveform to TA 4.Send your 8-bit Full Adder Verilog and test

programs as attachments by email to ai5998@wayne.edu e.g. Subject: Lab2 and your Last name

Reference 1. Cadence VHDL/Verilog Simulation Guide and T

utorial 2. ECE7530 Lab Handouts