CAD Algorithms and Tools

Overview• Introduction

• Multi-level logic synthesis• SIS as a representative CAD tool

• Boolean networks

• Transformations of Boolean networks• sweep, eliminate, fast_extract, resub, full_simplify

• Optimization loop

• Implementation • network/node data structure, packages, scripts

• Conclusions

• Software demo

Introduction

• Multi-level logic synthesis• Description, motivation, results

• Logic synthesis methods• In the past, applied by hand; now, by the

tools

• CAD tools• Experimental, industrial

SISSIS• The first comprehensive open-source logic synthesis

tool

• Based on a decade of research at UC Berkeley and other universities (1983-1993)

• Precursor of many modern CAD tools

• Gives a good idea what is inside those tools

• Source code, benchmarks available on-line:

http://www-cad.eecs.berkeley.edu/Software/software.html

• Boolean network is a direct acyclic graph

Primary inputs (PIs)

Primary outputs (POs)

Internal nodes

Boolean NetworksBoolean Networks

Fanin/Fanout of a Node• Node has only one output. • Node can have any number of inputs (fanins)

• and can be an input to any number of nodes (fanouts)

N

FO1 FO2 FO3

FI1 FI2 FI3

Fanouts

Node

Fanins

Transitive Fanin/Fanout of a Node

NTransitive fanin

Transitive fanout

Factoring

F = a’c + a’d + bc + bd + e F = (a’+b)(c+d) + e

Optimizing Transformations Optimizing Transformations on Boolean Networkson Boolean Networks

Common logic extraction

F = (a + b)cd + e F = XY + eG = (a + b)e’ G = Xe’H = cde H = Ye X = a + b Y = cd

F G H F G H

X Y

Resubstitution

G = a + b + c G = a + b + c

F = a + bd + cd F = G(a+d)

F

G

F

G

Elimination

G = a + b + c G = a + b + cF = G(a+d) F = a + bd +

cd

F

G

F

G

Sweep

(1)Removes nodes that do not fanout

(2)Eliminates constant nodes and single-input nodes (buffers, inverters)

full_simplify

• Simplifies each node in the network using don’t-cares

Don’t-cares for Nodes in Don’t-cares for Nodes in the Networkthe Network

• External don’t-cares

• Some input combinations never occur (unused codes, unreachable states)

• Internal don’t-cares

• Satisfiability don’t-cares• Some input combinations never occur at a node

• Observability don’t-cares

• Under some input combinations, the value produced at the output of the node does not matter

Satisfiability Don’t-cares

• (x,y)=(1,0) is a don’t-care for node F

a

b

c

F z1

x

y

Observability Don’t-Cares

• (a,c)=(1,1) is a don’t-care for node F

a

b

c

F

z1

z2

node_structstruct node_struct {

char *name; /* name of the output signal */ char *short_name; /* short name for interactive use */

node_type_t type; /* type of the node */

int sis_id; /* unique id (used to sort fanin) */

unsigned fanin_changed:1; /* flag to catch fanin generation errors */ unsigned fanout_changed:1; /* flag to catch fanout generation errors

*/ unsigned is_dup_free:1; /* node has no aliasing of its fanin */ unsigned is_min_base:1; /* node is minimum base */ unsigned is_scc_minimal:1; /* node is scc-minimal */

Structure of a node

Role of sophisticated representations, Role of sophisticated representations, data structures and algorithms.data structures and algorithms.

node_struct (continued) int nin; /* number of inputs */ node_t **fanin; /* the array of pointers to the input nodes */

lsList fanout; /* list of 'fanout_t' structures */ lsHandle *fanin_fanout; /* handles of our fanin's fanout_t structure */

pset_family F; /* on-set */ pset_family D; /* dc-set -- currently unused */ pset_family R; /* off-set */

node_t *copy; /* used by network_dup(), network_append() */

network_t *network; /* network this node belongs to */ lsHandle net_handle; /* handle inside of network nodelist */};

network_structstruct network_struct { char *net_name; /* the name of the network */ st_table *name_table; /* table to hash names into node pointers

*/ st_table *short_name_table; /* table to hash names into node pointers

*/

lsList nodes; /* list of all nodes */ lsList pi; /* list of just primary inputs */ lsList po; /* list of just primary outputs */ network_t *dc_network; /* external don't care network */

st_table *latch_table; /* table to hash names into latch pointers */

lsList latch; /* the linked list of latches */ graph_t *stg; /* state transition graph */ char *clock; /* the clock */

char *default_delay; /* stores default delay info */ astg_t *astg; /* asynchronous signal transition graph */};

Structure of a network

script.rugged

sweep; eliminate -1simplify -m nocompeliminate -1

sweep; eliminate 5simplify -m nocompresub -a

fxresub -a; sweep

eliminate -1; sweepfull_simplify -m nocomp

Scripts to control the synthesis process

Role of scripting and user-directed Role of scripting and user-directed synthesissynthesis

What’s next?

• Multi-valued logic optimization– New CAD tool: MVSIS

• Reversible logic synthesis

• Quantum, DNA-based, etc

full_simplify SIS vs. MVSIS

Statistics Literals in FF Runtime Benchmark

Ins Outs Orig SIS MVSIS SIS MVSIS

9symml.blif 9 1 277 270 226 1.20 1.9 alu2.blif 10 6 453 374 312 1.89 12.0 alu4.blif 14 8 855 t/o 738 t/o 24.6 dalu.blif 75 16 3067 2331 1707 145.9 14.2 des.blif 256 245 6101 5677 4621 16.2 300.0 frg2.blif 143 139 2010 1522 1415 9.5 21.3 pair.blif 173 137 2420 2203 2140 6.5 59.3

c1908.blif 33 25 1497 1406 771 68.1 204.0 c432.blif 36 7 372 335 291 4.6 6.0 c880.blif 60 26 703 687 630 2.34 23.3

Total 16900 14805 12113 256 642 Ratio, % 100 88 72 100 251

Conclusions

• Reviewed multi-level logic optimization

• Introduced Boolean networks

• Considered typical operations

• Looked into the implementation of SIS

Problems for studentsProblems for students• What are BDDs and how are they used.

• Shannon expansion and its role in trees and diagrams

• Boolean networks• Operations on Boolean Networks.

• Various types of don’t cares and their use

• SIS system in practice.

Sources

Alan Mishchenko

Electrical and Computer EngineeringPortland State University