burr-brown spice based macromodels - ti.com corporation pspice ® parts™ simulation software. ......

APPLICATION BULLETIN®

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INTRODUCTIONComputer based simulation has an importance because it cansignificantly reduce the development time and thereforespeed up the time-to-market process. The increased use ofSPICE based simulation software has created a rising de-mand for accurate models. Such models, or macromodels,should reflect the actual performance of the component, butwithout carrying the burden of too many circuit details,which can lead to convergence problems. BURR-BROWNhas responded to this need and provides macromodels for abroad range of semiconductor products. This ApplicationBulletin, and the accompanying disk is a collection ofSPICE models of BURR-BROWN op amps, differenceamps, instrumentation amps, isolation amps, and analogfunction circuits. There are four different levels of modeltopologies used, which are:

Level I: Standard Macromodel

Level II: Enhanced Macromodel

Level III: Multi-Pole/Zero Macromodel

Level IV: Simplified Circuit Model

• The standard op amp macromodels were derived using theMicroSim Corporation PSpice® Parts™ simulation software.A detailed description on this macromodel type is given inSection A.

• The second level of macromodel is an enhanced version ofthe standard model, which is indicated by the suffix “E” inthe model’s name. This model type is included to offer thecircuit designer a model with a higher level of accuracy. SeeSection B for details.

• The Multiple-Pole/Zero macromodel uses the same inputstage as the standard or enhanced op amp macromodel, buthas multiple poles and pole/zero pairs in the mid-section.This model has the designation “M”, and was used forwide bandwidth op amps and function circuits where thistopology showed an advantage over the standard topology.For a detailed description see Section C.

• In some instances, a fourth type of model is available,which are designated by either an “X”, “X1”, or an “X2”suffix. The model of this level is not a macromodel, butrather a simplified circuit model at the transistor level. The

BURR-BROWNSPICE BASED MACROMODELS, REV. F

By Hubert Biagi, R. Mark Stitt, Bonnie Baker, and Stephan Baier

©1990 Burr-Brown Corporation AB-020F Printed in U.S.A. January, 1995

FILE NAME DESCRIPTION

OPA111.MOD OPA111 Standard Op Amp MacromodelOPA111E.MOD OPA111 Enhanced Op Amp MacromodelOPA671M.MOD OPA671 Multiple Pole/Zero MacromodelOPA603X.MOD OPA603 Simplified Circuit Model

TABLE I. Examples of Files on Macromodel Disk.

simplified circuit models produce the most accurate simula-tion results, but because of the complexity, require longersimulation time. See Section D for a detailed discussion onthese models.

For a complete overview of all available macromodels onthe disk see Table XI on the last page.

DISKETTE INFORMATION

The disk has four different subdirectories, in which themodels are organized according to their topology level:

A:\

CIR_MODENH_MODMPZ_MODSTD_MOD

Here, the Standard macromodels (Level I) are found in theSTD_MOD subdirectory. The Enhanced macromodels(Level II) are found in the ENH_MOD subdirectory. TheMulti-Pole/Zero macromodels (Level III) are found in theMPZ_MOD subdirectory, and the Simplified circuit models(Level IV) are found in the CIR_MOD subdirectory. Ex-amples of model files are shown in Table I. This applicationbulletin and the macromodel disk are being revised fre-quently. To obtain the latest revision please contact yournearest sales office. Each model net-list starts with a headercontaining the part number, revision information, and thelicense statement. It should be noted that the disk containsonly the net-lists of the macromodels, and does not providethe simulation software that allows the user to run themodels. The structure of the net-lists conforms to the stan-dard SPICE format, which most SPICE based simulatorswill accept. Please refer to the individual software manual ifconflicts are encountered. Burr-Brown also welcomes anycomments, which may be sent to the Applications Depart-ment at the address given above.

PSpice® PartsTM, MicroSim Corp.

SBFA009

2

GENERAL INFORMATIONThroughout this application bulletin and the net-lists of themacromodels, standard definitions and designators are used.As a reference they are listed in the following tables. TableII and Table III specifically refer to the Standard and theEnhanced macromodel only. Listed in Table IV are thedefinitions for all used component prefixes.

TABLE II. Op Amp Macromodel Components for theStandard and Enhanced Macromodels.

TABLE III. PSpice Parts Inputs for Standard andEnhanced Marcomodels.

BURR-BROWN MACROMODELSYMBOL DESIGNATION DEFINITION

V+, V– +VPWR

, –VPWR

Positive, Negative Power Supply+VOUT, –VOUT Max Positive, Negative Output

SwingSR+ +SR Positive-Going Slew RateSR

––SR Negative-Going Slew RatePd Quiescent Power Dissipation

IB

IB

Input Bias CurrentAOL Av–dc DC Open-Loop Voltage GainUGBW F–0dB Unity-Gain FrequencyCMRR CMRR Common-Mode Rejection Ratioø

MPhi Phase Margin at F-0dB (°)

rO Ro-dc DC Output Resistancez

ORo-ac AC Output Resistance

ISC Ios Short-Circuit Output CurrentC

CCc Compensation Capacitance

COMPONENT DESCRIPTION

C1

Phase-Control CapacitorC2 Compensation CapacitorC

EE, C

SSSlew-Rate Limiting Capacitor

DP Substrate JunctionE

GNDVoltage-Controlled Voltage Source

FB Output Device (Controlled by the Current Through VB, V

C, V

E, and V

LP, V

LN)

G11,G21 Input Bias Current CorrectionG

AInterstage Transconductance (Controlled by Differential Voltage at the Input Device Loads)

GCM

Common-Mode Transconductance (Controlled by the Common-Mode Voltage at the Input Device Emitters or Sources)

IEE, ISS Input Stage CurrentH

LIMVoltage-Limiting Device

J1, J2 JFET Input TransistorsQ

1, Q

2Bipolar Input Transistors

R2 Interstage ResistanceR

C1, R

C2Input-Stage Load Resistance

RD1, RD2 Input-Stage Load ResistanceR

E1, R

E2Input-Stage Emitter Resistance

REE, RSS Input-Stage Current-Source Output ResistanceR

O1, R

O2Output Resistors

RP Power Dissipation ResistorV

BIndependent Voltage Source

VC, DC Output Offset Limiter (to V+)V

E, D

EOutput Offset Limiter (to V–)

VLIM Output Current Limiting SensorV

LN, D

LNNegative Supply Limit

VLP, DLP Positive Supply Limit

PREFIX DEFINITION

C CapacitorD DiodeE Voltage-Controlled Voltage SourceF Current-Controlled Current SourceG Voltage-Controlled Current SourceH Current-Controlled Voltage SourceI Independent Current Source or StimulusJ JFET TransistorQ Bipolar TransistorR ResistorS Voltage-Controlled SwitchV Independent Voltage Source or Stimulus

TABLE IV. Macromodel Component Prefix Definitions.

LIMITATIONS

These macromodels are intended to help designers simulatetypical amplifier performance. The macromodels were com-piled using data sheet typical specifications. Where datasheet specifications were not available, typical measuredvalues or design values were used. Macromodels wereverified with several standard simulations such as gain-phase and large- and small-signal transient response. Insome cases, adjustments were made to the macromodels sosimulations with the macromodel more closely agreed withactual measured typical performance.

Since these macromodels only simulate the typical perfor-mance of certain selected specifications, they will not pre-dict actual device performance under all conditions. Gooddesign practice dictates that, in addition to simulation withmacromodels, circuit verification must include:

1) worst case analysis with data sheet minimum and maxi-mum room temperature specifications

2) worst case analysis with variation of specifications overthe operating temperature range

3) thorough breadboard evaluation

4) complete prototype characterization

DUAL AND QUAD OP AMPS

All op amps are modeled as single devices. To model dualsor quads, use two or four models. Quiescent current for thedual or quad op amp macromodel is the dual or quad op ampquiescent current divided by two or four.

INSTRUMENTATION AMPLIFIERSAND DIFFERENCE AMPLIFIERS

Instrumentation amplifier and difference amplifiermacromodels use standard op amp macromodels plus addi-tional components as shown in Figures 1 and 2. There aretwo types of models used for difference amplifiers. They arethe four-resistor difference amplifier and the five-resistordifference amplifier.

FOUR-RESISTOR DIFFERENCE AMPLIFIER

The four-resistor difference amplifier macromodel, used forthe INA105, INA106, and the difference amplifier section inall instrumentation amplifier macromodels, is shown in

3

Figure 1a. The circuit uses an op amp and four matchedresistors. If R2/R1 = R4/R3, GAIN = R2/R1 and CMR = ∞. Tosimulate DC CMR error, R

2 is set 0.01% low. CMR for a

four resistor difference amplifier is:

CMR = –20 LOG10 [(%/100) • R1/(R

1 + R

2)]

Where: % = % error in any resistor.

With a 0.01% resistor error, DC CMR for the INA105 unitygain difference amplifier is 86dB, and DC CMR for theINA106 gain-of-ten difference amplifier is 100.8dB.

To simulate AC CMR error, a small value capacitor, C2, is

placed in parallel with R2 to roll-off of CMR with increasingfrequency.

FIGURE 1a. Difference Amp Macromodel and Node Assign-ments.

FIVE-RESISTOR DIFFERENCE AMPLIFIER

The five-resistor difference amplifier macromodel used forthe INA117 is shown in Figure 4b. The advantage of thefive-resistor difference amplifier configuration is a boost ininput common-mode-voltage range for a given op ampcommon-mode range. The circuit uses an op amp and fivematched resistors. If (R2 || R5)/R1 = R4/R3, GAIN = R2/R1 andCMR = ∞. To simulate DC CMR error, R

4 is set 0.005%

low. For errors in R4, the CMR for a five-resistor difference

amplifier is;

CMR = –20 LOG10 [(%/100) • R1/(R

1 + R

4)]

Where:% = % error in R

4

R2 || R5 = R2 • R5/(R2 + R5)

With a 0.005% resistor error, DC CMR for the INA117 highcommon-mode-voltage unity-gain difference amplifier is86.5dB. Note that unlike the four resistor difference ampli-fier, the sensitivity of DC CMR to errors in resistor value isdifferent for different resistors.

To simulate AC CMR error, a small value capacitor, C2, is

placed in parallel with R2 to roll-off of CMR with increasing

frequency.

13

14

–In

+In

5VO

3

V+

4

V–

R1

R3

2

1Ref

R2

R48

C2

A3

R5

9Ref B

Ref A

FIGURE 1b. INA117 High Voltage Difference AmplifierMacromodel and Node Assignments.

13

14

5VO

R1

R3

11

12Ref

R2

R48

C2

A3

4

V–

A2

3

V+

A1

RFB1

RFB2

9

10

1+In

2–In

RG

RG1

RG2

CC1

CC2

FIGURE 2. Standard Instrumentation Amplifier Macromodeland Node Assignments.

FIGURE DESCRIPTION

1a Difference Amp Macromodel Node Assignments1b INA117 Difference Amplifier Macromodel2 Instrumentation Amp Macromodel Node Assignments3 INA103 Macromodel and Node Assignments4 INA118 Macromodel and Node Assignments5 INA110 Macromodel and Node Assignments6 INA120 Internal Gain Setting Resistor Connections

TABLE V. Figure Reference.

13

14

–In

+In

5VO

3

V+

4

V–

R1

R3

2

1

Sense

Ref

R2

R48

9

C2

A3

4

FIGURE 3. INA103 Current-Feedback Instrumentation Amplifier Macromodel and Node Assignments.

13

14

5VO

R1

R3

11

12

Ref

R2

R48

C2

A3

4

V–

A2

3

V+

A1

RFB1

RFB2RG

RG1

RG2

Q2Q1

+In

–In1

2

I2I1

I4I3

1716

CC1

CC2

+V1

15

RCE

10

9

D1

D2

FIGURE 4. INA118 Instrumentation Amplifier Macromodel and Node Assignments.

13

14

5VO

R1

R3

11

12

Ref

R2

R48

C2

A3

4

(V–)

A2

3

V+

A1

RFB1

RFB2RG

RG1

RG2

Q2Q1

+In

–In1

2

I2

IB2

IB1

I1

1716

CC1

CC2

+V1

15

RCE

10

9

D1

D2

CG1 CG2

GND

IBAL0

5

13

14

5VO

R1

R3

11

12Ref

R2

R4

8

C2

A3

4

V–

A2

3

V+

A1

RFB1

RFB2

RG

RG1

RG2

Q2Q1

+In

–In1

2

I2I1

I4I3

17

16

CC1

CC2

I6I5

22

21

J2J1

CG2CG1

C4

RCE

D1

D2

+V1

15

10

9

FIGURE 6. INA120 Internal Gain-Setting Resistor Connections.

FIGURE 5. INA110 Current-Feedback FET-Input Instrumentation Amplifier Macromodel and Node Assignments.

VO

R1

R3

Ref

R2

R4

A3

V–

A2

V+

A1

RFB

RFB

+In

–In

2kΩ

44Ω

400Ω

2kΩ

G8

G9

G10

G5

G11

G14

G15

20kΩ

20kΩ

G4

INA120 INTERNAL GAIN CONNECTIONS (1)

GAIN CONNECT

1 G4-G5 G14-G1510 G4-G5 G11-G14-G15100 G4-G8 G11-G14 G10-G151000 G4-G8 G11-G14 G9-G15

NOTE: (1) "G" numbers are also package pin numbers.

6

SECTION A:STANDARD MACROMODELSThe standard op amp macromodels were created by runningthe PSpice® Parts™ Simulation software on an IBM-com-patible PC. This software uses the standard Boyle op ampmodel(1). The PSpice manual available from Microsim(2)

contains a detailed discussion of each of the elements usedin the macromodels.

Op amp macromodels use the node assignments shown inFigures A1 to A6. The FET-input amplifiers using the stan-dard PSpice Parts topology are shown in Figures A3 and A4.

The node assignments for the standard PSpice Part op ampmacromodels with bipolar-inputs are shown in Figures A5and A6. Figure A1 shows the external op amp node assign-ments. Tables II, III and IV list component prefix designa-tions, macromodel component descriptions, and PSpice IN-PUT designations used for the standard and enhanced mod-els. The parameters that are modelled by the standardmacromodels are listed in Table X.

FIGURE A1. Node Assignments for Standard and EnhancedOp Amp Macromodels.

2

1

–In

+In

5VO

3

V+

4

V–

FIGURE DESCRIPTION

A1 Op Amp Node AssignmentsA2 OPTxxx Node AssignmentsA3 N-Channel JFET-Input Op AmpA4 P-Channel JFET-Input Op AmpA5 NPN Bipolar-Input Op AmpA6 PNP Bipolar-Input Op Amp

TABLE VI. Standard Macromodels Figure Reference.

(1) For more information, see: G.R. Boyle, B.M. Cohn, D.O. Pederson, and J.E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journalof Solid-State Circuits, SC-9, 353 (1974).

(2) MicroSim Corporation, 20 Fairbanks, Irvine, CA 92718 USA, (714) 770-3022, (800) 245-3022.

FIGURE A3. N-Channel JFET-Input Op Amp Standard PSpice Parts Macromodel.

NOTE: (1) Use Boyle model illustrated in Figure A4.

FIGURE A2. OPT–Standard Macromodel.

+In

+

V+

VO

V–

RD1 RD2

J2J1–In

1

2

RP DP VC

DC

+VE

DE

4

5

3

53

54

GCM GAR2

C2

6

9 +VB

RO1

+EGND

FB

7 +VLIM

8

RO2

RSS CSS

99

ISS

10

C1

11 12

DLN

DLP

+

+

91

92VLN

VLP

+

HLIM

90

ROUT

5

1

RFB

CFB

A1(1)

4

3

CPHOTORPHOTODPHOTO

2

8

V+

V–

VO

See Table II, for amore detaileddescription of thecomponents.

7

FIGURE A4. N-Channel JFET-Input Op Amp Standard PSpice Parts Macromodel.

FIGURE A5. NPN-Input Op Amp Standard PSpice Parts Macromodel.

–In

+

V+

VO

V–

RC2 RC2

Q2Q1

+In1

DPRP VC

DC

+VE

DE

4

5

3

53

54

GCM GAR2

C2

6

9+

VB

RO1

FB

7 +VLIM

8

RO2

REE

CEE

99

IEE

10

C1

11 12

DLN

DLP

+

+

91

92VLN

VLP

+

HLIM

90

+EGND

2

RE1 RE2

13 14

See Table II, for a more detaileddescription of the components.

FIGURE A6. PNP-Input Op Amp Standard PSpice Parts Macromodel.

+In

+V+

VO

V–

RC1 RC2

Q2Q1–In

1

2

RP DP VC

DC

+VE

DE

4

5

3

53

54

GCM GAR2

C2

6

9+

VB

RO1

+EGND

FB

7 +

VLIM

8

RO2

REE CEE

99

IEE

10

C1

11 12

DLN

DLP

+

+

91

92VLN

VLP

+

HLIM

90

RE1 RE2

1413


–In

+

V+

VO

V–

RD1 RD2

J2J1

+In1

DPRP VC

DC

+VE

DE

4

5

3

53

54

GCM GAR2

C2

6

9+

VB

RO1

FB

7 +VLIM

8

RO2

RSS

CSS

99

ISS

10

C1

11 12

DLN

DLP

+

+

91

92VLN

VLP

+

HLIM

90

+EGND

2


8

SECTION B:ENHANCED MACROMODELSThe enhanced version, “E”, of the standard PSpice Partsmodel contains several additional performance features. Allof the macromodels using this topology are in the ENH_MODsubdirectory on the disk. The FET-input amplifiers using thestandard PSpice Parts topology plus enhancements are shownin Figures B1 and B2. The node assignments for the en-hanced op amp macromodels with bipolar-inputs are shownin Figures B3 and B4. Figure A1 shows the external op ampnode assignments. Tables II, III, and IV list componentprefix designations, macromodel component descriptions,and PSpice INPUT designations used for the standard andenhanced models. The parameters that are modelled by theenhanced macromodels are listed in Table X. Additions andchanges to the standard PSpice Parts macromodel to theenhanced version are discussed in the following text.

TABLE VII. Enhanced Macromodels Figure Reference.


FIGURE B1. N-Channel JFET-Input Op Amp Enhanced PSpice Parts Macromodel.

FIGURE DESCRIPTION

B1 N-Channel JFET-Input Op AmpB2 P-Channel JFET-Input Op AmpB3 NPN Bipolar-Input Op AmpB4 PNP Bipolar-Input Op AmpB5 OPA27/37 Input ProtectionB6 OPA77/177 Input ProtectionB7 INA114/118 Input Protection Circuitry

Input Current CorrectionOne feature that Burr-Brown offers with the enhanced modeltype is accurate simulation of input bias current for N-ChannelJFET and P-Channel JFET operational amplifiers. Math-ematically, the input bias current for JFET op amps shouldequal twice the IS of the JFET model. However, simulationwill show that the gate current from J1 and J2 in Figures A3through B2 is between 10 to 20pA larger than expected,depending on the common-mode voltage of the input stageand the magnitude of the supply voltages, if G11 and G21 arenot included in the model. This additional current is gener-ated from the drain-to-gate and source-to-gate nodes of theinput FETs of the operational amplifier, which manifestsitself as the bias current of the amplifier. The additionalcurrent is caused by the Spice default value, GMIN. In thiscase, 1/GMIN is the impedance between the drain and gateand the source and gate. This is done by Spice to keep thegate node of each FET from floating. The default value, orGMIN is 1E-12 . The voltage dependent current sources,G11 and G21 remove this error current from the model, hencethe macromodel models input bias current correctly. Thistechnique is used in all of the FET-enhanced and multiplepole/zero macromodels. To improve simula-tion accuracy the .OPTIONS statement should includeABSTOL = 100fA or 10fA.

NoiseMost of the enhanced JFET-input macromodels model de-vice current noise and voltage noise. The current noise ismodeled using RN1, RN2, RN3, RN4, RN5 and RN6 to create thenoise source and the voltage-dependent current sources, G11

and G21, to model the noise on the inverting and non-

CDIF

+V+

VO

V–

RD1 RD2

J2J1

RQDP VC

DC

+VE

DE

4

5

3

53

54

GCM GAR2

C2

6

9 +VB

RO1

+EGND

FB

7 +VLIM

8

RO2

RSS CSS

99

ISS

10

C1

11 12

DLN

DLP

+

+

91

92VLN

VLP

+

HLIM

90

DQ1

+

+

21

22

VQ1

FQ3

20

FQ2

FQ1

DQ2 VQ2

–In

+In

2

C2CM

G11 G21

– +

64EN

C1CM

1

Ω

9

inverting inputs of the amplifiers. The voltage noise ismodelled using DN1, DN2, VN1 and VN2 to create the noisesource and EN to model the noise on the non-inverting inputof the amplifiers.

Input CapacitanceDifferential and common-mode input capacitors, C

DIF, C

1CM,

and C2CM have been added to the enhanced macromodels.Input capacitance could also be modeled by including ca-pacitor coefficients in the transistor models. Instead, discretecapacitors were used so the comparison to the standardmodel would be more obvious.

FIGURE B2. P-Channel JFET-Input Op Amp Enhanced PSpice Parts Macromodel.

FIGURE B3. NPN-Input Op Amp Enhanced PSpice Parts Macromodel.

+In

+

V+

VO

V–

RC1 RC2

Q2Q1–In

1

2

RQDP VC

DC

+VE

DE

4

5

3

53

54

GCM GAR2

C2

6

9+

VB

RO1

+EGND

FB

7 +VLIM

8

RO2

REE CEE

99

IEE

10

C1

11 12

DLN

DLP

+

+

91

92VLN

VLP

+

HLIM

90

DQ1

+

+

21

22

VQ1

FQ3

20

FQ2

FQ1

RE1 RE2

CDIF

C2CM C1CM

DQ2 VQ2

13 14



Input Protection Diodes

If an op amp contains input protection diodes, its enhancedop amp macromodel also contains diodes connected be-tween the input pins as shown in Figures B5 and B6, forexample.

Quiescent PowerR

P was replaced by R

Q. The value of R

Q is higher. It models

only the resistive portion of quiescent current. The currentsources described below model the constant portion of thequiescent current. This technique provides a more accuratemodel of quiescent current vs power-supply voltage.

CDIF

–In

+

VO

V–

R D1 RD2

J2J1

+In

2

1

RQDP VC

DC

+VE

DE

4

5

3

53

54

GCM GAR2

C2

6

+VB

RO1

FB

7 +VLIM

8

RO2

RSS

CSS

99

ISS

10

C1

11 12

DLN

DLP

+

+

91

92VLN

VLP

+

HLIM

90

DQ1

+

+

21

22

VQ1

FQ3

20

FQ2

FQ1

+EGND

DQ2 VQ2

C2CM

V+

C1CM

G21G11

EN

– +

64

9

10


CDIF

–In

+

VO

V–

RC1 RC2

Q2Q1

+In

2

1

RQDP VC

DC

+VE

DE

4

5

3

53

54

GCM GAR2

C2

6

9+

VB

RO1

FB

7 +VLIM

8

RO2

REE

CEE

99

IEE

10

C1

11 12

DLN

DLP

+

+

91

92VLN

VLP

+

HLIM

90

DQ1

+

+

21

22

VQ1

FQ3

20

FQ2

FQ1

+EGND

DQ2 VQ2

C2CM C1CM

V+

RE1 RE2

13 14

FIGURE B4. PNP-Input Op Amp Enhanced PSpice Parts Macromodel.

Output Current Flowingfrom the Power-Supply NodesA number of components were added so that both load andquiescent current flow from the power supply nodes.

FQ3 mirrors the current flowing from VLIM . Positive current from F

Q3 flows through D

Q1 into V

Q1.

Negative current from FQ3

flows through DQ2

into VQ2

. FQ1 supplies constant portion of IQ plus mirrors positive

output current, which is measured by VQ1

. F

Q2 supplies constant portion of I

Q plus mirrors negative

output current, which is measured by VQ2.

NOTE: The enhanced op amp macromodels are more com-plicated and require more simulation time than thestandard macromodels, but will provide more accu-racy in simulations in some applications.

FIGURE B5. Input Protection Diode Circuitry Used onOPA27/37 Enhanced Macromodels.

2

1

–In

+In

5VO

3

V+

4

V–

D2BD1A

D2AD1B

VD1 VD2

R2IN

R1IN

INN

INP

FIGURE B6. Input Protection Circuitry Used on OPA77/177Enhanced Macromodels.

FIGURE B7. Input Protection Circuitry Used on INA114/118Enhanced Macromodel.

2

1

–In

+In

5VO

3

V+

4

V–

D1N2D1N1

3

1

4

X2.FS12

X2.FS22 X2.FS11

X2.FS21

X2.VS21

X2.VS11

X2.S21

X2.S11

3

2

4

X1.FS12

X1.FS22 X1.FS11

X1.FS21

X1.VS21

X1.VS11

X1.S21

X1.S11

Protection circuitry for the non-inverting input.

Protection circuitry for the inverting input.

V+

–In

V–

V+

+In

V–

11

improvements in current steering from the supply voltages.This model type is typically used to model high-speedamplifiers; however, it has come in useful when modellingfunction circuits that require special considerations.

SECTION C:MULTIPLE-POLE/ZEROMACROMODELSThe multiple pole/zero (“M”) macromodel allows modelingof more than two poles and any additional zeros in the opamp macromodel. All of the macromodels using this topol-ogy are in the MPZ_MOD subdirectory on the disk. Theinput stage of this model is similar to the standard andenhanced op amp macromodels; however, after the inputstage that similarity disappears. By using various circuittopologies the gain stages, pole stages, zero stages and pole/zero stages are constructed. The number of each of thesestage types is dependent on the performance characteristicsof the amplifier being modelled. An effort is made to matchthe macromodel performance as closely as possible to thetested gain/phase of the op amp. The output stage also offers

FIGURE C1. Input Stage to the N-Channel JFET-Input Op Amp Multiple Pole/Zero Macromodel.

2J12J11

3

1

13

V–

ISS

V+

G12

IOS CDIFF

R12

R11

G11

R13 R14

1615

C12

14 EOS

+

–

VA–+

–In

+In

7

4

–In J2J1

+In

13

V–

G21

CDIFF

R13

R11

R15 R16

1817

EOS

+–

C12

V+

IOS

G11

R13 R14

–+VA

ISS

14

15 16

4

2

3

7

1

FIGURE C2. Input Stage to the P-Channel JFET-Input Op Amp Multiple Pole/Zero Macromodel.

FIGURE DESCRIPTION

C1 N-Channel JFET–Input Op AmpC2 P-Channel JFET–Input Op AmpC3 NPN Bipolar–Input Op AmpC4 PNP Bipolar–Input Op AmpC5 Gain-, Pole/Zero, and Output StagesC6 ACF2101M–Op Amp SectionC7 ACF2101M–Node AssignmentsC8 OPA675M/676M–Input StageC9 OPA675M/676M–Package and Pad ParasiticsC10 VCA610M–Macromodel

TABLE VIII. Multi Pole/Zero Macromodels Figure Reference.

12

+In

R6

Q2Q1

VA

R3 R4

10 11

IOS CDIFF

R2

R1R5

7

+ –

EOS

C1

4IEE

V+

–In

V–10

FIGURE C3. Input Stage to the NPN–Input Op Amp Multiple Pole/Zero Macromodel.

R4

Q2Q1VA

R5 R6

13 14

15 16

11

12

+–

IOS

R2

R1

R3

7

+ –

EOS

ICC

C1

CDIFF 10

3

2

4

V+

V–

+In

–In

FIGURE C4. Input Stage to the PNP–Input Op Amp Multiple Pole/Zero Macromodel.

The accuracy of this model topology compared to the stan-dard and enhanced model topologies is improved for highspeed amplifiers primarily because of the improved gain/phase performance. Assuming no convergence problem ex-ists with the macromodels discussed so far, the time takenfor Spice to produce the dc operating point calculation of themultiple pole/zero model is about twice the time required forthe standard model. For transient analysis using this model,simulation time can be reduced by using the .OPTIONstatement to increase the number of transient iterations from10 to 40. The proper Spice command is:

.OPTIONS ITL4=40

The basic topology of input stages of this op amp model areshown in Figures C1, C2, C3, and C4. The input stage is theonly section in the macromodels that differ between the fourtypes of op amps (N-Channel FET, P-Channel FET, NPNBipolar, and PNP Bipolar). The remainder of the macromodelcircuit (gain stages, phase stages, CMRR stage, and outputstage) is shown in a generic form in Figure C5. A summaryof the parameters modelled is listed in Table X.

13

FIGURE C5. Multiple Pole/Zero Macromodel without Input Stage. Refer to Figures C1 Through C4 for Input Stage Topology.

+

+

+

+

G3 (V11 – V16)

G14 (VO – V15)

R14

R11

C4

R12

R13

C5

V12

G5 (V12 – V16)

G6 (V12 – V16)

R18

4

R16

R15 L1

L2

V13

G8 (V17 – V16)

G7 (V17 – V16)

V14

R20

L4

L3

R19

G10 (V13 – V16)

G9 (V13 – V16)

R22

R21

C7

C6

4

7

9

R10

R9

+

+

C3

C2

R8

R7VA

VAG2

G1

23

V2

V1

D2

D1

7

D7 G13 (V15 – VO) D8 G12 (V15 – Vp) R24

R23G11 (V7 – V15)D6D5

D3

D4V15(From Previous

Stage)

4

7 7

4

L5

Output

Intermediate Output Node

Output StageCorrection Current

Sources

Pole StageCommon-Mode Gain Stage with Zero

Zero/Pole Stage fz < fp

Pole/Zero Stage fp < fz

VH Reference

Gain Stage

V15

R17

G4 (V11 – V16)

V4

V3

VO

V+

V–

14

C12

R13 R14

V213

22

D21

23

D22

V22 G22

G22 C22 R27

IPS RPS R9

R10C23 R28

VOS

21

V+

V–

71

30

13

14

ISS

30

30

3

2J11

J12

15 16

D91

D92

21 66

G91

G92

R91

R92 D95 G95 G96 D96

D93 D94

94 95

4

7

–In

+In

7

4

FIGURE C6. Op Amp Section of the ACF2101 Using the Multiple Pole/Zero Macromodel Topology.

SR

3

6

31

37 CINT

33

32

SH1

SH2

2Sw In

Com

Cap

Sw Out

Sw Com

FIGURE C7. Node Assignments for ACF2101 Macromodel.

The multiple pole/zero topology is used to model the op ampsection of the ACF2101 switched integrator. The nodeassignments for this model are shown in Figure C6 and C7.The transient time of the switches (HOLD, RESET, andSELECT) should be programmed to have a slew of 6V/µs.Complying with this requirement will give the user greatersuccess in convergence during transient analysis, and a more

accurate emulation of the effect of the 200ns switchingspeed of the actual switching transistors in the ACF2101.This is easily implemented with the PULSE command inSpice. Also, to insure proper operation, always establish theinitial bias point for the transient analysis with RESET andHOLD equal to the potential of COMMON (node 3).

15

RSW1

C1

13

VTTL1

997

CSW1

RSW2

999

R4R3

7

111110

113 202 Q2 Q2-2Q1-2Q1

102

114 115

116

C11

IEE

10

998

CSW2

11

VTTL2

Q12Q11

214

216

C12

213

996 12

+V

+InB +InA –InB –InA

Cha

–V

FIGURE C8. Input Stage of the OPA675 and OPA676 Switched-Input Op Amp Using the Multiple Pole/Zero MacromodelTopology.

FIGURE C9. Package and Pad Parasitics Modelled by the OPA675 and OPA676 Macromodel.

switched device and the OPA676 is a TTL-switched device.Both files will model the device characteristics and packageparasitics. If the user is using the product in its die form, thepackage parasitics no longer apply (Figure C9).

The OPA675 and OPA676 are wideband op amps with twoindependent differential inputs (Figure C8). The multiplepole/zero topology is used to model the op amp portion ofthese switched-input amplifiers. Both amplifiers are identi-cal except for the switch logic. The OPA675 is an ECL-

Ideal OPA

675/676

3

COUT219

5

CCPP1

CCPP2

8

COUT1

LOUT

LCPP

1 (16)

2 (15)

CP1

CM1

CP2

CM2

LM

LP102 (202)

108 (201)

+In

–In

Out

Comp Cap

16

26

R2

10

11 Q2 Q3Q1

IS

7

Q02Q01 8

6

32

13

C3G3 R3C1

7

12

E1

E44

C42

1

C01 C02

R01

20

R02

21

D01

D03

D02

D04

6

29 24

27 28

G31R31

31

C41R41

R42

E43

G42

G41

E42

E41

D41

D42

44

41

45

G1G2

7

6

V54

V53

E51

55

D53

D54

G54 G53 G52

G51

R54

D57 D58

R53

51

52

53 54

7

5

6

43

42

Gain Control

Input Stage

Quiescent CurrentGain Stage

Output Stage

D55 D56

I1

FIGURE C10. VCA610M Voltage Controlled Amplifier using the Multiple Pole/Zero Macromodel Topology.

17

SECTION D:SIMPLIFIED CIRCUIT MODELSAs already mentioned the simplified circuit models providea much different simulation approach, because they do notfollow a standard model design. They are micromodels atthe transistor level, therefore each model has its individualcircuit schematic, which are shown on the following pages.Almost all of the devices of this model level (Level IV) arewideband/high-speed components with bandwidth capabili-ties of up to 1GHz. Some models have only one simplifiedcircuit model available, and are labeled with the suffix “X”.Other models offer two simplified circuit models. In general,the models with an “X1” suffix are of equivalent complexityas the “X” models. They are simpler implementations of themacromodel and will simulate faster; however, the accuracyis not as good as with the macromodels with an “X2” suffixfor the same product.

All of these models are found in the CIR_MOD subdirectoryon the disk. These models are designed using differenttopologies than mentioned above and several non-linearelements. Because of the increased number of non-linearelements in these models, the simulation time is longer, butthe accuracy is improved.

The wideband operational amplifiers that have simplifiedcircuit macromodels were designed using several subcircuitsthat allow the user to implement a variety of configurations.The OPA622 is a monolithic amplifier that can be config-ured as a current-feedback amplifier or a voltage-feedbackamplifier. Like typical current-feedback amplifier, theOPA622 has a constant large-signal bandwidth of 280MHz.One would expect that when the OPA622 is configured in avoltage-feedback configuration the bandwidth would changewith gain. This is not the case. When the OPA622 isconfigured as a voltage-feedback amplifier, it will againhave a constant bandwidth over a wide gain and outputvoltage range. In the voltage-feedback mode, the OPA622offers the speed advantages of current-feedback amplifiersand matched input impedance advantage of the voltage-feedback op amp. The OPA623 is strictly configured as acurrent-feedback amplifier, using the same internal designas the OPA622.

The OPA660 wideband amplifier offers the user an “idealtransistor” and a buffer. The “ideal transistor” has threeterminals available to the user—a high-impedance input(base), a low-impedance input/output (emitter) and the cur-rent output (collector). This “ideal transistor”, otherwisecalled an Operational Transconductance Amplifier (OTA),is constructed using several discrete real transistors on thechip to give the user superior gain and temperature perfor-mance, hence, the comparison to an “ideal transistor”.

Although these transistor level models are more accuratethan the other three topology levels used for macromodelson this disk, the user is cautioned that all models are an aidto circuit design and not a suggested replacement for bread-boarding. Simulation should be used as a forerunner or asupplement to traditional lab testing. The parameters that aremodelled by the transistor level circuit macromodels arelisted in Table X.

TABLE VIIII. Simplified Circuit Models Figure Reference.

FIGURE DESCRIPTION

D1 BUF600/601X1 Circuit ModelD2 BUF600/602X2 Complex Circuit ModelD3 BUF634X Circuit ModelD4 ISO120/121X Circuit ModelD5 ISO130 Circuit ModelD6 MPC100X1 Circuit ModelD7 MPC100X2 Complex Circuit ModelD8 OPA603X Circuit ModelD9 OPA620/621X Circuit ModelD10 OPA622X1 Circuit ModelD11 OPA622X2 Complex Circuit ModelD12 OPA623X1 Circuit ModelD13 OPA623X2 Complex Circuit ModelD14 OPA640X/OPA641X Circuit ModelD15 OPA642X/OPA643X Circuit ModelD16 OPA644X Circuit ModelD17 OPA646X Circuit ModelD18 OPA648X Circuit ModelD19 OPA64x Package and Pad ParasiticsD20 OPA658X Circuit ModelD21 OPA660X1 Circuit ModelD22 OPA660X2 Complex Circuit Model

18

Q16X

Q41 16X

4042

V–

VOUT

V+

V41

V42

22

4

C39

41

C40

R34

5

Q34

Q30

Q29

39

Q33

C33

R33

33

VIN

Q23

Q21

21

C208

Q22

12X

Q24RQC

1

8

24

I21

FIGURE D1. BUF600X1 and BUF601X1 Simplified Circuit Macromodel. Compared to Figure D2, this macromodel is lesscomplex with faster simulation times.

FIGURE D2. BUF600X2 and BUF601X2 Complex Macromodel. Compared to Figure D1, this macromodel is more complexand requires more simulation time.

Q42 6X

Q41 16X

V–

VOUT

V+

22

4

I21

5

Q34

Q30 1.4X

Q25

C204

VIN

Q23

Q21

21

C208

Q22

12X

Q24RQC

1

8

Q26

24

Q29 1.4X

Q27 1.4X

Q28 1.4X

Q33

Q31 2X

Q35

Q36

Q32 2X

34

36

Q38 6X

Q37 6X

Q39 6X

Q40 6X

41

32

35

40

39

27

28

19

C2

R4R3

C2V

C2L

E3

E2

E4Q4

Q3

Q2

Q1

I6

I3I3

I4

R6

I1

I2

R5

56

54

10(18)

–VS2

COM2

VOUT

VOUT

GND2

+VS2

V1

V2

58

9(17)

16(24)

15(23)

12(20)

3(3)(1)

+VS1

GND1

VIN

COM1

–VS14(4)

24(40)

C1

14(22)

57

R2 R1 50

R7

VOS

6023(39)

NOTE: (1) First node number is for ISO120. Second node number is for ISO121.

51

21(37)

55

11(19)13(21)52

E1

FIGURE D4. ISO120/121X Isolation Amplifiers Simplified-Circuit Macromodel.

FIGURE D3. BUF634X Simplified Circuit Macromodel.

VOUT

Q2

Q1

D1

D9

D8

Q4

CINQ9 Q10

Q12

R5R6

Q11

16

15

Q5

D5

D6

C2

C1

C0

R27

R26

R25

R24

R7 R8

R2

R1

R9 R10

R1

R2

D2

Q3

D4

D10

Q14

Q13

D11

D3

73

7

Q6

Q8

98

8

94

5

85

80

3

1022

4

14

18

10

11

12

9

17

6

13

86

VOS

Q7

RIN

CP

IB

Iss

1VIN

23

21

22

24

20

90

+VCC

–VCC

20

FIGURE D5. ISO130X Simplified-Circuit Model.

R5R3

D1

R12

3 10

D3

D2

VS1

GND14

1

VINP

GVS1VIN+

R4

I2

I1

9

R2

D4

VIN

VIN–

RE1 RE2

1614

Q2Q1

I3

VOUT+

VOUT–

C1

R7TDELAY R8 R9

R11

R10

C2 C4

C3

18

13

11

V2

E1

9

+

15

–

10

V3

12

R6

17

R12

19

20

21

E2

GVS2

E3

22

23

7

6

GND2

5

VS2

8

21

G21

C23

R22V22

R21

14SEL

C25

C26

In

26

25

Q22

Q21

R23

R24

23 Q23 Q24

C24

Q 25

Q26

VOUT

V–

V+

V28

V27

11

10

12

27

28

25

26

FIGURE D6. MPC100X1 Simplified-Circuit Macromodel. Compared to Figure D7, this macromodel is less complex with fastersimulation times. Shown here is only one out of four inputs of the MPC100. However, the same circuit schematicapplies to the MPC102X1 and MPC104X1 model.

R24

C33

Q22

D25

D26

Q30

42Q36

Q35

Q29

27

R29

Q31

R34 R43

R45

R46

Q45

Q43

Q44 Q46

R32

35

36

1

33Q37

Q38Q40

Q39

Q42

Q41

11

39

40

10

12

14

34

32

45

Q32

C24

Q21

Q23

Q24

25

23

R23

R30

Q28

C28

Q27

26

30

29

Q33 24

22

41

3421

SEL

In

11

28

V+

VOUT

V–

44

46

43

FIGURE D7. MPC100X2 Complex-Circuit Macromodel. Compared to Figure D6, this macromodel is more complex and requiresmore simulation time. Shown here is only one out of four inputs of the MPC100.

22

+In3

R0EB

RPS

GC

R0B

R0A6

7Q0B

9

11

Q0A

Q8A

R0EA

8

R8A

34

36

10

Q5A

R5A

32

30

Q9A

–In

R8B

35

Q5B37

R5B

33

31Q8B

Q9B

IS

RB

FB

CB

R1A

R2AT

16

Q1A

R1EA

Q2A

14

4

R1EB

15

Q1B

R2BT

Q2B

17

13

R1B

+V6A

Q6A

+V6B

Q6B

26

27

19

18

Q3A

22

20

R3

Q3B

23

Q4A

24

R4A

25

Q4B

2

QSCA

QSCB

R4B

1

C2B

V–

VO5

V+

28

21

2

FIGURE D8. OPA603X High Speed Current-Feedback Op Amp Simplified-Circuit Macromodel.

23

–In

+In

5VO

2X2X2

1

109

Q5

R4

5X17

Q2Q1

4X

Q3

13

R3

14

R5

Q4

16

R6

15

2X

Q9

22

R8

Q10

23

R9

21

2X

Q8

2X

Q6Q718

19

I1

R7

Q11

20X

20

24

I2

Q14

40X

Q13

40X

V–

Q12

20X

25

I3

C1

V+3

R2R1

4

1211

NOTE: OPA620 and OPA621 simplified-circuit macromodelsare the same with the following exceptions.

C1

I1

I2

I3

MODEL (pF) (mA) (mA) (mA)

OPA620 10 1.1 4 2OPA621 2 1.3 3.5 3.5

FIGURE D9. OPA620X and OPA621X High Speed Op Amp Simplified-Circuit Macromodel.

24

FIG

UR

E D

10. O

PA

622X

1 S

impl

ified

Circ

uit M

acro

mod

el. C

ompa

red

to F

igur

e D

11, t

his

mac

rom

odel

is le

ss c

ompl

ex w

ith fa

ster

sim

ulat

ion

times

.

Bia

sing

Circ

uit

(BC

)

R23

Q25

6X

Q24

Q26

6X

Q30

Q29

Dia

mon

d B

uffe

r (D

B)

Dia

mon

d T

rans

isto

r (D

T)

13

28

12

Buf

fer

+

C28

Q28

Q27

Q22

Q23

C22

C21

Q21

C23

C27

21

23+

In

R63

Q65

6X

Q64

Q66

6X

8

Buf

fer

–

Q62

Q63

C62

C61

Q61

C63

61

63–I

n3

Q12

3

141

Q12

4

Q12

2 10

X

Q12

1

25

R12

2

R12

3

122

X1

X4

X2

131

I Q A

djus

tV

–

27

22

4

62

VO

UT

Q31

Q33

Q34

Q32

10O

TA

C10

33 34 121

Q3637

Q35 Q

37

Q38

Q40

2.

2X

Q39

2.

2X

38

9

11V

+

6

Vol

tage

O

ut

VO+

VO–

Cur

rent

Buf

fer

(CB

)

X3

111

25

OTAQ27

Q26 10X

Q21

C213 C210

10

Q22

Q25 10X

Q23 10X

Q24 10X

Q28

Q29 6X

Q30 6X

28

Q32 6X

Q31 6X

30

23

24

V+

+In

5V–

141

4

131

12

29

Q33 8X

Q34 8X

Q48 48X

Q47 48X

VO–

VO+

6

C209

11

9

Q44 4X

Q43 4X

Q45 12X

Q46 12X

47

46

45

Q38

5X

Q39 5X

Q37

5X

Q40 5X

Q35 8X

Q36 8X

125

111

13

VOUT

X2 X3

37

38

Buffer +

Diamond Transistor (DT)

Current Buffer (CB)

111

125

33

34

Q67

Q66 10X

Q61

C208

Q62

Q65 10X

Q63 10X

Q64 10X

Q68

Q69

Q70

68

Q72 6X

Q71 6X

70

63

64

V+

+In

5V–

141

3

131

12

69

Q73 4X

Q74 4X

X4 X1

Diamond Buffer (DB)

Biasing Circuit (BC)

73

74

8

I121

Q123

Q121

Q122

6 X Q124

R122

122

R123

Q125 11X

C202

E13

C121

121

E14

C124

124

Buffer –

2

IQ Adjust

5

141

131

12V+

V–

FIGURE D11. OPA622X2 Complex Macromodel. Compared to Figure D10, this macromodel is more complex and requiresmore simulation time.

26


R23

Q25 6X

Q24

Q26 6X

Q30

Q29


2

28

C28Q28

Q27

Q22

Q23

C22

C21

Q21

C23

C27

21

23–In

Q123

141

Q124

Q122 10X

Q121

4RQC

122

X1 X2

131

V–

27

22

3

Q31

Q33

Q34

Q32

C35

33

34

121Q36

37

Q35

Q37

Q38

Q40 2.2X

Q39 2.2X

38

6VOUT

Current Buffer (CB)

X3

111

3935

FIGURE D12. OPA623X1 Simplified-Circuit Macromodel. Compared to Figure D13, this macromodel is less complex withfaster simulation times.

27

Q27

Q26 10X

Q21

C39

Q22

Q25 10X

Q23 10X

Q24 10X

Q28

Q29 6X

Q30 6X

28

Q32 6X

Q31 6X

30

23

24

V+

+In

4V–

141

3

131

7

29

Q33 10X

Q34 10X

Q48 48X

Q47 48X

V–

V+

4

C206

7

6

Q44 4X

Q43 4X

Q45 12X

Q46 12X

47

46

45

Q38 5X

Q39 5X

Q40 5X

Q35 10X

Q36 8X

123

111

2

VOUT

X2 X3

37

38

–In


Current Buffer (CB)

111

123

33

34

X1


Q123

Q121

Q122

6 X Q124

RQC

122

Q125 11X

E13

C121

121

E14

C124

124

4

141

131

7V+

V–

C203

C202

Q37 5X

39

FIGURE D13. OPA623X2 Complex Macromodel. Compared to Figure D12, this macromodel is less complex with fastersimulation time.

28

FIG

UR

E D

14.

OP

A64

0X,

OP

A64

1X,

Wid

e B

andw

idth

Op

Am

p S

impl

ified

-Circ

uit

Mac

rom

odel

. S

ee F

igur

e D

19 f

or p

acka

ge p

aras

itics

.

Q2

Q1

Q20

Q15

Q19

Q14

V1

R15

R13

R14

R12

Q18

R11

Q20

Q11

R8

Q8

Q7

R9

C8

C6

Q22

Q21

R16

2X 2X

4X 4X4X

4X4X

I SO

UR

Q27

Q26

R18

Q25

24X

24X

2X

Q28

2X

Q24

Q23

R19

38

Q32

Q29

Q31

Q30

36X

36X

Q33

20X

Q34

R20

10X

C2

C3

8X

R4

R22

R2

Q3

R3

R5

2 4

R21

1 3

R1

21

6

1716

7

1819

20

23

24 22

25

27

26

4544

1716

28

15

29 31

30 3234

33

36

35

37 40

39

4210

X20

X

41

5

43

12X

12X

to C

1P

29

FIG

UR

E D

15.

OP

A64

2X,

OP

A64

3X,

Low

Dis

tort

ion,

Hig

h-S

peed

Op

Am

p S

impl

ified

-Circ

uit

Mac

rom

odel

. S

ee F

igur

e D

19 f

or p

acka

ge p

aras

itics

.

Q4

Q2

Q23

Q18

Q22

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R18

R14

R17

R13

Q20

R8

Q8

R11

Q12

C8Q

24

4X 4X4X

3X3X

I SO

UR

Q30

Q29

R21

Q28

20X

20X

2X

Q31

2X

Q27

Q28

R22

49

Q35

Q32

Q34

Q33

36X

36X

Q38

20X

Q37

R23

20X

C2

C3

8X

R3

R27

R25

Q5

R2

R5

2 4

R26

1 3

R24

17 7

1819

20

24

23 22

26

27

2829

32

44

43 45

47

46 50 51

48

5220

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53

5

54

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CA

4

Q25

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15

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R18

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31

34

3738

25

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6

Q3

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R4

21

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35 16

22

2

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R9

35

42

2

36

30

FIG

UR

E 1

6. O

PA

644x

, H

igh-

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ed O

p A

mp

Sim

plifi

ed-C

ircui

t M

acro

mod

el.

See

Fig

ure

D19

for

pac

kage

par

asiti

cs.

R6

R7

R4

R5

R27

R3

R9

R28

RE

31

R19

R32

R10

Q12

Q16

Q17

Q13

29

31

30

C3P

P

C3

C4P

P

C4

76

54

Q38

Q39

48 49

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Q11

Q3

Q10

Q8

Q14

Q6

V2

F2

V3

F3

Q09

C2

C1

C2P

P

C1P

PF

1

I SO

UR

I OU

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C03

4

CS

33

C02

9R

029

RE

29

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2

C6

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33

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33

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3

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2

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R18

RB

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29

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4

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CE

32

C12

C12

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P

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Q44

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Q43

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R33

R34

R1

R2

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2 2

17

5859

2 4

18

19

2728

3259

59

59

5959

39

3735

382

24

2526

21

22

20

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2

2

33

3459

36

215

2

46

59

2

2

18

44 45

43 59

2

40

165251

5

31

FIG

UR

E D

17.

OP

A64

6X,

Low

Pow

er,

Hig

h-S

peed

Op

Am

p S

impl

ified

-Circ

uit

Mac

rom

odel

. S

ee F

igur

e D

19 f

or p

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aras

itics

.

Q2

Q1

Q18

Q15

Q17

Q11

V1

R14

R12

R13

R11

Q18

Q10

R8

Q6

Q7

R3

C8

C7

3X3X

I SO

UR

Q22

Q21

R15

Q19

2X 2X

Q24

R16

Q32

Q31

36X

36X

R17

C2

C3

2X

R4

R19

R2

Q3

R3

R5

2 4

R19

1 3

R1

21

6

1716

7

1819

20

23

24 22

25

27

26

2817

16

29

15

30

3133

4X

5

4X4X

2X

38

41

42Q

28

4020

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X

43

Q30

Q27

Q29

Q26

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372X

453936

354X

Q20

Q25

17

2X34

32

Q23

32

FIG

UR

E D

18.

OP

A64

8X,

Hig

h-S

peed

Op

Am

p S

impl

ified

-Circ

uit

Mac

rom

odel

.

5

1 2

12

14 17

43

18 23

19 13

2221

2930

2015

16

24 27

26

6

28

32

38

3942

40

35

37

34

36

41

43

31

25 33

R18

R19

B11

B12

B5

B6

B27

B28

B31

B37

B39

B33

B35

B41

B42

R24

B?

??

B13

B7

B22

B1

B3

B2

B4

B23

B24

B25

B32

B8

B9

B29

B30

B10

B15B18

B14R

5R

8R

1R

2R

22

R7

R8

R

3

R4

R

23

C3

CC

OM

P

I SO

UR

I 2

B38

33

FIGURE D19. Schematic to Model the Pad Parasitics Used for the OPA64X High-Speed Op Amp Series.

R2P

L 2P

132R

1PL 1

P

6

R7P

L 6P

14

R5P

L 5P

7

R12

PL 1

0P

11

R11

PL 9

P

215

L 13P

R18

P

60 63 66 67

61 64 68

62 65 69

C4P

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P

C3P

C9P

C15

P

C2P

C8P

C14

P

C1P

L 18P

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P

3

L 19P

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P

10

L 22P

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P

5

L 23P

R31

P

12

L 27P

R33

P

4

L 28P

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P

98

73 76 79

74 77 80

75 78 81

C23

P

C30

P

C24

P

C31

P

C38

P

C22

P

C16

P

C29

P

C35

P

C18

PC

17P

1

L 14P

R17

PL 1

5PR

21P

7071

72

R38

PL 3

1P82

34

FIGURE D20. OPA658X, OPA2658X and OPA4658 Current-Feedback Wideband Op Amp Simplified-Circuit Macromodel.

534

3533

36

Q20

Q19

Q11

Q13

Q14

Q12

Q16

C2

Q22

Q18

R11

Q21

Q17

R10

Q9

Q8

R4

R3

R9

Q15

27

37

24 25 26

28 30

31

32

29

R6

R8

R7

23

2119

22

R2

R1

R5

R16

R17

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Q7 Q10

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C3

C4

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Q3

Q4

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20

17

16

13 14

R12

1 2

I SO

UR

1

I SO

UR

2

11 12

1 2

C1

43

C2P

C1P

C4P

C3P

R4P

L 4P

C5P

R6P

L 8P

R5P

L 5P

R3P

L 3P

L 11P

R11

P

R2P

R7P

L 2P

L 7P

R8P

L 8P

R10

PL 1

0P

R9P

L 9P

4342 45

46 49

50

4744

R1P

L 1P

41

48

C6P

C8P

C7P

2 8 9 7

31 5

4 2

6 10

5152

53

5455

56

35

FIG

UR

E D

21. O

PA

660X

1 S

impl

ified

-Circ

uit M

acro

mod

el. C

ompa

red

to F

igur

e D

22, t

his

mac

rom

odel

is le

ss c

ompl

ex w

ith fa

ster

sim

ulat

ion

times

.

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sing

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uit

(MB

C)

V+

R23

Q25

Q24

Q26

Q30

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2

C20

8

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8

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mon

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uffe

r (M

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ond

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nsis

tor

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T)

2

26

7

Col

lect

or

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itter

C26

Q28

Q27

Q22

Q23

C22

C21

Q21

C23

C25

21

23

Bas

e

R73

Q75

Q74

Q76

C20

66

Buf

fer

Out

Q72

Q73

C72

C71

Q71

C73

71

73

Buf

fer

In 5

Q12

3

14

Q12

4

Q12

2

Q12

1

1

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1

4

R12

2

R12

3

122

X3

X1

X2

13

I Q A

djus

tV

–

25

22

3

72

36

FIG

UR

E D

22. O

PA

660X

2 C

ompl

ex M

acro

mod

el. C

ompa

red

to F

igur

e D

21, t

his

mac

rom

odel

is m

ore

com

plex

and

req

uire

s m

ore

sim

ulat

ion

time.

Bia

sing

Circ

uit

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C)

V–

I Q A

djus

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1

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2

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1

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4

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4

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3C

121

Q12

5

14

13

74

Q74

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C20

5

Q76

Q78

Q79

Q80

Q72

Q73

73

77

79

80

Q82

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fer

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14

Buf

fer

In

13

Q75

Q77

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21Q

23

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Q26

Q22

1424

Q27

27

R27

C20

3

Q25

Q31

Q29

Q32

Q30

27

29 30

Q34

Q36 36

34 R34

R36

C20

8

C20

2

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Q3535R

35

2

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mon

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r (M

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EM

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EN

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AS

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ES

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E

CM

RR

vs

FR

EQ

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Y

PS

RR

PS

RR

vs

FR

EQ

UE

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Y

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EW

RA

TE

PA

D P

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AS

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NO

GR

OU

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RE

FE

RE

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CO

MM

EN

TS

MODEL

DE

VIC

E

CH

AR

AC

TE

RIS

TIC

S

MO

DE

LE

D

FIG

UR

E

ACF2101M X NA X X X X X X X X X X X X X 7 C6,7BUF600X1 X NA X NA X X X X X X X 10, 14 D1BUF600X2 X NA X X X NA X X X X X X X X X 10, 14 D2BUF601X1 X NA X NA X X X X X X X 10, 14 D1BUF601X2 X NA X X X NA X X X X X X X X X 10, 14 D2

BUF634X X X X X X X X X X 1 D3INA101 X X X X X X X X X 1 2INA101E X X X X X X X X X X X X X 1 2INA102 X X X X X X X X X 1 2INA102E X X X X X X X X X X X X 1 2

INA103 X X X X X X X X X X 1 3INA103E X X X X X X X X X X X X X 1 3INA105 X X X X X X X X X 2 1aINA105E X X X X X X X X X X X 2 1aINA106 X X X X X X X X X 2 1a

INA106E X X X X X X X X X X X 2 1aINA110 X X X X X X X X X X 1 5INA110E X X X X X X X X X X X X X 1 5INA111 X X X X X X X X X X 1 2INA111E X X X X X X X X X X X X X 1 2

INA114 X X X X X X X X X 1 2INA114E X X X X X X X X X X X X X 1 2INA115 X X X X X X X 2INA115E X X X X X X X X X X X X 2INA117 X X X X X X X X X 2 16

INA117E X X X X X X X X X X X 2 16INA118 X X X X X X X X 4INA118E X X X X X X X X X X X 4INA120 X X X X X X X X X X 1 6INA120E X X X X X X X X X X X X X X 1 6

INA131 X X X X X X X 2INA131E X X X X X X X X X X X X 2ISO120X NA NA X X X X X 4 D4ISO121X NA NA X X X X X 4 D4ISO130X D5

MPC100X1 X X X X X X X X X 14, 10 D6MPC100X2 X X X X X X X X X X X X X 14, 10 D7MPC102X1 X X X X X X X X X 14, 10 D6MPC104X1 X X X X X X X X X 14, 10 D6OPA1013 X X X X X X X X A6

OPA1013E X X X X X X X X X X B4OPA111 X X X X X X X X X A4OPA111E X X X X X X X X X X X X X X B2OPA121 X X X X X X X X X A4OPA121E X X X X X X X X X X X X X X B2

OPA124 X X X X X X X X X A4OPA124E X X X X X X X X X X X X X X B2OPA128 X X X X X X X X X A4OPA128E X X X X X X X X X X X X X X B2OPA129 X X X X X X X X X A4

OPA129E X X X X X X X X X X X X X X B2OPA131 X X X X X X X X XOPA131E X X X X X X X X X X X X X XOPA177 X X X X X X X X A5OPA177E X X X X X X X X X X X X B6

TABLE X. Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel.

38

OPA2107 X X X X X X X X X A4OPA2107E X X X X X X X X X X X X X X B2OPA2111 X X X X X X X X X A4OPA2111E X X X X X X X X X X X X X X B2OPA2131 X X X X X X X X X

OPA2131E X X X X X X X X X X X X X XOPA2541 X X X X X X X X X A4OPA2541E X X X X X X X X X X X X B2OPA2604 X X X X X X X X X A4OPA2604E X X X X X X X X X X X X X X B2

OPA2604M X X X X X X X X X X X X X X X X C2, 5OPA2658X X X X X X X X X X X X X X X X X X X X X D20OPA27 X X X X X X X X A5OPA27E X X X X X X X X X X X X B4OPA27M X X X X X X X X X X X X X X X C3, 5

OPA37 X X X X X X X X A5OPA37E X X X X X X X X X X X X B4OPA404 X X X X X X X X X A4OPA404E X X X X X X X X X X X X X X B2OPA445 X X X X X X X X X A4

OPA445E X X X X X X X X X X X X B2OPA4131 X X X X X X X X XOPA4131E X X X X X X X X X X XOPA4658X X X X X X X X X X X X X X X X X X X X X D20OPA501 X X X X X X X X X A5

OPA501E X X X X X X X X X X X X B4OPA502 X X X X X X X X X A3OPA502E X X X X X X X X X X X X B4OPA511 X X X X X X X X X A4OPA511E X X X X X X X X X X X X B2

OPA512 X X X X X X X X X A4OPA512E X X X X X X X X X X X X B2OPA541 X X X X X X X X X A4OPA541E X X X X X X X X X X X X B2OPA602 X X X X X X X X X A4

OPA602E X X X X X X X X X X X X X X B2OPA603X X X X X X X X X X X X X 9 D8OPA604 X X X X X X X X X A4OPA604E X X X X X X X X X X X X X X B2OPA604M X X X X X X X X X X X X X X X X C2, 5

OPA606 X X X X X X X X X A4OPA606E X X X X X X X X X X X X X X B2OPA620 X X X X X X X X A5OPA620E X X X X X X X X X X X B4OPA620X X X X X X X X X X X X X 8 D9

OPA621 X X X X X X X X A5OPA621E X X X X X X X X X X X B4OPA621X X X X X X X X X X X X X 8 D9OPA622X1 X NA X NA X X X X X X X 10, 14 D10OPA622X2 X NA X X X NA X X X X X X X X X X 10, 14 D11

OPA623X1 X NA X NA X X X X X X X 10, 14 D12OPA623X2 X NA X X X NA X X X X X X X X X X 10, 14 D13OPA627 X X X X X X X X X A4OPA627E X X X X X X X X X X X X X X B2OPA628M X X X X X X X X X X X X X X X C3

INP

UT

BIA

S C

UR

RE

NT

INP

UT

OF

FS

ET

CU

RR

EN

T

OF

FS

ET

VO

LT

AG

E

INP

UT

VO

LT

AG

E N

OIS

E

INP

UT

CU

RR

EN

T N

OIS

E

INP

UT

PR

OT

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TIO

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UT

IMP

ED

AN

CE

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RE

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WIN

G

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CE

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EN

T

QU

IES

CE

NT

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EN

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s P

OW

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SU

PP

LY

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IES

CE

NT

CU

RR

EN

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PE

RA

TU

RE

GA

IN v

s F

RE

QU

EN

CY

GA

IN v

s T

EM

PE

RA

TU

RE

PH

AS

E R

ES

PO

NS

E

CM

RR

vs

FR

EQ

UE

NC

Y

PS

RR

PS

RR

vs

FR

EQ

UE

NC

Y

SL

EW

RA

TE

PA

D P

AR

AS

ITIC

S

NO

GR

OU

ND

RE

FE

RE

NC

E

CO

MM

EN

TS

MODEL

DE

VIC

E

CH

AR

AC

TE

RIS

TIC

S

MO

DE

LE

D

FIG

UR

E

CO

MM

EN

TS

TABLE X (cont). Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel.

39

OPA637 X X X X X X X X X A4OPA637E X X X X X X X X X X X X X X B2OPA640X X X X X X X X X X X X X X X X X X X X X 8, 12 D14OPA641X X X X X X X X X X X X X X X X X X X X X 8, 12 D14OPA642X X X X X X X X X X X X X X X X X X X X X 8, 12 D15

OPA643X X X X X X X X X X X X X X X X X X X X X 8, 12 D15OPA644X X X X X X X X X X X X X X X X X X X X X 8, 12 D16OPA646X X X X X X X X X X X X X X X X X X X X X 8, 12 D17OPA648X X X X X X X X X X X X X X X X X X X X X 8, 12 D18OPA660X1 X NA X NA X X X X X X X X X X D21

OPA660X2 X NA X X X X NA X X X X X X X X X X 10, 14, 5 D22OPA671M X X X X X X X X X X X X X X X X X X X X X C2, 5OPA675M X X X X X X X X X X X X X X X X 6 C8, C9OPA676M X X X X X X X X X X X X X X X X 6, 11 C8, C9OPA77 X X X X X X X X A5

OPA77E X X X X X X X X X X X X B6OPT101 X X X X X X X A2OPT201 X X X X X X X A2OPT202 X X X X X X X A2OPT209 X X X X X X X A2

UAF42 X X X X X X X X X 3 A4UAF42E X X X X X X X X X X X X 3 B2VCA610M X X X X X X X X X 13 C10

INP

UT

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OT

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CE

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BIA

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NC

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IMIT

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FL

OW

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FR

OM

PO

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UP

PL

IES

OU

TP

UT

VO

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AG

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WIN

G

QU

IES

CE

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IES

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T v

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OW

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PP

LY

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IES

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T v

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GA

IN v

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CY

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RR

PS

RR

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COMMENTS: 1. Instrumentation Amplifier. 2. Difference Amplifier. 3. All four op amps in the UAF42 chip are identical. This model only contains one op amp. 4.Also models isolation barrier impedance. 5. Also models enable transient response and the quiescent resistor transient response. 6. Also has the input control switchand models its transient response. 7. Model includes HOLD, RESET and SELECT switches and internal capacitor. 8. Also models total harmonic distortion. 9. Alsomodels bias current vs power supply and bias current vs common-mode. 10. Also models group delay time. 11. Also models TTL switching times. 12. Also modelsoutput recovery time. 13. Also models gain control vs frequency. 14. Contact the factory for a more detailed description of this macromodel 800 548-6132 or FAX(602) 746-7852.

TABLE X (cont). Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel.

40

RGI

= One of the three internal gain-setting resistors shownin the table (Ω)R

GE = external gain-setting resistor (Ω)

INA103INSTRUMENTATION AMPLIFIER

The INA103 contains internal gain-setting and feedbackresistors:

RFB

= 3kΩR

G = 60.606Ω (Gain = 100)

The internal gain-setting feedback resistors may be used, orexternal feedback resistors may be used.

If the internal resistors are used:

GAIN = 1 + (6k/RG)

If external feedback resistors are used:

GAIN = 1 + (2 • RFB

/RG)

Where:R

G = Optional external gain-setting resistor (Ω)

RFB

= Optional external feedback resistor (Ω)


VOUT

= − 1C

INT

iIN∫

PRODUCT NOTESFor more information please refer to the individualdata sheet.

ACF2101SWITCHED INTEGRATOR

The integrator output voltage range is from +0.5V to –10V.The output voltage (VOUT) can be calculated as:

VOUT = the output voltage of the ACF2101CINT = the integration capacitor (in farads)iIN = the input current (in amperes)dt = the integration time (in seconds)


The INA101 contains internal gain-setting feedback resis-tors;

RFB

= 20kΩWhen using the metal package (TO-100), these resistorsmust be used. When using the ceramic or plastic packages,the internal gain-setting feedback resistors may be used, orexternal feedback resistors may be used.

If the internal resistors are used:

GAIN = 1 + (40k/RG)

If external feedback resistors are used:

GAIN = 1 + (2 • RFB/RG)

Where:R

G = external gain-setting resistor (Ω)

RFB

= optional external feedback resistor (Ω)


The INA102 contains internal gain-setting and feedbackresistors;

RFB = 20kΩINA102 INTERNAL GAIN-SETTING RESISTORS

RG GAIN(Ω) (V/V)

4.444k 10404 10040.4 1000

The internal resistors are ratio trimmed to high accuracy andhave excellent tracking with temperature for low gain drift.If the internal resistors are used:

GAIN = 1 + (40k/RG)

External gain-setting resistors can be used in series with oneof the internal gain-setting resistors. If external gain-settingresistors are used:

GAIN = 1 + (40k/[RGI

+ RGE

])

dt

INA110 INTERNAL GAIN-SETTING RESISTORS

RG GAIN(w) (V/V)

4.444K 10404.04 100201.0 20080.16 500

The INA110 contains internal gain-setting and feedbackresistors;

RFB

= 20kΩThe internal resistors are ratio trimmed to high accuracy andhave excellent tracking with temperature for low gain drift.If the internal resistors are used:

GAIN = 1 + (40k/RG)

External gain-setting resistors can be used in series with oneof the internal gain-setting resistors. If external gain-settingresistors are used:

GAIN = 1 + (40k/RGI

+ RGE

])

RGI =one of the four above internal gain-setting resistors (Ω)R

GE = external gain-setting resistor (Ω)


The INA111 contains internal gain-setting feedback resis-tors;

RFB = 25kΩExternal gain-setting resistors are used to set the gain at:

GAIN = 1 + (50k/RG)

RG = external gain resistor (Ω)

41


The INA120 contains an internal gain-setting and feedbackresistor string;

RFB = 20kΩINA120 INTERNAL GAIN-SETTING RESISTORS

RG GAIN[Ω] [V/V]

4000 10400 10044 1000

The internal resistors are ratio-trimmed to high accuracy andhave excellent tracking with temperature for low gain drift.If the internal gain-setting resistor string is used, it can beconnected to the amplifier input terminals to give accurategains of 1, 10, 100, and 1000. The gain equation is the sameas for external gain-setting resistors, but in higher gains, partof the lower gain-setting resistor is added to the feedbackresistor so the values shown for R

G can not be inserted

directly in the equation—see Figure 10.

The internal feedback resistors can be used with externalfeedback resistors. If the internal feedback resistors are usedwith external gain-setting resistors:

GAIN = 1 + (40k/RG)

Where:

RG = optional gain-setting resistor (Ω) connected between

G5 and G

14 with G

11 open

External gain-setting and feedback resistors can be used. Ifexternal feedback resistors are used:

GAIN = 1 + (2 • RFB/RG)Where:

RG = Optional external gain-setting resistor (Ω)

RFB = Optional external feedback resistor (Ω)

OPA111OPERATIONAL AMPLIFIER

The OPA111 slew rate is asymmetric with the positive-going slope faster than the negative-going slope (4V/µs vs2V/µs). Since the PSpice macromodel only allows asymmet-ric slew rate in the opposite direction, a conservative sym-metrical slew rate of 2V/µs was used in the macromodel.

OPA121OPERATIONAL AMPLIFIER

The OPA121 slew rate is asymmetric with the positive-going slope faster than the negative-going slope (4V/µs vs2V/µs). Since the PSpice macromodel only allows asymmet-ric slew rate in the opposite direction, a conservative sym-metrical slew rate of 2V/µs was used in the macromodel.

OPA660OPERATIONAL TRANSCONDUCTANCEAMPLIFIER AND BUFFER

This device includes a voltage-controlled current source anda voltage buffer. The voltage-controlled current source orOperational Transconductance Amplifier can be viewed asan “ideal transistor”. The transconductance of the OTA canbe adjusted with an external resistor, allowing bandwidth,quiescent current and gain tradeoffs to be optimized. Demoboards are available.

OPA675SWITCHED-INPUT OPERATIONAL AMPLIFIER

The OPA675 is a “classical” high-speed amplifier that hastwo differential input stages. Each stage is selectable withECL logic.

OPA676SWITCHED-INPUT OPERATIONAL AMPLIFIER

The OPA676 is a “clasical” high-speed amplifier that hastwo differential input stages. Each stage is selectable withTTL logic.

OPA2111DUAL OPERATIONAL AMPLIFIER

The OPA2111 slew rate is asymmetric with the positive-going slope faster than the negative-going slope (4V/µsvs 2V/µs). Since the PSpice macromodel only allows asym-metric slew rate in the opposite direction, a conservativesymmetrical slew rate of 2V/µs was used in the macromodel.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumesno responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to changewithout notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrantany BURR-BROWN product for use in life support devices and/or systems.

42

CO

NT

EN

T O

F M

AC

RO

MO

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LEV

EL

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TD

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INA

101

INA

102

INA

103

INA

105

INA

106

INA

110

INA

111

INA

114

INA

115

INA

117

INA

118

INA

120

INA

131

OPA

27O

PA37

OPA

77O

PA11

1O

PA12

1O

PA12

4O

PA12

8O

PA12

9O

PA13

1O

PA17

7

OP

A40

4O

PA

445

OP

A50

1O

PA

502

OP

A51

1O

PA

512

OP

A54

1O

PA

602

OP

A60

4O

PA

606

OP

A62

0O

PA

621

OP

A62

7O

PA

637

OP

A10

13O

PA

2107

OP

A21

11O

PA21

31O

PA

2541

OP

A26

04O

PA41

31

OP

T10

1O

PT

201

OP

T20

2O

PT

209

OP

T21

1

UA

F42

INA

101E

INA

102E

INA

103E

INA

105E

INA

106E

INA

110E

INA

111E

INA

114E

INA

115E

INA

117E

INA

118E

INA

120E

INA

131E

OP

A27

EO

PA

37E

OP

A77

EO

PA

111E

OP

A12

1EO

PA

124E

OP

A12

8EO

PA

129E

OP

A13

1EO

PA

177E

OP

A40

4EO

PA

445E

OP

A50

1EO

PA

502E

OP

A51

1EO

PA

512E

OP

A54

1EO

PA

602E

OP

A60

4EO

PA

606E

OP

A62

0EO

PA

621E

OP

A62

7EO

PA

637E

OP

A10

13E

OP

A21

07E

OP

A21

11E

OP

A21

31E

OP

A25

41E

OP

A26

04E

OP

A41

31E

UA

F42

E

AC

F21

01M

OP

A27

MO

PA

604M

OP

A62

8MO

PA

671M

OP

A67

5MO

PA

676M

OPA

2604

M

VC

A61

0M

BU

F60

0X1

BU

F60

0X2

BU

F60

1X1

BU

F60

1X2

BU

F63

4X

ISO

120X

ISO

121X

ISO

130X

MP

C10

0X1

MP

C10

0X2

MP

C10

2X1

MP

C10

4X1

OP

A60

3XO

PA

620X

OP

A62

1XO

PA

622X

1O

PA

622X

2O

PA

623X

1O

PA

623X

2O

PA

640X

OP

A64

1XO

PA

642X

OP

A64

3XO

PA

644X

OP

A64

6XO

PA

648X

OP

A65

0XO

PA

658X

OP

A26

58X

OP

A46

58X

OP

A66

0X1

OP

A66

0X2

TABLE XI. Content of the Macromodel Disk, Revision F, Listed by Topology Level and Directory. New models in bold.

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgment, including thosepertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated

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