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Burn InRolf-P. Vollcrtscn

Infincon TechnologicsCOIF.c/o IBM MD 967A1000 River Strcet, Essex Jui~ction,VT 05452 USAPhone: f 1 8(12 769 2823 Fax: t. 1 802 769 1220 E-mail : ro l f .vo l l e r~sc~~( ih~ t i e~n .com

AbstractBurn-In is us4 to swwn weak pabs rrom a popiilrtion o rcomplctcly p~oc esscd chips to assist in mceling rcliahililyrecluiretncnts. 'Iliis tulorial providcs a gcncrnl introduction to buin-in.It i s shown how burn-in improves thc railurc ratc. 'l'ypiarl bum-inconditions, thc bum-in models and an cxaniplc or failuremediatiistns are given. lhc impact of burn-in on techriologyrcliahiliiy (hol carriers, gate oxide, elcctiumigration) is d iscussed,cniphasiaiig that the uppcr limits o r the burn-in conditions can beconlrollcd by technology rdiability. linally ihc benefits ariddisadvnnlngcs a f huni-in arc summarivod.

lrltroductionJlurn-111(n1) s itwcT1 known proccdurc in the microclccironicsindustry. It was first used to scceeii dcrects in low-v olun ic irnm;itui.epans in thc sixtics [ I ] and was incoigoiated in thc railitary st;iridardsby 1968 11 M a y bum-in is a11 iidegrd part of thc microdcctroiiiccliip produclion. Tlweforc the rclalion of hui-ii-in, rclinbility anddcrecis is carcYu)ly iovcstigatcd aitd s u m m a r i d 114 1 1 l u r n - i ~ s iicost factor is idso included in nplimi7;ition considerations 19-12].

In this tutorial thc basics ot" bumin aic revicwed and thcpossiblc impact or hum-in OIL intrinsic tcchiiology reli;ibilily ispointcd out. As shown in slide 2 tlic tutoi'ial starts with n descriptiono f the iitcntion and method nl'bui-n-in. The hathtub ctnvc is uscd toilluslixle i x dcsiird effect of burn-in. 'lypical bum-in wmd itinns ;tiidtypcs arc given bcfm the burn-in inodeling is rwicwed. Then thcimpact of hum-in on Icchnology reliability is discuwd. The luloriiilconcludes with suniinary o r bcncfits aod disadvnntrtgcsor bu~n-iii.

Definition and MotivationQuin-in is a sewn method to climiiiaic defects in colnpleielyprocessed i n i a o c l ~ t r o n i cgarts atiliring accclcratcd aging hyapplying clcvaial operation conditions. -['he passing populationiisu;illy shows ail improved t'nihre raillc during enrly lire (slide 3). Themwtivahn fi,r buni-in and its impact arc best cxplaincd using thebathtub cuive slide 4-6). lhe cuivc in slide 4 WRS ctllculatd using

pamtuetcrs lhnt nicely m u l l in thc shape o r a bathtiih. Thc plot haslinear ;ixis with the instantancons fiiilurc rate or liamrd rate on theveitical and tinic 011 thc horixontal axis. 'Yypically three ditrcrentrcgioils can be distinguislicd: I'hc inrant mortality at shout timcs witillie clxracteristic rapidly &creasing failure mtc. Ibis portion isdesiicd 10 h rcmovcd, because it represents derccts and paiticlcs thatarc not scrccned in the initial tests a t linic zero (10). Once t lic h a m dratc itaclics l low lcvel thc uscful operating life region begins.During this period parts a i r cxpocled to fait with an almo st constiiritrate. The lcvcl o r the limard rntc dcpclnds o n proccss maturity ;ind is99 IRW FINAL REPORT

reduced by line 1e;iming. nuin-in is not cficicnt Tor irnpmving theicvcl of this rcgion. Ihc usefill life is lirnited by thc onset orwcrlroutwith B charactwisiic strong incrcasc or tbc h n m d ratc. W w o u tuliimatcly occurs dcpcndiq on tuchiology propzitics likcelcbmmigraiion, gatc oxide brwkdowh or hot crrricr degradation.?he orisct of wcalnut is uontrollod by dcsign and usc conditions.Usu~rl~yuchuology mod& arc appliccl to vciify that tlic onsd ofwenrout is wcll beyond tlic spccificd product lifclimc. jkpcnditig oilthc buni-in conditions Ihc wearout regicin triight bc dcgrtided hyhum-in as discussed Inter. Plotted willi log-scalcs instcad o f liricarscalcs llie lxithlub cuivc tcaiisforms to a VI-stiapeand it heconicsobvious that therc is 110 rcgion with a constant h iml ratc (slidc 7 ,The appropriatc bwn-iti conditions reduw: the hnmrd raw i n tlicinfant mortality region bcltiw thc failurc rale targel without ancciingtlic w e a m i t raiigc. Post burn-in a constant rnilurc ratc can bcobsci-vedat times sinalicr than thc cquivalcni b um-in time.

Burn-In Methods and Conditians13urn-In m;ry consist of two pai2s: Ibc warer-level huru-in andthe piickagc-level bum-in. lhe wafer-level burn-in 1131 is ilscd toirriprove packtlgc-level bum-in yicld tind avoid unneccssarypackaging o f bad chips. F urh im ore , some of the failing paits mayhe repai ra lk (redundmcy in DltAM3), which is not possiblc onpackage-lcvel (this changcs with Ihc intmductirm of clcclt'oriicCkiscs).Thus w ak r- le d burn-in retluccs cost. 1 owcvw, bccausc it generallyis pcrfo~mcd il il produdion tcsler, it weds to he vciy short. Also,

tcmpermrc is restricted to well below package-lcvcl hum-in.'Lhcicforcvoltrgc isusually iiicrcased ahovc thc package-level huni-in voltage atid special mcasures aiy: takcri to obtain bcser cfficicncy(duly Lxtor) than in package-Icvel buni-in.

The packagc-lcvcl hum-in assurcs reliability or the I ha lproducl (including chip package intcrachn) and is tcrditinnallymeiint by "bum-in". l hc pnckagcrl chips a1.e typically pluggcd intohuiii-in board that is thm placcd iii a Imum-in own. A hum-inscqucncc is shown in slide 9. R lest tcmpaatut'c vndous Icsts arcpcrCornicd. 'I'hcn b urn-in modc i s activatcd and the tcmpcrature israiscd lo burti-in coriditinn, n i which also thc vnltigc is iiicrcased andthc clock sltlrts to 1 ~ 1 1 . kpcnding on the rype of'hurti-in rciiabilityfails and esc;ipts may he dctcctcd during burn-in. There could hetcsts inlenuptiiig bum-in to gct a rcndout at nne or sevcixl pcrinls intime. ALkr cornplelion oT tI1c bum-iri (imc hias and tcmpenture a i tImitght lo iioiuinnl conditions ;iad final tests are performed. Forsoiiic burn-in types the runc.tionnl tests hcrorc, duviiig and nffcr hurii-in arc lhc only possibilities to dctcct fails. The following typcs o fhum-in are distinguishcd t2, 51: Tlic siinplc static bum-in (slide 10)r c k s 011 npplied bkrs mid tempcralurc ;S wcII as o n lhc tcsf hcforcniid alter 1mim-iii. llic input and outputt pins arc open and only thepowcr suppIy pins are wired. T l l i s simplc hoard dcsigii allowssbcssing or many lxins in parallcl nnd it i s thc lcnst cxpcnsivcconfiguration. 'Yhc drawback is tlxit noi al l nodcs or the circuit itre

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Vol lertsen TUTORIAL 1 C SUMMARY: Burn-Inburn-in tiinc of l OOD OD h (quivalcnt to one liretime) and bum-in ofthe complctc population results in ano thcr distrihution that is plo t td(dotled line). This is n typicd examplc fur tlic effect oi' screens onextrinsic distributions whether it is tlic product with tlic i n k o fdifferent failure rnechanisiils or a n extrinsic distribution from galeoxidc capacitors [14, 151. It is also interesting to iiotc from whichpatt of tlic original distribution the fails during lifetime a l b urn-incumc from. ombined, the two distrihution s rcsull in the "post burn-in" disliibntion. If tlic spccificd lifetime is lOOOOOli and thc postburii-in distribution ends up above thc target f:.lilui*c ate, additionidbum-in can improvc the failuic rate,TIowever,oiicc the failnrc riitc ntciid of lifc is controlled by the burn-in-cscapcs istribution additionalburn-in i s not uscful anymorc. In this cme Drily the rccluction o rcscapw helps.

cxcrcised and therc is no fccdback during burn-in, which rcsnlts inthc highest esape rate o f all burn-in types. 'I'lie dynamic bum-it1(slide 11) addresses thc potential problem of not all m d c s beingstressed, In addition til the raised voltage and tcmpcriiture, externalsigrials arc applied to the input pins that a r c wired in parallel for allchips. This requires full product functionality at bum-in conditionsbut itnpmvcs hum-in efficiency while cost arc still moderate andparallcl stressing o r many paits is casily possihIe. Still no reedbackfrom any chip during bum hin s available thus the escape ratc is stillhigh. Conscquetitly li~rtherrnpiwcmcnt is achicvcd by nionitoreddynamic bumin (sl idc 12) . In this case some limited rmponscmonitoring is perfoimed. Dcpcnding on the extent of monitoring thepartillcl strcssitig is limited and rhc equipment b w m c s morecxpensive. IYowever, the cscilpc ratc is rduccd. ?he most advancedtype of burn-in (slide 13-14) is the irisitu burn-in or ' l l) lU (Testi>uring Burn-In). It applics full hnc tion rl tesl paiterns and fullresponse monitoring for each individual chip. The advantage is thatcxnct failurc times and signatures m he de t c i mi nd as wcll i l sequipment or contact problems. Thus huui-in escapes can bemininiiGd an d ch ips thiit wcrc not cxpscd to bum-in voltage can berccyclcd. ' h e individual monitoring of ench chip limits tlic nuinhcro f parts thal can bc strcsscd 011 onc bum-in board and the r q u i a dequipment makes this type of burn-in morc cxpcnsivc.

Burn-in escapes and their root causes are suminarizcd in slidc15. Ihe rertsoii paits are not compktcly or ildcquatcly s ~ c s s douldbe due to lacking functionality at bum-in conditions, proceduralerrors and inadequate stress pattcins or annca l d fails [23.

'I'ypical burn-in conditions are givcn in slidc 16. Tlic voltage isusually 1 .3 to 1.7 timcs higher than the nominal voltagc. This alsoapplics to chip intcrnalvoltagcs which are generate on the chip. Thetemperature is raised to between 100C and 140'C. Besides 125C[ l ] also 14OoC is a well-established bu n- in temperature [8, 2, 31.The third parameter is the dumtion or bum-in, which plays animpoilant role because of cost aiid turn around timc. Fordevclopmcnt and cxly production thc duration ranges from 4511 o168h. There may be exccptions that require cvcli longcr tinics (e.g.parts Tor space or rnilitaiy applimtion). For maturc pruccsscs theburn-in time is reduced to 5h 1511.

Burn-In ModelingFor burn-in modeling, similar equations as for gate oxide arc

uscd (slidc 17) . For tcmpciyturc acccltmtion, rhc well-knownAdicnius equation is appiicd, and for thc voltiigc accclcration ancxponcntlnl rclatioti betwccn timc and volkqge is used [2, 5, 81. Inaddition, there i s an acccleration factor for mechanical strcss I2 thatis not considered here. The acceleraiion ,paramelen areexperimentally determined for each product and lechnology. TheWeibull distribution is accepted as prolxbility distribution (slide 18).It c m be shown that a power law represents an cxcellcntappioximation [Z] f only failure pcrccntlzgcs bclow 10% are ofinterest,which is almost always thc CISCIlie equation to describe the post burn-in distribution i s givcriin slidc 19 [7]. This equation applies to extrinsic and intrinsicdistiibutions. Another equation shows how bum-in escapcs are to bcconsidc1.d 12, 81. Thcsc cqmtions are applitxl in an example on slide20. In this arbitrary example 1% escapes are assumd which wsultsin a new, p arallel disiribulioii representing the escapes but two ordwso r magnitude below ihe original distribution. Assuming an quivalcri t

llurn-in fails arc a mixture o r vaiious failwc rncchiinisnis (slide21). 1 ne comp osition cliatigcs with product, e.g., gate oxidc t';iilswerc ii mairi contributor some lime ago [21. Today, shoits betweenmctiil lcvcls and contacts are domiuathig with cmphnsis 011 i11Wf1-level shorls. Anothcr incchnnisni are opens in the tnctiil l i i cs ntidcontacts. Almost no gAle oxide fails arc ohscrvcd. Sometimes chipcracks are idcn tificd. Photo litliogiwphy relatcd fails arc frrund oncein a white.

Impact of Burn-In on Technology ReliabilityAggressive scaling and pufoimance requirements rcclucc orclimiiiate m argins for technology rcliability. Too severe bum-in hasthe potential o f ;iffccting the lechnology reliability. Thc cquivaleiitburn-in t ime nonn alizd by thc lifetime specifica lioii is uscd lo showthe impact of bun- i n on product (extrinsic distribution) andteclinolugy rcliahility (wearout distributions) in slidc 22. Buin-in canmean the equivalcnt of multiplc lifctimes for the product, h u t alsomore than one liretimc for gntc oxide atid inore than a halrlifc f i r tlicdevices. ltie imnpiia on dcvicc reliability depends sbongly on the

device dmigti. 7 ic lmst impact can be expcLTal for cbctromigration(EhQ nd slrcss migration (or strcss voiding).

Thc possible impact on inbinsic disti-ibirtions is illustratd itislidc 23. Dcpcnding on the burn-in coiiditirins thl: failurc rale may besigniticanlly increased. The cffwt is basically the same for gatetrxidc and EM (nlthough Cor EM , uswlly a log-rioimnl distribution isused). The hazard ratc plolled versus tiinc (slidc 24) rcvcals aconsfant rntc of fails berorewearout incrcascs tlic failurc rate. l r thelevel o r thc constant fallout is well below targct it docs not affoctproduct reliability. At a high level, however, i t causes violalion or lheproduct reliability tnrgct and the burn-in conditions nccd to bemoderated to avoid the d;itnagc.For hot camiers, burn-in i s considwd by inroduction of anadditional biirn-in equivalent timc. This tinic i s derived from thcdegradation at bum-in conditions and the modd for dcgndation at

use condition (slidc 2 5 . In slide 26 an example for devicedegradation at buix-in aiid use condilions is shown. The degradtitioiibehavior at usc cmditions ailer burn-in is iilsu plottcd. Again, burn-iti is n clear adder up to long tiincs, whcrc the deg~adatioii t usccondilioris dominates. nata confiimiug this iiiodcl arc rcpoileed in thiswoikshop [16],111summary, the impact of hum-in an technology rcliability(wwrout) may barely bc dc t cc t d during burn-in (slide 27). If hutm-iri

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TUTORIAL 1C SUMMARY: B u r r i hconditions havc an inipact on wcaniut it may hc sccn late in productlifc m l y and manifcst itselC hy ;in increased cumulative failure rate a tcnd of lire. To v c d y with product tliiit tin wearout meclianisni isprcscnt requircs 50Oh-lOUUh of stress at burn-in conditions. Inconsequence, thc opliini7aUnn of burn-in conditions for tlic bcstscrmn cfficiency nwds to coiaidcr the potential irnpaci o n wcai.out.

Vollertscn

ConclusionThc bcnefts of hum-in aiv obvious (slidc 28). Desidcs thescreening of wcak pails and licnce inipmving tbc carly ficld railureratc it allows for spccial tests with long duration, which cannot h cdnnc o n expensivc testers. It is at1 cxcelleiit monitor orthc line ou tpu~and drivcs pioccss improvcmcnts due to failure mechanism fecdback.Rum-in is thc ultimate product rcliabjlity tcst mid gencratcs animpressive statistical database. Hnwever, hutn-in also has itsdisadvantages (slidc 29) like zidditional luin around timcs and highcost. Ibc latter depends on thc complexity of the parts and the bum-in mcthod. T h c s a potcntial for induced damage, c.g., ES1) o rotlmr kindling relatcd damage. For ctq-tain products hum-in might h einefficient 111

Rcgardlcss how succcss&l burn-in is in improving carly ki lurcrates; it ages parts ;md it does not improvc h e quality or reliability oftlic pails that survive bum-in. Thcicfcrcunncccssatybur-n-in must beavoidcd. The burn-in conditions musl bc carelully clioscri to precludcdcgmdation of inldnsic tcclmology rclinbilily.

AcknowledgementRcvicw o r the manuscript by Andw Iorcier (mM I)) i s gntcfullyacknowldgcd.

AefcrencesM. ci. Pcdit,R. Radojcic, i . Itno, Cruidihok for managingsilicon chip reliability, CKC Prcss, 1998, p. 184D. 1,. Ihompson,It. It. Wood, Semiconductor Defect RcliabilityModeling, IFiI~li IWS Tutorial Notes 1996, pp. 1a . I - la.39A. J. Wager, Stmiconductor Dcfkt Rcliability Scrcening andModcling, TEIY; lRPS Tutorial Notes 1996, pp, 1b. l - 1b.39C . G . Shirley, A Dcfect Modcl ofI(eliahility, E li I

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Vo l l e r t se i i Bathtub curveCalculaled exemple bathiub curve

I

Bathtub curve definitionsInfant mortality (rapidly decreasing failure rate)- defects (litho, etch, misalignment, scratches),- passes time-zero test(s)- removed by Bum-In- passes time-zero test@) and Burn-In-failure rate level depends on process maturity and

part icles

Useful (operating) life IOW failure rate)

decreases with line learningJ

Definit ons con .Wearout (increasing failure rate)

Ultimately occurs, limits useful life- onset depends on technology properties (hot carrierdegradation, gate oxid e breakdown,electromigration), design and use conditions- requires models lo verify that onset iswell beyond specified product life

Bathtub curve on log scaleCaIculaled ~ Y a m p l i d h b b tuwn.. and I d e a N m 4 n

. .i in im imo l o r n i m m imrmo

Urn. ih]

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TUTORIAL 1 C SUMMARY: Brim.liiBum-In procedure

Wafer level Burn-In- improves package-level Burn-In yield

l lows repairs- voltage acceleration and more efficient duty

factor on ester ==> short time)- usually identified with "Burn-In"- packaged chips on Burn-In boardsPackage-level Burn-In

Bum-In sequence1 Stress and insitu t es t

dBurn-In timeTimeTypes of Burn-In

Simple static: application o f increased biasand temperature, pre- and pos l Burn-Infunctional tests at nominal condit ionsc allows parallel stressing of many parts+ relatively low cost- stress not applied to all nodes- no feedback during Burn-In (highest escape

rate)I O

6

a

9

Types of Burn-In (cont.)Dynam ic: application of increased bias,temperature and external inputs (clocks, randomdata or full test patterns), pre- and posl Burn-Infunctional tests at nominal conditions+ allows parallel stressing o f many parts+ relatively low costo stress may reach all nodes (depends on test

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TUTORIAL 1 C SUMMARY: Burn-In Voller sen

Types of Burn-ln (cont.)Monitored Dynamic; application of increasedbias, temperature, external inputs and someresponse monitoring , pre- and post Burn-Infunctional iests at nominal conditionso parailel stressing of parts limited- expensiveo stress may reach all nodes (depends on test

pattern)o feedbackduring Burn-In (lower escape rate)

I 1

Types of Burn-In (cont.)In situ or TDBl (Test During El): application ofbias, temperature, full functional test patternsand full response monitoring, pre- a nd postBurn-In functional tesls at nominal conditionsfull product functionality at Burn-In conditions+ axact failure times+ finds equipment or contact problems+ identifies unique fails during stress2 minimizes Burn-In escapes

13

Typical Burn-ln conditionsVoltage: 1 .3 1.7 times higher than nominalTemperature: 1 C ... 140CDuration:- development early production: 45h - 168h- mature process: 5h - 15h

Burn-in modelingTemperature acceleration ATAT= t,/t>= eXp{ E,/k X (1/T, - IIT,)}

Voltage acceleration A,A= t,/ t2= exp{ p x (V, - V,)}E and p are technology dependent andexperimentally determinedTotal Bt acceleration: A = AT AV

17

Types of Burn-In escapesEscapes: components not being completely o radequately stressedFunctional: limited or no functionality at Burn-Incond tions b l o cks stress)Operational: incomplete or inadequate stress(bad connector. bypass BI), human errorPattern: not all nodes accessed by patternRecovered fail: anneals before post Burn-In testAcceleration: insufficient accelerated mec hanism

Types of Burn-In (cant.) Burn-In modeling (cont.)In situ (co nt.)-tstress reaches all nodeso parallel stressing of parts limited- most expensive

Failure distributionWeibullF(t) = 1 - exp(-{t tS3,2Sb)b)Approximation for small percentages 4 )F t)= a x tbslope b is the same for both cases

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Burn-In modeling (cont.)Cumulative failure of components post Burn-In

Consideration of Burn-In EscapesFpBlies(f) = P FU) (1 - P I F&p: percentage o f escapes (0 p 1)

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Voller tsen TUTORIAL C SUMMARY: Burnln

Burn-In modeling(arbitrary example)

~p k 4 a r . la s m mnw. I

TypicaI Fa ure mechanismsShorts (inter and intra metal levels and tocontacts)Metal line and contact opeos

Rarely:Gate oxide defectsChip cracks (packaging related)Litho re lated fails

t

Impact of Burn-In on intrinsictechnology properties

Impact of Burn-In on wearoutdistributions (gate oxide, EM}

Impact of Burn-In on wearoutdistributions (gate oxide, EM)..

Impact of Burn-In on DevicesN E T peak l S u b conducting HC degradation

Impact of Burn-In on DevicesI

Impact of Burn-In on intrinsictechnology propertiesNo wearout fails may be detected in h i -n-InNowearout fails may occur during early lifeImpact may occur late in product life time=r may increase failure rate at EOLAbsence-of-wearoutverification on productrequires 500h-1OOOh stress at Burn-Inconditions

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TUTORIAL I SUMMARY: Bu rw lnBurn-In Benefits

Screen of weak parts (improv es field failureSpecial tests possible (long duration tests)Monitorof line output (maverick control)

rate)

Process improvement by failure mechanismfeedbackUltimate reliability test (product is final arbiter)Statistical database

Volterisen

DisadvantagesHigh cost (depends an complexity of part andAdditional turn around timePotential for induced damageFor same products inefficientBum-Inages parts, it does not improvequality Or reliability of parts that pass

avoid unnecessary Burn-In

Burn-In method)

292a

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