Burkard ReisertJune 11th , 2004

Fermilab, High Rise, Hornet Nest

Pulsar Meeting

Ted’s overview talk:• Pulsar production/testing success ! all hardware in place (see Burkard’s talk)• New VME DAQ readout code in place (see Jane and Burkard’s talk)• Pulsar crate almost FULL platform for integration in place (see Burkard’s talk)

Lots of stuff to cover:

Title on Agenda: Muon/XTRP/L1/SVT/Merger readiness

Ted’s email: Beam tests coordination.   "In God we trust, everything else we test with beam"                   come up with plans on how to do this.                  train people to rotate on weekly bases... all requests coordinate with trigger SPLs.                  setup web page for instructions...etc.                  plans... train people in the next few weeks for all data paths.                  start rotation by end of month.

Test Stand for Production Testing

TS

L1

L1Mezz.

Mezz.

Mezz.•VME access•Internal RAM and SRAM•Internal com.•TS interface•SVT/XTRP•L1 Signals•Mezzanine card Interface•Slink Interface

AUX

Tx Rx

Mezz. SVT/XTRPSLINK

Production batch: 45 boards43 delivered (2 more to be assembled)24 w/o P3 connector

15 boards w/o P3 available for SVT all boards passed Pulsar test stand test and SVT RW test stand tests (~10 boards w/ P3 have been tested for SVT as well)

5 out of 43 had minor problems 2 already fixed, 2 @ HR, 1 demo for Zita Young (our summer student)

Very successful production & testing

PULSAR Production Testing (~Last Month)

Up to 9 boards tested per day

Test of Slink formatter on Muon board:- standalone (with Pulsar Tx) March- in beam (Muon input splitted, DAQ readout for Muon and Merger Input) April- release Slink formatter for use on other paths April

SLink Formatter & Slink Merger(schedule as given on 03/12/04, revisited 04/22/04)

Beam Test of Slink Merger:- Merge Muon Slink package with other Slink inputs DAQ readout of Merger inputs and outputs May - Platform for system integration in June

Working hard to make it happen

Conclusion: on Track

Slink Tx for now

Some data recorded, but not looked at

It’s coming !

Move test stand setup to Pulsar crate in Trigger roomInput to Muon Pulsar: split muon signals and Pulsar XTRP Test pattern Enable one input on Slink Merger Some DAQ issues: - FER code overwrites SLink input enable register - only 2 fiber inputs per FPGA FER expects 8 work around: use standalone Pulsar VME code to - load proper values manually in RC CONFIG state - Dump Muon and SLink DAQ RAMs in RC HALT stateCosmic and L2 Torture runs look promising

muon fibers

Muon Rx

Muon & Slink Merger Installation in Trigger Room

SLink Merger

XTRPSLink

formatterXTRPTx

L2 Muons

CDFRunIIa

“”

April21th

muon fibers Muon Rx

April 22nd Status in Trigger Room

SLink Merger

XTRP

XTRPTx

L2 Muons

CDFRunIIa

“”

16/48 RECES

Reces Rx

Cluster Rx

CList &IsoList

Muon RxL2 Muon Merger

Reces RxReces input DAQ Output SLink Tx

Cluster RxCluster input DAQ Output SLink Tx

Plan for next week:-- solve DAQ issues-- go for Cosmic, L2Torture & Beam

Fibers aresplit

DAQ issues: Why we needed a new Readout?

Readout of 1 board takes 0.7 ms ! Why?

1 board full cycle

2 boards full

Data volume Front end readout: Overhead

~ 5 s block transfer setup time~ 0.5s/wordSame as most CDF boards (hadron TDC is twice as fast)

Newparameters

Dial number of words per DAQ RAMBoard level Readout listDeal with remapped Fiber Input DAQ

Solution: more flexible Readout Configurartion:

C0

C1

D1 0

D1 1

D2 0

D2 1

Muon var var 256 --- 256 ---

Reces 21 --- 16 --- 16 ---

SVT var var (var) --- ---- ---

Cluster var --- 8*64 --- 8*64 ---

Merger var --- var var var (var)

L2toTS --- --- var --- --- ---

Thanks to Bill & Jane

While new DAQ code was developedWe made use of COT downtime during store read two boards

Muon RxSLink Merger

XTRP

L2 Muon

Slink Tx

XTRP Tx

Compare:

Muon Output Slink Merger (input & output)Test pattern Slink Merger (input & output)

50k events 0 errors ready to distribute Slink Formatter

Beam test of Slink Merger

Firmware factoryLVDS Fanoutboard

L1

L1

L1SVT

XTRP

TS

Clist

These guys have been busy as beeswhile the new DAQ code was developed.

Pulsar methodology at work at its best:

Testing of the new DAQ Code

Reces RxSLink Merger

SVT

SVT Rx

Reces TxSVT Tx

Reces Fibers

SLink Tx

Enjoy the flexibilityof the newreadout code

e.g.: readout1,2,3 Pulsars1,2,6 Buffers etc..

Add some features,fix some bugs

ready for prime time!

Pulsar Crate in Trigger Room

B0L2PU00

Muon(w/o L1)

XTRP

L2 Muons

Run IIa Level 2 Decision Crate

- Processor

1/3 RECES

Reces

Cluster

SVT

SVT

CL

ist Master

CListISOList

Merger SlinkRx

PulsarTx

B0L2PU00

Level2_Pulsar_00

Tx

crate is filling up

(= SVT DataIO)

TRACER

SVT

RECES

CLUSTER

SLINK

MERGER

CRATE

CPU

TRACER

MUON

/

XTRP

SLINKRX

SVT

RECES

CLUSTER

TX

RECES&SVT

SLINK

MERGER

SLink

Tx

CRATE

CPU

TRACER

MUON

L2TS

?

CLUSTER

RECES

SVT

CRATE

CPU

RECES

RECES

RECES

MERGER

MUON

/

XTRP

L2TS

?

Future Pulsar crate (one possible config.) Present Pulsar Crate

RECES

XTRP

RECES

Pulsar Transmitter crate Boards w/o P3 fit in “Bottom ” crate

We have• Hardware (Pulsars, Mezz., Aux. fiber & LVDS splitters)• the DAQ Code (new TP2D)• the Monitoring frame work

We need • to test all Firmware in beam• to do system level tests• to make a plan

Crates are filling up

Beam tests coordination:    "In God we trust, everything else we test with beam“ With beam? Yes with beam! (parasitically of course ) 

Ted’s charge to me: “Come up with plans”

BR: “Learn from the past”

CDF RunIIa (our legacy at CDF): “Level 2 pager carrier” That is exactly as much as I can do for the present system, carry the pager (more or less) H1@HERA (my previous experiment): “Expert on call”

Note the differencein attitude !

1st attempt on a plan of three phasesTime we spent in beam

100%

Single board tests:Need access to debug connectors on the boardFirmware completion: L1, PreFred, Cluster Algo

now

Aug ??th

“Online” Monitoring Monitoring massagingHigh stat System level tests, Firmware massaging (performance)

Fill up the crate:System level testsSingle board high statstic Firmware massaging (make it work)Monitoring Completion

Hardware/Firmware

End of June

4th July

End of July

PC

PC receivesbeam data (incomplete event)

PC returnssomething

Pulsar Level2 triggers on CosmicsWhat will we be able to do in beam?

I know all this is common knowledge, but worth spelling it out

Motivation: “I want to be an expert” “I want to know more than just my system”

Education: Teaching = share knowledge Learning = spent time on the system try things out Training = do it all over again

Communication (means of communication): group: informal meeting (Tue), bi-weekly meeting (Fr), email point-to-point: list of phone numbers, cell phones are superior to pagers

Documentation: e-log entries HowTo pages for useful tools and trouble shooting Informal & CDF notes Celebration: have fun