building memory from logic gates
DESCRIPTION
Building memory from logic gates. 1. 1. B. Q. What happens when the input, A, is pulsed as shown? When the pulse is removed, the outputs remain in their new state. 0. 1. 1. Q. A. 0. 0. 1. 0. 0. B. Q. 1. Feedback. 1. 0. Q. 0. A. 1. 0. Type “D” Flip-Flop. S. D. Q. - PowerPoint PPT PresentationTRANSCRIPT
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 1
Building memory from logic gates
1
1
1
Q
Q
0
1
0Q
Q
0
0 1
0
1
0
0
1
0
1
• What happens when the input, A, is pulsed as shown?• When the pulse is removed, the outputs remain in their new state
• What happens when the input, A, is pulsed as shown?• When the pulse is removed, the outputs remain in their new state
A
A
B
B
FeedbackFeedback
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Type “D” Flip-Flop
• Design to change its output state synchronously with a clock signal input- State of signal on the D input (data) is transferred to the Q
output on the rising edge of the clock- Set/Reset inputs are asynchronous
D
CLK
S
R
Q
Q
RESET=0 ( Q > 0)
SET=0 ( Q > 1 )
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11Timing Diagram
S
R
D
CLK
Q
Q
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Inside the “D” Flip-flop
Try this out on your Digital Simulator. It works!Try this out on your Digital Simulator. It works!
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The ‘D’ flip-flop divides by two
D
CLK
S
R
Q
Q
1
1
CLK
D
Q
/Q
• The /Q output is fed back to the D input• Ignoring propagation delay, the Q output after the rising edge of the clock agrees with the D input before the rising edge of the clock.• The waveform at the Q output has twice the period (half the frequency) of the waveform at the clock input.
Rising edges
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Cascading D-FFs
clock
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The “D” FF as a counting element• A 16-bit binary ripple counter
• Given the name because the pulses “ripple” through the circuit
Clock in
S
R
D
CLK
Q
Q
S
R
D
CLK
Q
Q
S
R
D
CLK
Q
Q
Q1 Q2 Q3
1
RESET
S
R
D
CLK
Q
Q
Q0
• Each “D” FF divides the incoming clock frequency by 2X• RESET sets all Q output to 0 without a clock signal (asynchronous)• Counts as fast as the first stage can toggle, but cannot be read until the count has rippled through to the last stage • Can build counter/dividers of any length, any binary divisor
• Clock frequency at output Q3 equals fClock in ÷ 16
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Waveform of a 16-bit counter
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“D” FF as a shift register
S
R
D
CLK
Q
Q
Q0
S
R
D
CLK
Q
Q
Q1
S
R
D
CLK
Q
Q
Q2
S
R
D
CLK
Q
Q
Q3
Shift data in
1
Shift data out
Clock in
RESET
• Shift register moves data through successive stages on each clock pulse• Used for serial data communications, multiplication ( why ?), image processing• Basis for UART ( Universal Asynchronous Receiver/Transmitter )• Data can be read in serially and then read out in parallel• Serial data communications limits the number of signal wires needed to transmit bytewide• data ( Example shown here is a nibble )
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Serial data transmission
most significant bit 0 1 1 0 least significant bit
DATA
CLOCK
• The data value is synchronized with the rising edge of the clock.• One rising edge (clock pulse) is required for each data bit being
transmitted• In this example the data is transmitted most significant bit to
least significant bit
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Waveform for the shift register
D
Q0
Q1
Q2
Q3
CLK
0
1
1
0
t1 t2 t3 t4
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“D” flip-flop as a storage register
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D0
D7
D1
D3
D2
D4
D5
D6
Q0
Q7
Q1
Q3
Q2
Q4
Q5
Q6
Clock in
D0 D1 D2 D3 D4 D5 D6 D7
INPUT DATA OUTPUT DATA
D0 D1 D2 D3 D4 D5 D6 D7
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An 8-bit storage register
D0
D7
D1
D3
D2
D4
D5
D6
Q0
Q7
Q1
Q3
Q2
Q4
Q5
Q6
Clock in
D0 D1 D2 D3 D4 D5 D6 D7
INPUT DATA OUTPUT DATA
D0 D1 D2 D3 D4 D5 D6 D7
8-bitStorage Register
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State representation of a ‘D’ FF
• Can best represent the design of state machines with a table or a graphical description ( ignore the asynchronous set/reset inputs)
• Assume the transitions occur on the rising edge of clk
D
CLK
Q
Q
Current Current Next Input State State
D Q Qn
00 0
1 1 1
01 1
0 1 001 10
0
1
input
State
10
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State machine for a 4-bit counter
0000000100110100
0101
0110
0111
1000
1111
1100101110101001
0010
1110
1101
• No matter what state you start from, the next state is always determined• If RESET were made synchronous, we would add an arrow from every state back to 0000.
• No matter what state you start from, the next state is always determined• If RESET were made synchronous, we would add an arrow from every state back to 0000.
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4-bit memory array
Memory Cell Address
0 0 0 01 0 0 00 1 0 01 1 0 00 0 1 01 0 1 00 1 1 01 1 1 00 0 0 11 0 0 10 1 0 11 1 0 10 0 1 11 0 1 10 1 1 11 1 1 1
Memory cell data
Ain
Bin
Cin
Din
Aout
Bout
Cout
Dout
16 by 4 memory array
ADDRESS INADDRESS INDATA OUTDATA OUT
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State Machine
The output values in the register is the address of the memory cell for the data that determines the next state of the outputs after the clock arrives
The output values in the register is the address of the memory cell for the data that determines the next state of the outputs after the clock arrives
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CLK
D0
D1
D2
D3
A0
A1
A2
A3
16 x 4 Memory Array
Q0
Q1
Q2
Q3
REGISTER
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Why do we need the D flip-flop?Case A
D Q
clk
Clock input
A B C
BA C
D FFD FF
Case B